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Agilent HCPL-3140/HCPL-0314 0.4 Amp Output Current IGBT Gate Drive Optocoupler
Data Sheet
Functional Diagram
N/C
1
8
VCC N.C.
Truth Table
LED OFF VO LOW HIGH
ANODE CATHODE N/C
2 3 4
7 6 5
VO VEE
ON
SHIELD
HCPL-3140/HCPL-0314
Description The HCPL-3140/HCPL-0314 family of devices consists of a GaAsP LED optically coupled to an integrated circuit with a power output stage. These optocouplers are ideally suited for driving power IGBTs and MOSFETs used in motor control inverter applications. The high operating voltage range of the
output stage provides the drive voltages required by gate controlled devices. The voltage and current supplied by this optocoupler makes it ideally suited for directly driving small or medium power IGBTs. For IGBTs with higher ratings, the HCPL-3150 (0.5 A) or HCPL-3120 (2.0 A) optocouplers can be used.
Features * 0.4 A minimum peak output current * High speed response: 0.7 s maximum propagation delay over temperature range * Ultra high CMR: minimum 10 kV/s at VCM = 1 kV * Bootstrappable supply current: maximum 3 mA * Wide operating temperature range: -40C to 100C * Wide VCC operating range: 10 V to 30 V over temp. range * Available in DIP8 and SO8 package * Safety approvals: UL approval pending, 2500 Vrms for 1 minute. CSA approval pending. VDE approval pending VIORM = 630 Vpeak (HCPL-3140) Applications * Isolated IGBT/Power MOSFET gate drive * AC and brushless DC motor drives * Inverters for home appliances * Industrial inverters * Switch Mode Power Supplies (SMPS)
A 0.1 F bypass capacitor must be connected between pins VCC and V EE.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information Specify part number followed by option number (if desired). Example :
HCPL-3140#XXX No option = Standard DIP package, 50 per tube. 300 = Gull Wing Surface Mount Option, 50 per tube. 500 = Tape and Reel Packaging Option. 060 = VDE 0884, VIORM = 630 VPEAK. HCPL-0314#XXX No option = SOIC-8 surface mount in tube, 100 per tube. 500 = Tape and Reel Packaging Option. 060 = VDE 0884, VIORM = 566 VPEAK.
Package Outline Drawings HCPL-3140 Standard DIP Package
9.65 0.25 (0.380 0.010) TYPE NUMBER 8 7 6 5 7.62 0.25 (0.300 0.010) 6.35 0.25 (0.250 0.010)
OPTION CODE* DATE CODE
A XXXXZ YYWW 1 1.19 (0.047) MAX. 2 3 4
1.78 (0.070) MAX. + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002)
5 TYP. 4.70 (0.185) MAX.
0.51 (0.020) MIN. 2.92 (0.115) MIN. DIMENSIONS IN MILLIMETERS AND (INCHES). 1.080 0.320 (0.043 0.013) 0.65 (0.025) MAX. 2.54 0.25 (0.100 0.010) * MARKING CODE LETTER FOR OPTION NUMBERS. "V" = OPTION 060 OPTION NUMBERS 300 AND 500 NOT MARKED.
2
HCPL-3140 Gull Wing Surface Mount Option 300 Outline Drawing
PAD LOCATION (FOR REFERENCE ONLY) 9.65 0.25 (0.380 0.010)
8 7 6 5
1.016 (0.040) 1.194 (0.047)
4.826 TYP. (0.190) 6.350 0.25 (0.250 0.010) 9.398 (0.370) 9.906 (0.390)
1
2
3
4
1.194 (0.047) 1.778 (0.070) 1.780 (0.070) MAX. 9.65 0.25 (0.380 0.010) 7.62 0.25 (0.300 0.010)
0.381 (0.015) 0.635 (0.025)
1.19 (0.047) MAX.
4.19 MAX. (0.165)
+ 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002)
1.080 0.320 (0.043 0.013) 0.635 0.130 2.54 (0.025 0.005) (0.100) BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
0.635 0.25 (0.025 0.010)
12 NOM.
HCPL-0314 Small Outline SO-8 Package
8
7
6
5
3.937 0.127 (0.155 0.005)
XXX YWW
5.994 0.203 (0.236 0.008) TYPE NUMBER (LAST 3 DIGITS) DATE CODE
4
PIN ONE 1 0.406 0.076 (0.016 0.003)
2
3
1.270 BSG (0.050) * 5.080 0.127 (0.200 0.005) 7 0.432 (0.017)
45 X
3.175 0.127 (0.125 0.005)
0 ~ 7 1.524 (0.060) 0.203 0.102 (0.008 0.004)
0.228 0.025 (0.009 0.001)
* TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
5.207 0.254 (0.205 0.010) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.
0.305 MIN. (0.012)
3
Solder Reflow Temperature Profile
300
PREHEATING RATE 3C + 1C/-0.5C/SEC. REFLOW HEATING RATE 2.5C 0.5C/SEC. PEAK TEMP. 245C PEAK TEMP. 240C PEAK TEMP. 230C 2.5C 0.5C/SEC. 160C 150C 140C 3C + 1C/-0.5C 30 SEC. 30 SEC. SOLDERING TIME 200C
Regulatory Information The HCPL-3140/HCPL-0314 are pending approval by the following organizations: VDE Approval under VDE 0884/06.92 with VIORM = 630 Vpeak (HCPL-3140) and 566 Vpeak for HCPL-0314. UL Approval under UL 1577, component recognition program up to VISO = 2500 Vrms expected prior to product release. File E55361. CSA Approval under CSA Component Acceptance Notice #5, File CA 88324 expected prior to product release.
TEMPERATURE (C)
200
100
PREHEATING TIME 150C, 90 + 30 SEC. 50 SEC. TIGHT TYPICAL LOOSE
ROOM TEMPERATURE
0
0
50
100
150
200
250
TIME (SECONDS)
VDE 0884 Insulation Characteristics (HCPL-3140 Option 060)
Description Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage 150 Vrms for rated mains voltage 300 Vrms for rated mains voltage 600 Vrms Climatic Classification Pollution Degree (DIN VDE 0110/1.89) Maximum Working Insulation Voltage Input to Output Test Voltage, Method b* VIORM x 1.875=V PR, 100% Production Test with tm =1 sec, Partial discharge < 5 pC Input to Output Test Voltage, Method a* VIORM x 1.5=V PR, Type and Sample Test, tm =60 sec, Partial discharge < 5 pC Highest Allowable Overvoltage (Transient Overvoltage tini = 10 sec) Safety-limiting values - maximum values allowed in the event of a failure. Case Temperature Input Current** Output Power** Insulation Resistance at TS, VIO = 500 V V IORM VPR Symbol Characteristic I - IV I - III I-II 55/100/21 2 630 1181 Vpeak Vpeak Unit
VPR VIOTM
945 6000
Vpeak Vpeak
TS IS,INPUT PS, OUTPUT RS
175 230 600 >10 9
C mA mW
* Refer to the optocoupler section of the Isolation and Control Components Designer's Catalog, under Product Safety Regulations section, (VDE 0884) for a detailed description of Method a and Method b partial discharge test profiles. ** Refer to the following figure for dependence of PS and I S on ambient temperature.
4
OUTPUT POWER - PS, INPUT CURRENT - IS
800 700 600 500 400 300 200 100 0 0 25 50 75 100 125 150 175 200 PS (mW) IS (mA)
TS - CASE TEMPERATURE - C
Insulation and Safety Related Specifications
Parameter Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Plastic Gap (Internal Clearance) Symbol L(101) HCPL-3140 7.1 HCPL-0314 4.9 Units mm Conditions Measured from input terminals to output terminals, shortest distance through air. Measured from input terminals to output terminals, shortest distance path along body. Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1)
L(102)
7.4
4.8
mm
0.08
0.08
mm
Tracking Resistance (Comparative Tracking Index) Isolation Group
CTI
>175 IIIa
>175 IIIa
V
Absolute Maximum Ratings
Parameter Storage Temperature Operating Temperature Average Input Current Peak Transient Input Current (<1 s pulse width, 300pps) Reverse Input Voltage "High" Peak Output Current "Low" Peak Output Current Supply Voltage Output Voltage Output Power Dissipation Input Power Dissipation Lead Solder Temperature Solder Reflow Temperature Profile Symbol TS TA IF(AVG) IF(TRAN) VR IOH(PEAK) IOL(PEAK) VCC -VEE VO(PEAK) PO PI -0.5 -0.5 Min. -55 -40 Max. 125 100 25 1.0 5 0.6 0.6 35 VCC 250 105 Units C C mA A V A A V V mW mW 3 4 2 2 1 Note
260C for 10 sec., 1.6 mm below seating plane See Package Outline Drawings section
5
Recommended Operating Conditions Parameter Power Supply Input Current (ON) Input Voltage (OFF) Operating Temperature Symbol VCC -VEE IF(ON) VF(OFF) TA Min. 10 8 - 3.0 - 40 Max. 30 12 0.8 100 Units V mA V C Note
Electrical Specifications (DC) Over recommended operating conditions unless otherwise specified. Parameter High Level Output Current Low Level Output Current High Level Output Voltage Low Level Output Voltage High Level Supply Current Low Level Supply Current Threshold Input Current Low to High Threshold Input Voltage High to Low Input Forward Voltage Temperature Coefficient of Input Forward Voltage Input Reverse Breakdown Voltage Input Capacitance Symbol IOH IOL VOH VOL ICCH ICCL IFLH VFHL VF DVF/DTA BVR CIN Min. 0.2 0.4 0.2 0.4 VCC-4 Typ. 0.5 0.4 0.5 VCC -1.8 0.4 0.7 1.2 Max. Units A A V V mA mA mA V 1.5 -1.6 1.8 V mV/C V 60 pF IF = 10 mA 16 Test Conditions Vo = VCC- 4 Vo = VCC-10 Vo = VEE+2.5 Vo = VEE+10 Io = -100 mA Io = 100 mA Io = 0 mA Io = 0 mA Io = 0 mA, Vo>5 V Fig. 2 3 5 6 1 4 7,8 9,15 Note 5 2 5 2 6,7 14
1 3 3 7
0.8 1.2
5
IR = 10 A f = 1 MHz, VF = 0 V
6
Switching Specifications (AC) Over recommended operating conditions unless otherwise specified. Parameter Propagation Delay Time to High Output Level Propagation Delay Time to Low Output Level Propagation Delay Difference Between Any Two Parts or Channels Rise Time Fall Time Output High Level Common Mode Transient Immunity Output Low Level Common Mode Transient Immunity Symbol tPLH tPHL PDD Min. 0.1 0.1 -0.5 Typ. 0.2 0.3 Max. 0.7 0.7 0.5 Units s s s Test Conditions Rg = 47 , Cg = 3 nF, f = 10 kHz, Duty Cycle = 50%, IF = 8 mA, VCC = 30 V Fig. 10,11, 12,13, 14,17 Note 14
10
tR tF |CMH| |CML|
50 50 10 10
ns ns kV/s kV/s
TA = 25C, VCM = 1 kV
18 18
11 12
Package Characteristics Parameter Input-Output Momentary Withstand Voltage Input-Output Resistance Input-Output Capacitance Symbol VISO RI-O CI-O Min. 2500 Typ. Max. Units Vrms pF Test Conditions TA=25C, RH<50% for VI-O=500 V Freq=1 MHz Fig. Note 8,9 9
1012 0.6
Notes: 1. Derate linearly above 70C free air temperature at a rate of 0.3 mA/C. 2. Maximum pulse width = 10 s, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak minimum = 0.4 A. See Application section for additional details on limiting IOL peak. 3. Derate linearly above 85C, free air temperature at the rate of 4.0 mW/C. 4. Input power dissipation does not require derating. 5. Maximum pulse width = 50 s, maximum duty cycle = 0.5%. 6. In this test, VOH is measured with a DC load current. When driving capacitive load VOH will approach V CC as I OH approaches zero amps. 7. Maximum pulse width = 1 ms, maximum duty cycle = 20%. 8. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage 3000 V rms for 1 second (leakage detection current limit II-O 5 A). This test is performed before 100% production test for partial discharge (method B) shown in the VDE 0884 Insulation Characteristics Table, if applicable. 9. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together. 10. PDD is the difference between t PHL and tPLH between any two parts or channels under the same test conditions. 11. Common mode transient immunity in the high state is the maximum tolerable |dVcm/dt| of the common mode pulse VCM to assure that the output will remain in the high state (i.e. Vo > 6.0 V). 12. Common mode transient immunity in a low state is the maximum tolerable |dV CM/dt| of the common mode pulse, VCM, to assure that the output will remain in a low state (i.e. Vo < 1.0 V). 13. This load condition approximates the gate load of a 1200 V/25 A IGBT. 14. The power supply current increases when operating frequency and Qg of the driven IGBT increases.
7
(VOH-VCC) - HIGH OUTPUT VOLTAGE DROP - V
0 IOH - OUTPUT HIGH CURRENT - A
0.40
(VOH-VCC) - OUTPUT HIGH VOLTAGE DROP - V
0 VOH -1 -2 -3 -4 -5 -6
-0.5
0.38
-1.0
0.36
-1.5
0.34
-2.0
0.32
-2.5 -50
-25
0
25
50
75
100 125
0.30 -50
-25
0
25
50
75
100 125
0
0.2
0.4
0.6
TA - TEMPERATURE - C
TA - TEMPERATURE - C
IOH - OUTPUT HIGH CURRENT - A
Figure 1. V OH vs. Temperature.
Figure 2. I OH vs. Temperature.
Figure 3. V OH vs. I OH.
0.44
VOL - OUTPUT LOW VOLTAGE - V
0.470 0.465 0.460 0.455 0.450 0.445 0.440 -50
VOL - OUTPUT LOW VOLTAGE - V
25
IOL - OUTPUT LOW CURRENT - A
0.43
20
0.42
15
0.41
10
0.40
5
0.39 -50
-25
0
25
50
75
100 125
-25
0
25
50
75
100 125
0
0
100 200 300 400 500 600 700 IOL - OUTPUT LOW CURRENT - mA
TA - TEMPERATURE - C
TA - TEMPERATURE - C
Figure 4. V OL vs. Temperature.
Figure 5. I OL vs. Temperature.
Figure 6. V OL vs. I OL .
1.4 ICC - SUPPLY CURRENT - mA 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 ICCL ICCH 100 125
ICC - SUPPLY CURRENT - mA
1.2 1.0 0.8 0.6 0.4 0.2 0 10 ICCL ICCH 15 20 25 30
IFLH - LOW TO HIGH CURRENT THRESHOLD - mA
3.5
3.0
2.5
2.0
1.5 -50
-25
0
25
50
75
100 125
TA - TEMPERATURE - C
VCC - SUPPLY VOLTAGE - V
TA - TEMPERATURE - C
Figure 7. I CC vs. Temperature.
Figure 8. I CC vs. VCC .
Figure 9. I FLH vs. Temperature.
8
400
TP - PROPAGATION DELAY - ns TP - PROPAGATION DELAY - ns
400
500
TP - PROPAGATION DELAY - ns
300
300
400
300
200
200
200
100 TPLH TPHL 0 10 15 20 25 30
100
100
TPLH TPHL -25 0 25 50 75 100 125
0
6
9
12
15
18
0 -50
VCC - SUPPLY VOLTAGE - V
IF - FORWARD LED CURRENT - mA
TA - TEMPERATURE - C
Figure 10. Propagation Delay vs. VCC.
Figure 11. Propagation Delay vs. IF.
Figure 12. Propagation Delay vs. Temperature.
400
TP - PROPAGATION DELAY - ns
400
35
VO - OUTPUT VOLTAGE - V
TP - PROPAGATION DELAY - ns
30 25 20 15 10 5 0 -5 0 1 2 3 4 5 6
350
300
300
TPLH TPHL
200
250
100 TPLH TPHL 0 0 20 40 60 80 100
200
0
50
100
150
200
Rg - SERIES LOAD RESISTANCE -
Cg - LOAD CAPACITANCE - nF
IF - FORWARD LED CURRENT - mA
Figure 13. Propagation Delay vs. Rg.
Figure 14. Propagation Delay vs. Cg.
Figure 15. Transfer Characteristics.
25
IF - FORWARD CURRENT - mA
20
15
10
5
0 1.2
1.4
1.6
1.8
VF - FORWARD VOLTAGE - V
Figure 16. Input Current vs. Forward Voltage.
9
1 IF = 7 to 16 mA + 10 KHz -
50% DUTY CYCLE
8 0.1 F VCC = 15 to 30 V IF tr tf 90% 50% VOUT 10% tPLH tPHL
500
2
7 VO
+ -
3
6
47 3 nF
4
5
Figure 17. Propagation Delay Test Circuit and Waveforms.
VCM 1 IF A B 5V + - 3 6 2 7 VO + - VCC = 30 V VO SWITCH AT A: IF = 10 mA VO SWITCH AT B: IF = 0 mA + VCM = 1500 V VOL 8 0.1 F 0V t VOH V t = VCM t
4
5
Figure 18. CMR Test Circuit and Waveforms.
10
-
Applications Information Eliminating Negative IGBT Gate Drive To keep the IGBT firmly off, the HCPL-3140/HCPL-0314 has a very low maximum VOL specification of 1.0 V. Minimizing Rg and the lead inductance from the HCPL-3140/HCPL-0314 to the IGBT gate and emitter (possibly by mounting the
HCPL-3140/HCPL-0314 on a small PC board directly above the IGBT) can eliminate the need for negative IGBT gate drive in many applications as shown in Figure 19. Care should be taken with such a PC board design to avoid routing the IGBT collector or emitter traces close to the HCPL-3140/HCPL-0314 input as this can result in unwanted
coupling of transient signals into the input of HCPL-3140/ HCPL-0314 and degrade performance. (If the IGBT drain must be routed near the HCPL-3140/HCPL-0314 input, then the LED should be reverse biased when in the off state, to prevent the transient signals coupled from the IGBT drain from turning on the HCPL-3140/ HCPL-0314.)
+5 V 1 270 2
HCPL-3140/HCPL-0314 8 0.1 F 7 Rg Q1 3 6 + - VCC = 15 V
+ HVDC
CONTROL INPUT 74XXX OPEN COLLECTOR
3-PHASE AC
4
5 Q2
- HVDC
Figure 19. Recommended LED Drive and Application Circuit for HCPL-3140/HCPL-0314.
11
Esw - ENERGY PER SWITCHING CYCLE - J
Selecting the Gate Resistor (Rg) Step 1: Calculate R g minimum from the I OL peak specification. The IGBT and Rg in Figure 19 can be analyzed as a simple RC circuit with a voltage supplied by the HCPL-3140/HCPL-0314. Rg = VCC - VOL IOLPEAK 24 V - 5 V 0.6A
4.0 Qg = 50 nC 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 20 40 60 80 100 Qg = 100 nC Qg = 200 nC Qg = 400 nC
= 32 The VOL value of 5 V in the previous equation is the VOL at the peak current of 0.6A. (See Figure 6). Step 2: Check the HCPL-3140/HCPL-0314 power dissipation and increase Rg if necessary. The HCPL-3140/HCPL-0314 total power dissipation (PT) is equal to the sum of the emitter power (PE) and the output power (PO). P T = PE + PO PE = IF * VF * Duty Cycle PO = PO(BIAS) + PO(SWITCHING) = ICC * VCC + ESW (Rg,Qg)* f = (ICCBIAS + KICC * Qg * f) * VCC + E SW (Rg,Qg) * f where KICC * Qg * f is the increase in ICC due to switching and KICC is a constant of 0.001 mA/(nC*kHz). For the circuit in Figure 19 with IF (worst case) = 10 mA, Rg = 32 , Max Duty Cycle = 80%, Qg = 100 nC, f = 20 kHz and TAMAX = 85C: PE = 10 mA * 1.8 V * 0.8 = 14 mW P O = (3 mA + (0.001 mA/(nC * kHz)) * 20 kHz * 100 nC) * 24 V + 0.4 J * 20 kHz = 80 mW < 260 mW (PO(MAX) @ 85C) The value of 3 mA for ICC in the previous equation is the max. I CC over entire operating temperature range. Since PO for this case is less than PO(MAX), Rg = 32 is alright for the power dissipation.
Rg - GATE RESISTANCE -
Figure 20. Energy Dissipated in the HCPL-0314 and for Each IGBT Switching Cycle.
LED Drive Circuit Considerations for
Ultra High CMR Performance Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector IC as shown in Figure 21. The HCPL-3140/HCPL-0314 improves CMR performance by using a detector IC with an optically transparent Faraday shield, which diverts the capacitively coupled current away from the sensitive IC circuitry. However, this shield does not eliminate the capacitive coupling between the LED and opto-coupler pins 5-8 as shown in Figure 22. This capacitive coupling causes perturbations in the LED current during common mode transients and becomes the major source of CMR failures for a shielded optocoupler. The main design objective of a high CMR LED drive circuit becomes keeping the LED in the proper state (on or off ) during common mode transients. For example, the recommended application circuit (Figure 19), can achieve 10 kV/s CMR while minimizing component complexity. Techniques to keep the LED in the proper state are discussed in the next two sections.
12
1
CLEDP
8
1
CLEDO1 CLEDP
8
2
7
2
CLEDO2
7
3
CLEDN
6
3
CLEDN
6
4
5
4
SHIELD
5
Figure 21. Optocoupler Input to Output Capacitance Model for Unshielded Optocouplers.
Figure 22. Optocoupler Input to Output Capacitance Model for Shielded Optocouplers.
+5 V
1
CLEDP
8 0.1 F 7
ILEDP
+ VSAT -
2
+ -
VCC = 18 V
3
CLEDN
6 Rg 5
***
4
SHIELD
***
* THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW DURING -dVCM/dt.
+- VCM
Figure 23. Equivalent Circuit for Figure 17 During Common Mode Transient.
1 +5 V
CLEDP
8
1 +5 V
CLEDP
8
2
7
2
7
3 Q1 4
CLEDN ILEDN
6
3
CLEDN
6
SHIELD
5
4
SHIELD
5
Figure 24. Not Recommended Open Collector Drive Circuit.
Figure 25. Recommended LED Drive Circuit for Ultra-High CMR IPM Dead Time and Propagation Delay Specifications.
13
CMR with the LED On (CMRH) A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by overdriving the LED current beyond the input threshold so that it is not pulled below the threshold during a transient. A minimum LED current of 8 mA provides adequate margin over the maximum IFLH of 5 mA to achieve 10 kV/s CMR. CMR with the LED Off (CMRL) A high CMR LED drive circuit must keep the LED off (VF VF(OFF)) during common mode transients. For example, during a -dVCM/dt transient in Figure 23, the current flowing through CLEDP also flows through the RSAT and VSAT of the logic gate. As long as the low state voltage developed across the logic gate is less than VF(OFF) the LED will remain off and no common mode failure will occur. The open collector drive circuit, shown in Figure 24, can not keep the LED off during a +dVCM /dt transient, since all the current flowing through CLEDN must be
supplied by the LED, and it is not recommended for applications requiring ultra high CMR1 performance. The alternative drive circuit which like the recommended application circuit (Figure 19), does achieve ultra high CMR performance by shunting the LED in the off state. IPM Dead Time and Propagation Delay Specifications The HCPL-3140/HCPL-0314 includes a Propagation Delay Difference (PDD) specification intended to help designers minimize "dead time" in their power inverter designs. Dead time is the time high and low side power transistors are off. Any overlap in Ql and Q2 conduction will result in large currents flowing through the power devices from the highvoltage to the low-voltage motor rails. To minimize dead time in a given design, the turn on of LED2 should be delayed (relative to the turn off of LED1) so that under worst-case conditions, transistor Q1 has just turned off when transistor Q2 turns on, as shown in Figure 26. The amount of delay necessary to achieve this
condition is equal to the maximum value of the propagation delay difference specification, PDD max, which is specified to be 500 ns over the operating temperature range of -40 to 100C. Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time is equivalent to the difference between the maximum and minimum propagation delay difference specification as shown in Figure 27. The maximum dead time for the HCPL-3140/HCPL0314 is 1 s (= 0.5 s - (-0.5 s)) over the operating temperature range of -40C to 100C. Note that the propagation delays used to calculate PDD and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical IGBTs.
14
ILED1
VOUT1
Q1 ON Q1 OFF Q2 ON
VOUT2 ILED2
Q2 OFF
tPHL MAX tPLH MIN PDD* MAX = (tPHL- tPLH)MAX = tPHL MAX - tPLH MIN
*PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
Figure 26. Minimum LED Skew for Zero Dead Time.
ILED1
VOUT1
Q1 ON Q1 OFF Q2 ON
VOUT2
Q2 OFF
ILED2 tPHL MIN tPHL MAX tPLH
MIN
tPLH MAX (tPHL-tPLH) MAX PDD* MAX MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER) = (tPHL MAX - tPHL MIN) + (tPLH MAX - tPLH MIN) = (tPHL MAX - tPLH MIN) - (tPHL MIN - tPLH MAX) = PDD* MAX - PDD* MIN *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
Figure 27. Waveforms for Dead Time.
15
www.semiconductor.agilent.com Data subject to change. Copyright (c) 2001 Agilent Technologies, Inc. September 11, 2001 Obsoletes 5988-3612EN 5988-4133EN

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