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| a FEATURES Fast: 2.5 ns Propagation Delay Low Power: 118 mW per Comparator Packages: DIP, TO-100, SOIC, PLCC Power Supplies: +5 V, -5.2 V Logic Compatibility: ECL MIL-STD-883 Versions Available 50 ps Delay Dispersion APPLICATIONS High Speed Triggers High Speed Line Receivers Threshold Detectors Window Comparators Peak Detectors Ultrafast Comparators AD96685/AD96687 AD96685 FUNCTIONAL BLOCK DIAGRAM AD96687 FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION The AD96685 and AD96687 are ultrafast voltage comparators. The AD96685 is a single comparator with 2.5 ns propagation delay; the AD96687 is an equally fast dual comparator. Both devices feature 50 ps propagation delay dispersion which is a particularly important characteristic of high speed comparators. It is a measure of the difference in propagation delay under differing overdrive conditions. A fast, high precision differential input stage permits consistent propagation delay with a wide variety of signals in the commonmode range from -2.5 V to +5 V. Outputs are complementary digital signals fully compatible with ECL 10 K and 10 KH logic families. The outputs provide sufficient drive current to directly drive transmission lines terminated in 50 to -2 V. A level sensitive latch input is included which permits tracking, track-hold, or sample-hold modes of operation. The AD96685 and AD96687 are available in both industrial, -25C to +85C, and military temperature ranges. Industrial range devices are available in 16-pin DIP, SOIC, and 20-lead PLCC; additionally, the AD96685 is available in a 10-pin, TO-100 metal can. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD96685/AD96687-SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS 1 EXPLANATION OF TEST LEVELS Positive Supply Voltage (+VS) . . . . . . . . . . . . . . . . . . . . +6.5 V Negative Supply Voltage (-VS) . . . . . . . . . . . . . . . . . . . -6.5 V Input Voltage Range2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Latch Enable Voltage . . . . . . . . . . . . . . . . . . . . . . . . -VS to 0 V Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Operating Temperature Range3 AD96685/87/BH/BQ/BP/BR . . . . . . . . . . . . -25C to +85C AD96685/87/TQ . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature Range . . . . . . . . . . . . . -55C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +175C Lead Soldering Temperature (10 sec) . . . . . . . . . . . . . +300C Test Level I - 100% production tested. II - 100% production tested at +25C, and sample tested at specified temperatures. III - Sample tested only. IV - Parameter is guaranteed by design and characterization testing. V - Parameter is a typical value only. VI - All devices are 100% production tested at +25C; 100% production tested at temperature extremes for extended temperature devices; sample tested at temperature extremes for commercial/industrial devices. ELECTRICAL CHARACTERISTICS (Positive Supply Voltage = +5.0 V; Negative Supply Voltage = -5.2 V, unless otherwise noted) Parameter INPUT CHARACTERISTICS Input Offset Voltage4 Input Offset Drift Input Bias Current Input Offset Current Input Resistance Input Capacitance Input Voltage Ranges Common-Mode Rejection Ratio ENABLE INPUT Logic "1" Voltage Logic "0" Voltage Logic "1" Current Logic "0" Current DIGITAL OUTPUTS6 Logic "1" Voltage Logic "0" Voltage SWITCHING PERFORMANCES Propagation Delays7 Input to Output HIGH Input to Output LOW Latch Enable to Output HIGH Latch Enable to Output LOW Dispersions8 Latch Enable Minimum Pulse Width Minimum Setup Time Minimum Hold Time POWER SUPPLY9 Positive Supply Current (+5.0 V) Negative Supply Current (-5.2 V) Power Supply Rejection Ratio10 Temp +25C Full Full +25C Full +25C Full +25C +25C Full Full Full Full Full Full Full Full Industrial Temp. Range -25 C to +85 C Military Temp. Range -55 C to +125 C Test AD96685BH/BQ/BP/BR AD96687BQ/BP/BR AD96685TQ AD96687TQ Level Min Typ Max Min Typ Max Min Typ Max Min Typ Max I VI V I VI I VI V V VI VI VI VI VI VI VI VI 1 20 7 0.1 200 2 -2.5 80 -1.1 -1.5 40 5 -1.1 -1.5 -1.1 -1.5 +5.0 90 2 3 10 13 1.0 1.2 1 20 7 0.1 200 2 -2.5 80 90 -1.1 -1.5 40 5 -1.1 -1.5 +5.0 -2.5 80 -1.1 -1.5 40 5 -1.1 -1.5 2 3 10 13 1.0 1.2 1 20 7 0.1 200 2 +5.0 90 2 3 10 16 1.0 1.2 1 20 7 0.1 200 2 -2.5 80 90 -1.1 -1.5 40 5 +5.0 2 3 10 16 1.0 1.2 Units mV mV V/C A A A A k pF V dB V V A A V V +25C +25C +25C +25C +25C IV IV IV IV V 2.5 2.5 2.5 2.5 50 2.0 0.5 0.5 8 15 70 3.5 3.5 3.5 3.5 3.0 1.0 1.0 9 18 60 2.5 2.5 2.5 2.5 50 2.0 0.5 0.5 15 31 70 4 5 6 3.5 3.5 3.5 3.5 3.0 1.0 1.0 18 36 60 2.5 2.5 2.5 2.5 50 2.0 0.5 0.5 8 15 70 3.5 3.5 3.5 3.5 3.0 1.0 1.0 9 18 60 2.5 2.5 2.5 2.5 50 2.0 0.5 0.5 15 31 70 3.5 3.5 3.5 3.5 3.0 1.0 1.0 18 36 ns ns ns ns ps ns ns ns mA mA dB +25C IV +25C IV +25C IV Full Full Full VI VI VI 60 NOTES 1 Absolute maximum ratings are limiting values, may be applied individually, and beyond which serviceability of the circuit may be impaired. Functional operation under any of these conditions is not necessarily implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Under no circumstances should the input voltages exceed the supply voltages . 3 Typical thermal impedances . . . AD96685 Metal Can JA = 172C/W; JC = 52C/W AD96685 Ceramic JA = 115C/W; JC = 57C/W AD96685 SOIC JA = 170C/W; JC = 60C/W AD96685 PLCC JA = 88C/W; JC = 45C/W AD96687 Ceramic JA = 115C/W; JC = 57C/W AD96687 SOIC JA = 92C/W; JC = 47C/W AD96687 PLCC JA = 81C/W; JC = 45C/W RS = 100 . Input Voltage Range can be extended to -3.3 V if -VS = -6.0 V. Outputs terminated through 50 to -2.0 V. 7 Propagation delays measured with 100 mV pulse (10 mV overdrive), to 50% transition point of the output. 8 Change in propagation Delay from 100 mV to 1 V input overdrive. 9 Supply voltages should remain stable within 5% for normal operation. 10 Measured at 5% of +VS and -VS. Specifications subject to change without notice. -2- REV. C AD96685/AD96687 FUNCTIONAL DESCRIPTION Pin Name +VS NONINVERTING INPUT INVERTING INPUT LATCH ENABLE Description Positive supply terminal, nominally +5.0 V. Noninverting analog input of the differential input stage. The NONINVERTING INPUT must be driven in conjunction with the INVERTING INPUT. Inverting analog input of the differential input stage. The INVERTING INPUT must be driven in conjunction with the NONINVERTING INPUT. In the "compare" mode (logic HIGH), the output will track changes at the input of the comparator. In the "latch" mode (logic LOW), the output will reflect the input state just prior to the comparator being placed in the "latch" mode. LATCH ENABLE must be driven in conjunction with LATCH ENABLE for the AD96687. In the "compare" mode (logic LOW), the output will track changes at the input of the comparator. In the "latch" mode (logic HIGH), the output will reflect the input state just prior to the comparator being placed in the "latch" mode. LATCH ENABLE must be driven in conjunction with LATCH ENABLE for the AD96687. Negative supply terminal, nominally -5.2 V. One of two complementary outputs. Q will be at logic HIGH if the analog voltage at the NONINVERTING INPUT is greater than the analog voltage at the INVERTING INPUT (provided the comparator is in the "compare" mode). See LATCH ENABLE and LATCH ENABLE (AD96687 only) for additional information. One of two complementary outputs. Q will be at logic LOW if the analog voltage at the NONINVERTING INPUT is greater than the analog voltage at the INVERTING INPUT (provided the comparator is in the "compare" mode). See LATCH ENABLE and LATCH ENABLE (AD96687 only) for additional information. One of two grounds, but primarily associated with the digital ground. Both grounds should be connected together near the comparator. One of two grounds, but primarily associated with the analog ground. Both grounds should be connected together near the comparator. PIN DESIGNATIONS AD96685BQ/TQ/BR AD96687BQ/TQ/BR LATCH ENABLE -VS Q Q GROUND 1 GROUND 2 NC = NO CONNECT AD96685BP AD96685BH AD96687BP NC = NO CONNECT NC = NO CONNECT REV. C -3- AD96685/AD96687 SYSTEM TIMING DIAGRAM tS tH tPD - Minimum Setup Time - Minimum Hold Time - Input to Output Delay tPD(E) - LATCH ENABLE to Output Delay tPW(E) - Minimum LATCH ENABLE Pulse Width VOS VOD - Input Offset Voltage - Overdrive Voltage DIE LAYOUT AND MECHANICAL INFORMATION Die Dimensions (AD96685) . . . . . . . . 44 50 15 ( 2) mils Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 mils Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VS Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oxynitride Die Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold Eutectic Bond Wire . . . . . . . . 1.25 mil, Aluminum; Ultrasonic Bonding or 1 mil, Gold, Gold Ball Bonding Die Dimensions (AD96687) . . . . . . . . 77 60 15 ( 2) mils Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 mils Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VS Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oxynitride Die Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold Eutectic Bond Wire . . . . . . . . 1.25 mil, Aluminum; Ultrasonic Bonding or 1 mil, Gold, Gold Ball Bonding -4- REV. C AD96685/AD96687 ORDERING GUIDE Model AD96685BH AD96685BP AD96685BQ AD96685BR AD96685BP-REEL AD96685TQ AD96687BP AD96687BQ AD96687BR AD96687BR-REEL AD96687TQ Type Single Single Single Single Single Single Dual Dual Dual Dual Dual Temperature Range -25C to +85C -25C to +85C -25C to +85C -25C to +85C -25C to +85C -55C to +125C -25C to +85C -25C to +85C -25C to +85C -25C to +85C -55C to +125C Description 10-Pin Can, Industrial 20-Pin PLCC, Industrial 16-Pin DIP, Industrial 16-Pin SOIC, Industrial 20-Pin PLCC, Industrial 16-Pin DIP, Extended Temperature 20-Pin PLCC, Industrial 16-Pin DIP, Industrial 16-Pin SOIC, Industrial 16-Pin SOIC, Industrial 16-Pin DIP, Extended Temperature Package Options H-10A P-20A Q-16 R-16A P-20A Q-16 P-20A Q-16 R-16A R-16A Q-16 APPLICATIONS INFORMATION The AD96685/87 comparators are very high speed devices. Consequently, high speed design techniques must be employed to achieve the best performance. The most critical aspect of any AD96685/87 design is the use of a low impedance ground plane. Another area of particular importance is power supply decoupling. Normally, both power supply connections should be separately decoupled to ground through 0.1 F ceramic and 0.001 F mica capacitors. The basic design of comparator circuits makes the negative supply somewhat more sensitive to variations. As a result more attention should be placed on insuring a "clean" negative supply. The LATCH ENABLE input is active LOW (latched). If the latching function is not used, the LATCH ENABLE input should be grounded (ground is an ECL logic HIGH). The LATCH ENABLE input of the AD96687 should be tied to -2.0 V or left "floating," to disable the latching function. An alternate use of the LATCH ENABLE input is as a hysteresis control input. By varying the voltage at the LATCH ENABLE input for the AD96685 and the differential voltage between both latch inputs for the AD96687, small variations in the hysteresis can be achieved. Occasionally, one of the two comparator stages within the AD96687 will not be used. The inputs of the unused comparator should not be allowed to "float." The high internal gain may cause the output to oscillate (possibly affecting the other comparator which is being used) unless the output is forced into a fixed state. This is easily accomplished by insuring that the two inputs are at least one diode drop apart, while also grounding the LATCH ENABLE input. The best performance will be achieved with the use of proper ECL terminations. The open-emitter outputs of the AD96685/87 are designed to be terminated through 50 resistors to -2.0 V, or any other equivalent ECL termination. If high speed ECL signals must be routed more than a few centimeters, MicroStrip or StripLine techniques may be required to insure proper transition times and prevent output ringing. The AD96685/87 have been specifically designed to reduce propagation delay dispersion over an input overdrive range of 100 mV to 1 V. Propagation delay dispersion is the change in propagation delay which results from a change in the degree of overdrive (how far the switching point is exceeded by the input). The overall result is a higher degree of timing accuracy since the AD96685/87 is far less sensitive to input variations than most comparator designs. Typical Applications HIGH SPEED SAMPLING CIRCUIT HIGH SPEED WINDOW COMPARATOR REV. C -5- AD96685/AD96687 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Pin Ceramic DIP 16-Pin SOIC 20-Pin LCC 20-Pin PLCC 10-Pin TO-100 Metal Can -6- REV. C PRINTED IN U.S.A. C1096b-2-9/96 |
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