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| (R) STB3NC60 N - CHANNEL 600V - 3.3 - 3A - D2PAK/I2PAK PowerMESHTM MOSFET T YPE STB3NC60 V DSS 600 V R DS(on) < 3.6 ID 3A TYPICAL RDS(on) = 3.3 EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED VERY LOW INTRINSIC CAPACITANCES GATE CHARGE MINIMIZED 3 3 12 1 DESCRIPTION The PowerMESHTM II is the evolution of the first generation of MESH OVERLAYTM . The layout refinements introduced greatly improve the Ron*area figure of merit while keeping the device at the leading edge for what concerns switching speed, gate charge and ruggedness. APPLICATIONS HIGH CURRENT, HIGH SPEED SWITCHING SWITCH MODE POWER SUPPLIES (SMPS) DC-AC CONVERTERS FOR WELDING EQUIPMENT AND UNINTERRUPTIBLE POWER SUPPLIES AND MOTOR DRIVE I2PAK TO-262 (Suffix "-1") D2PAK TO-263 (Suffix "T4") INTERNAL SCHEMATIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symb ol V DS V DGR V GS ID ID I DM (*) P tot dv/dt(1) T s tg Tj Parameter Drain-source Voltage (VGS = 0) Drain- gate Voltage (R GS = 20 k) G ate-source Voltage Drain Current (continuous) at Tc = 25 C Drain Current (continuous) at Tc = 100 C Drain Current (pulsed) T otal Dissipation at T c = 25 C Derating Factor Peak Diode Recovery voltage slope Storage Temperature Max. O perating Junction Temperature o o o Value 600 600 30 3 1.9 12 80 0.64 4 -65 to 150 150 (1) ISD 3A, di/dt 100 A/s, VDD V(BR)DSS, Tj TJMAX Unit V V V A A A W W/ o C V/ns o o C C (*) Pulse width limited by safe operating area February 2000 1/9 STB3NC60 THERMAL DATA R thj- ca se R t hj-a mb R thc -sin k Tl Thermal Resistance Junction-case Max 1.56 62.5 0.5 300 o o o C/W C/W C/W o C Thermal Resistance Junction-ambient Max Thermal Resistance Case-sink Typ Maximum Lead Temperature For Soldering Purpose AVALANCHE CHARACTERISTICS Symbo l I AR E AS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by T j max) Single Pulse Avalanche Energy o (starting Tj = 25 C, I D = IAR , V DD = 50 V) Max Valu e 3 100 Unit A mJ ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF Symbo l V ( BR)DSS I DSS I GSS Parameter Drain-source Breakdown Voltage Test Cond itions ID = 250 A V GS = 0 Min. 600 1 50 100 Typ . Max. Un it V A A nA VDS = Max Rating Zero G ate Voltage Drain Current (V GS = 0) VDS = Max Rating Gate-body Leakage Current (VDS = 0) VGS = 30 V Tc = 125 o C ON () Symbo l V GS(th ) R DS(on ) I D(on) Parameter Gate Threshold Voltage VDS = V GS Static Drain-source On Resistance On State Drain Current VGS = 10V Test Cond itions ID = 250 A I D = 1.5 A 3 Min. 2 Typ . 3 3.3 Max. 4 3.6 Un it V A VDS > I D(on ) x R DS(on )max VGS = 10 V DYNAMIC Symbo l g fs () C is s C os s C rs s Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse T ransfer Capacitance Test Cond itions VDS > I D(on ) x R DS(on )max VDS = 25 V f = 1 MHz I D = 1.5 A V GS = 0 Min. Typ . 2 400 57 7 Max. Un it S pF pF pF 2/9 STB3NC60 ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbo l t d( on) tr Qg Q gs Q gd Parameter Turn-on T ime Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Cond itions VDD = 300 V I D = 1.5 A VGS = 10 V R G = 4.7 (see test circuit, figure 3) VDD = 480 V ID = 3 A V GS = 10 V Min. Typ . 9 13 13 2.3 4.4 18.2 Max. Un it ns ns nC nC nC SWITCHING OFF Symbo l t r(Vof f ) tf tc Parameter Off-voltage Rise Time Fall T ime Cross-over Time Test Cond itions VDD = 480 V I D = 3 A R G = 4.7 VGS = 10 V (see test circuit, figure 5) Min. Typ . 13 15 21 Max. Un it ns ns ns SOURCE DRAIN DIODE Symbo l I SD I SDM (*) V SD () t rr Q rr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward O n Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 3 A V GS = 0 420 1.5 7.1 Test Cond itions Min. Typ . Max. 3 12 1.6 Un it A A V ns C A ISD = 3 A di/dt = 100 A/s Tj = 150 o C VDD = 100 V (see test circuit, figure 5) () Pulsed: Pulse duration = 300 s, duty cycle 1.5 % (*) Pulse width limited by safe operating area Safe Operating Area for D2PAK/I2PAK Thermal Impedancefor D2PAK/I2PAK 3/9 STB3NC60 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/9 STB3NC60 Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/9 STB3NC60 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/9 STB3NC60 TO-262 (I2PAK) MECHANICAL DATA mm MIN. A A1 B B1 B2 C C2 D e E L L1 L2 4.3 2.49 0.7 1.2 1.25 0.45 1.21 8.95 2.44 10 13.2 3.48 1.27 TYP. MAX. 4.6 2.69 0.93 1.38 1.4 0.6 1.36 9.35 2.64 1 0.2 8 13.5 3.78 1.4 MIN. 0.169 0.098 0.027 0.047 0.049 0.017 0.047 0.352 0.096 0.393 0.519 0.137 0.050 inch TYP. MAX. 0.1 81 0.1 06 0.0 36 0.0 54 0.0 55 0.0 23 0.0 53 0.3 68 0.1 04 0.4 04 0.5 31 0.1 49 0.0 55 DIM. A C2 B2 B E L1 L2 D L P0 11 P5/C 7/9 e A1 C STB3NC60 TO-263 (D2PAK) MECHANICAL DATA mm MIN. A A1 B B2 C C2 D E G L L2 L3 4.3 2.49 0.7 1.25 0.45 1.21 8.95 10 4.88 15 1.27 1.4 TYP. MAX. 4.6 2.69 0.93 1.4 0.6 1.36 9.35 1 0.2 8 5.28 1 5.8 5 1.4 1.75 MIN. 0.169 0.098 0.027 0.049 0.017 0.047 0.352 0.393 0.192 0.590 0.050 0.055 inch TYP. MAX. 0.1 81 0.1 06 0.0 36 0.0 55 0.0 23 0.0 53 0.3 68 0.4 04 0.2 08 0.6 24 0.0 55 0.0 68 DIM. E C2 L2 A D L L3 B2 B G A1 C P0 11 P6/C 8/9 STB3NC60 Information furnished is believed to be accurate and reliable. However, STMicroelectonics assumes no responsibil ity for the consequences r of use of such information nor for any infringement of patents or other rights of third partes which may result from its use. No license is i granted by implication or otherwise under any patent or patent rights of STMicroelectro nics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all informaton previously supplied. STMicroelectronics products i are not authorized for use as critical components in life support devices or systems with express written approval of STMicroelectronics. out The ST logo is a trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japa - Malaysia - Malta - Morocco n Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com . 9/9 |
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