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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM69T618/D
64K x 18 Bit Synchronous Pipelined Cache Tag RAM
The MCM69T618 is a 1M-bit synchronous fast static RAM with integrated tag compare function. It is designed to address tag RAM for 512KB, 1MB, or 2MB secondary cache as well as to be used as a data RAM for 512KB caches. This device is organized as 64K words of 18 bits each. It integrates input registers, output registers, tag comparators, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache tag RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability. Addresses (SA), data inputs (DQ), write enable (SW), and chip enable (SE0 and SE1) are all controlled through positive-edge-triggered noninverting registers. Data enable (DE) is sampled on the rising clock edge while output enable (G) and match output enable (MG) are asynchronous. Write cycles are internally self-timed and initiated by the rising edge of the clock (K) input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. For read cycles, pipelined SRAM output data is temporarily stored by an edge-triggered output register and then released to the output buffers at the next rising edge of clock (K). Compare cycles begin as read cycles with output disabled, so compare data can be loaded into the input register. The comparator compares the read data with the registered input data, and a match signal is generated. The match output is also stored by an output register and released to the match output buffer at the next rising edge of clock (K). The MCM69T618 operates from a single 3.3 V power supply and all inputs and outputs are LVTTL compatible. * * * * * * * * * * MCM69T618-5 = 5 ns Clock-to-Match / 10 ns cycle Single 3.3 V + 10%, - 5% Power Supply Pipelined Data Comparator Pipelined Chip Enable and Write Enable for Data (DQ) Output Enable Path 64K x 18 Organization Supports Up to 2MB Cache Synchronous Data Input Register Load Enable (DE) Internally Self-Timed Write Cycle Asynchronous Data I/O Output Enable (G) Asynchronous Match Output Enable (MG) 100-Pin TQFP Package
MCM69T618
TQ PACKAGE TQFP CASE 983A-01
REV 5 12/23/97
(c) Motorola, Inc. 1997 MOTOROLA FAST SRAM
MCM69T618 1
FUNCTIONAL BLOCK DIAGRAM
SA
REGISTER
16 64K x 18 ARRAY
WRITE DRIVER
MATCH MG
REGISTER
COMPARE
18
18
DE LATCH K
DATA-IN REGISTER
DATA-OUT REGISTER
K
SW
REGISTER
REGISTER 18 18
SE0 SE1
LATCH
REGISTER
G
DQ1-DQ18
MCM69T618 2
MOTOROLA FAST SRAM
PIN ASSIGNMENT
SA SA SE1 SE0 NC NC NC NC NC VCC VSS K NC SW G NC NC NC SA SA NC NC NC VCC VSS NC NC DQ10 DQ11 VSS VCC DQ12 DQ13 NC VCC NC VSS DQ14 DQ15 VCC VSS DQ16 DQ17 DQ18 NC VSS VCC NC NC NC 100 99 98 97 9695 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 3738 39 40 41 42 43 44 4546 47 48 49 50 NC SA SA SA SA SA SA VSS MATCH VSS VCC DE MG SA SA SA SA SA NC NC Not to Scale TOP VIEW 100-PIN TQFP SA NC NC VCC VSS NC DQ9 DQ8 DQ7 VSS VCC DQ6 DQ5 VSS NC VCC NC DQ4 DQ3 VCC VSS DQ2 DQ1 NC NC VSS VCC NC NC NC
MOTOROLA FAST SRAM
MCM69T618 3
PIN DESCRIPTIONS
Pin Locations 42 8, 9, 12, 13, 18, 19, 22, 23, 24, 58, 59, 62, 63, 68, 69, 72, 73, 74 86 Symbol DE DQ1 - DQ18 Type Input I/O Description Data Enable Input: Latched on the rising clock edge, active low. The data input register is only updated when DE is low. Synchronous Data I/O: For write cycles, registered on the rising clock edge. Two cycles after a read command, the read data is output on the DQ pins provided that G is low. On the same cycle of a write command, the write data is input on the DQ signals. Output Enable: Asynchronous pin, active low. G must be low for read data to be output two cycles after a read command. If G is high, the data output DQ will remain in high impedance even if a read command occurs internally. Clock: All the signals except G and MG are controlled by the clock. Two cycles after a compare cycle and if MG is low, MATCH will be high if the data presented to the DQ inputs matches the data stored in the RAM. MATCH will be low if the data does not match. Match Output Enable: Asynchronous pin, active low. When MG is low, the MATCH output driver is on, otherwise the MATCH output driver is in high impedance. Synchronous Address Inputs: Registered on the rising clock edge. The address pins select one of the 64K tag entries. Synchronous Chip Enable: Registered on the rising clock edge, active high. Synchronous Chip Enable: Registered on the rising clock edge, active low. Synchronous Write: Registered on the rising clock edge, active low. The SW input specifies whether a read or write cycle is to occur when the chip is enabled. A write command should not be issued within three cycles of a read command unless G is high or output drive contention may occur. Power Supply: 3.3 V + 10%, - 5%. Ground. No Connection: There is no connection to the chip.
G
Input
89 39
K MATCH
Input Output
43
MG
Input
32, 33, 34, 35, 36, 37, 44, 45, 46, 47, 48, 80, 81, 82, 99, 100 97 98 87
SA
Input
SE0 SE1 SW
Input Input Input
4, 11, 15, 20, 27, 41, 54, 61, 65, 70, 77, 91 5, 10, 17, 21, 26, 38, 40, 55, 60, 67, 71, 76, 90 1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30, 31, 49, 50, 51, 52, 53, 56, 57, 64, 66, 75, 78, 79, 83, 84, 85, 88, 92, 93, 94, 95, 96
VCC VSS NC
Supply Supply --
MCM69T618 4
MOTOROLA FAST SRAM
TRUTH TABLE (See Notes 1 through 4)
Next Cycle Read Write Compare Fill Write Deselected (Match Out) Deselected SE 0 0 0 0 1 1 SW 1 0 1 0 X X DE X 0 0 1 X X MG X X 0 X 0 1 G 0 1 1 1 X X Match -- -- Data Out -- Data High High-Z DQ Data Out Data In Data In High-Z High-Z High-Z
NOTES: 1. X = Don't Care. 1 = logic high. 0 = logic low. 2. SE low is defined as SE1 = 0 and SE0 = 1. SE high is defined as SE1 = 1 or SE0 = 0. 3. G and MG are asynchronous signals and are not sampled by the clock K. G drives the bus immediately (tGLQX) when G goes low. 4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must also remain negated at the completion of the write cycle to ensure proper write data hold times.
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating Power Supply Voltage Voltage Relative to VSS for Any Pin Except VCC Output Current (per I/O) Package Power Dissipation Temperature Under Bias Storage Temperature Symbol VCC Vin, Vout Iout PD Tbias Tstg Value - 0.5 to + 4.6 VCC + 0.5 20 1.6 - 10 to + 85 - 55 to + 125 Unit V V mA W C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (See Note 1)
Rating Junction to Ambient (@ 200 lfm) Junction to Board (Bottom) Junction to Case (Top) Single-Layer Board Four-Layer Board Symbol RJA RJB RJC Max 40 25 17 9 Unit C/W C/W C/W Notes 2 3 4
NOTES: 1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, board population, and board thermal resistance. 2. Per SEMI G38-87. 3. Indicates the average thermal resistance between the die and the printed circuit board. 4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC-883 Method 1012.1).
MOTOROLA FAST SRAM
MCM69T618 5
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 3.3 V + 10%, - 5%, TJ = 20 to 110C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V)
Parameter Supply Voltage Operating Temperature Input Low Voltage Input High Voltage * VIL - 1.5 V for t tKHKH/2. ** VIH VCC + 1.0 V for t tKHKH/2. Symbol VCC TJ VIL VIH Min 3.135 20 - 0.5* 2.0 Typ 3.3 -- -- -- Max 3.6 110 0.8 VCC + 0.5** Unit V C V V
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter Input Leakage Current (0 V Vin VCC) Output Leakage Current (0 V Vin VCC) AC Supply Current (Device Selected, All Outputs Open, All Inputs Toggling at Vin VIL or VIH Cycle Time tKHKH min) CMOS Standby Supply Current (Deselected, Clock (K) Cycle Time tKHKH, All Inputs Toggling at CMOS Levels Vin VSS + 0.2 V or VCC - 0.2 V) Clock Running Supply Current (Deselected, Clock (K) Cycle Time tKHKH, All Other Inputs Held to Static CMOS Levels Vin VSS + 0.2 V or VCC - 0.2 V) Output Low Voltage (IOL = 8 mA) Output High Voltage (IOH = - 4 mA) NOTE: 1. Device in deselected mode as defined by the Truth Table. Symbol Ilkg(I) Ilkg(O) ICCA Min -- -- -- Typ -- -- -- Max 1 1 240 Unit A A mA Notes
ISB1
--
--
130
mA
1
ISB2
--
--
45
mA
1
VOL VOH
-- 2.4
-- --
0.4 --
V V
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25C, Periodically Sampled Rather Than 100% Tested)
Parameter Input Capacitance Input/Output Capacitance Symbol Cin CI/O Min -- -- Typ 3 6 Max 5 8 Unit pF pF
MCM69T618 6
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 3.3 V + 10%, - 5%, TJ = 20 to 110C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . See Figure 1 Unless Otherwise Noted
READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3)
MCM69T618-5 Parameter Cycle Time Clock High Pulse Width Clock Low Pulse Width Clock High to Match Valid Clock Access Time Output Enable to Output Valid Match Output Enable to Match Valid Clock High to Output Active Clock High to Output Change Clock High to Match Output Change Output Enable to Output Active Match Output Enable to Match Active Output Disable to Q High-Z Match Output Disable to Match High-Z Clock High to Q High-Z Setup Times: Address Data In Write Enable Address Data In Write Enable Symbol tKHKH tKHKL tKLKH tKHMV tKHQV tGLQV tMGLMV tKHQX1 tKHQX2 tKHMX tGLQX tMGLMX tGHQZ tMGHMZ tKHQZ tAVKH tDVKH tWVKH tEVKH tKHAX tKHDX tKHWX tKHEX Min 10 3.5 3.5 -- -- -- -- 0 1.5 1.5 0 0 -- -- 1.5 2.5 Max -- -- -- 5 5 5 5 -- -- -- -- -- 5 5 5 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4, 5 4, 5 5, 6 5 5, 6 4 4 4 4, 5 4 Notes
Hold Times:
0.5
--
ns
NOTES: 1. "Write" applies to the SW signal. "Enable" applies to SE0, SE1, and DE signals. 2. All read and write cycle timings are referenced from K or G. 3. G is a don't care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle. 4. Tested per AC Test Load (See Figure 1). 5. This parameter is sampled and not 100% tested. 6. Measured at 200 mV from steady state.
OUTPUT Z0 = 50 RL = 50 VT = 1.5 V
Figure 1. AC Test Loads
MOTOROLA FAST SRAM
MCM69T618 7
COMPARE/FILL WRITE CYCLES
t KHKH tKHKL K tEVKH SE* tKHEX tKLKH
SW
G tAVKH SA tDVKH DQ tDEVKH DE D(A) tKHDEX A tKHDX D(B) tKHAX B B
tMGLMV MG tMGLMX MATCH tKHMV tKHMX MATCH HIGH WHEN CHIP DESELECTED
HIT
MISS
FILL WRITE**
* SE low = SE0 high and SE1 low. ** During fill write sequence, tag entry is written with tag value retained in the data input register from the previous compare cycle.
MCM69T618 8
MOTOROLA FAST SRAM
READ/WRITE CYCLES
t KHKH K t KHKL SA A B C D tAVKH E t KHAX F G H t KLKH
SE* tWVKH SW t KHDX tDVKH Q(D) D(E) D(F) D(G) D(H) tKHWX
t KHQV DQ t KHQX1 Q(A) Q(B) tKHQX2 Q(C)
tKHQZ
DE t GLQV G tGHQZ
READS * SE low = SE0 high and SE1 low.
WRITES
ORDERING INFORMATION
(Order by Full Part Number) MCM
Motorola Memory Prefix Part Number
69T618
XX
X
X
R = Tape and Reel, Blank = Tray Speed (5 = 5 ns) Package (TQ = TQFP)
Full Part Numbers -- MCM69T618TQ5 MCM69T618TQ5R
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MOTOROLA FAST SRAM
MCM69T618 9
PACKAGE DIMENSIONS
TQ PACKAGE TQFP CASE 983A-01 0.20 (0.008) H A-B D
2X 30 TIPS
4X
e 0.20 (0.008) C A-B D e/2
-D-
80 81 51 50
B E/2 -B- E1 E E1/2 B VIEW Y
BASE METAL PLATING
-X- X=A, B, OR D
-A-
b1 c
100 1 30
31
D1/2 D1 D
2X 20 TIPS
D/2
0.13 (0.005)
0.20 (0.008) C A-B D
A -H- -C-
SEATING PLANE
q
2
0.10 (0.004) C
q
3 VIEW AB
0.05 (0.002)
S
S
q
1 0.25 (0.010)
GAGE PLANE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS D1 AND B1 DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE b DIMENSION TO EXCEED 0.45 (0.018). MILLIMETERS MIN MAX --- 1.60 0.05 0.15 1.35 1.45 0.22 0.38 0.22 0.33 0.09 0.20 0.09 0.16 22.00 BSC 20.00 BSC 16.00 BSC 14.00 BSC 0.65 BSC 0.45 0.75 1.00 REF 0.50 REF 0.20 --- 0.08 --- 0.08 0.20 0_ 7_ 0_ --- 11 _ 13 _ 11 _ 13 _ INCHES MIN MAX --- 0.063 0.002 0.006 0.053 0.057 0.009 0.015 0.009 0.013 0.004 0.008 0.004 0.006 0.866 BSC 0.787 BSC 0.630 BSC 0.551 BSC 0.026 BSC 0.018 0.030 0.039 REF 0.020 REF 0.008 --- 0.003 --- 0.003 0.008 0_ 7_ 0_ --- 11 _ 13 _ 11 _ 13 _
A2
R2
A1
R1
L2 L L1 VIEW AB
q
DIM A A1 A2 b b1 c c1 D D1 E E1 e L L1 L2 S R1 R2
q q q q
1 2 3
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MCM69T618 10
EEEE CCCC EEEE CCCC
b
M
c1
C A-B
S
D
S
SECTION B-B
Mfax is a trademark of Motorola, Inc.
MCM69T618/D MOTOROLA FAST SRAM

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