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INTEGRATED CIRCUITS
74ABT16823A 74ABTH16823A 18-bit bus interface D-type flip-flop with reset and enable (3-State)
Product specification Supersedes data of 1995 Sep 28 IC23 Data Handbook 1998 Feb 27
Philips Semiconductors
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop with reset and enable (3-State)
74ABT16823A 74ABTH16823A
FEATURES
* Two sets of high speed parallel registers with positive
edge-triggered D-type flip-flops
DESCRIPTION
The 74ABT16823A 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. The 74ABT16823A has two 9-bit wide buffered registers with Clock Enable (nCE) and Master Reset (nMR) which are ideal for parity bus interfacing in high microprogrammed systems. The registers are fully edge-triggered. The state of each D input, one set-up time before the Low-to-High clock transition is transferred to the corresponding flip-flop's Q output. Two options are available, 74ABT16823A which does not have the bus-hold feature and 74ABTH16823A which incorporates the bus-hold feature.
* Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
* Live insertion/extraction permitted * Power-up 3-State * 74ABTH16823A incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused inputs
* Power-up Reset * Output capability: +64mA/-32mA * Latch-up protection exceeds 500mA per Jedec Std 17 * ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CIN COUT ICCZ ICCL PARAMETER Propagation delay nCP to nQx Input capacitance Output capacitance Quiescent su ly current supply CONDITIONS Tamb = 25C; GND = 0V CL = 50pF; VCC = 5V VI = 0V or VCC VO = 0V or VCC; 3-State Outputs disabled; VCC = 5.5V Outputs low; VCC = 5.5V TYPICAL 2.3 1.9 4 6 500 9 UNIT ns pF pF A mA
ORDERING INFORMATION
PACKAGES 56-Pin Plastic SSOP Type III 56-Pin Plastic TSSOP Type II 56-Pin Plastic SSOP Type III 56-Pin Plastic TSSOP Type II TEMPERATURE RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C OUTSIDE NORTH AMERICA 74ABT16823A DL 74ABT16823A DGG 74ABTH16823A DL 74ABTH16823A DGG NORTH AMERICA BT16823A DL BT16823A DGG BH16823A DL BH16823A DGG DWG NUMBER SOT371-1 SOT364-1 SOT371-1 SOT364-1
PIN DESCRIPTION
PIN NUMBER 2, 27 54, 52, 51, 49, 48, 47, 45, 44, 43 42, 41, 40, 38, 37, 36, 34, 33, 31 3, 5, 6, 8, 9, 10, 12, 13, 14 15, 16, 17, 19, 20, 21, 23, 24, 26 56, 29 55, 30 1, 28 4, 11, 18, 25, 32, 39, 46, 53 7, 22, 35, 50 1998 Feb 27 SYMBOL 1OE, 2OE 1D0-1D8 2D0-2D8 1Q0-1Q8 2Q0-2Q8 1CP, 2CP 1CE, 2CE 1MR, 2MR GND VCC 2 FUNCTION Output enable input (active-Low) Data inputs Data outputs Clock pulse input (active rising edge) Clock enable input (active-Low) Master reset input (active-Low) Ground (0V) Positive supply voltage 853-1791 19025
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop with reset and enable (3-State)
74ABT16823A 74ABTH16823A
PIN CONFIGURATION
1MR 1OE 1Q0 GND 1Q1 1Q2 VCC 1Q3 1Q4 1Q5 GND 1Q6 1Q7 1Q8 2Q0 2Q1 2Q2 GND 2Q3 2Q4 2Q5 VCC 2Q6 2Q7 GND 2Q8 2OE 2MR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1CP 1CE 1D0 GND 1D1 1D2 VCC 1D3 1D4 1D5 GND 1D6 1D7
LOGIC SYMBOL (IEEE/IEC)
1OE 1MR 1CE 1CP 2OE 2MR 2CE 2CP 1D0 1D1 1D2 1D3 1D4 1D8 1D5 2D0 1D6 2D1 1D7 2D2 1D8 GND 2D0 2D3 2D1 2D4 2D5 VCC 2D6 2D7 GND 2D8 2CE 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2 1 55 56 27 28 30 29 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 8D 5, 6 EN1 R2 G3 3C4 EN5 R6 G7 7C8 4D 1, 2 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 25 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8
SH00015
2CP
SH00014
1998 Feb 27
3
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop with reset and enable (3-State)
74ABT16823A 74ABTH16823A
LOGIC DIAGRAM
nCE
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
nD8
nCP CP CP CP CP nD CP CP CP CP CP
nD
nD
nD
nD
nD
nD
nD
nD
R
Q
R
Q
R
Q
R
Q
R
Q
R
Q
R
Q
R
Q
R
Q
nMR
nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 nQ8
n = 1 or 2
SH00016
FUNCTION TABLE
INPUTS nOE L L L L H= h= L= l= NC= X= Z= = = nMR L H H H nCE X L L H nCP X nDx X h l X OUTPUTS nQ0 - nQ8 L H L NC Hold High impedance Clear Load and read data OPERATING MODE
H X X X X Z High voltage level High voltage level one set-up time prior to the Low-to-High clock transition Low voltage level Low voltage level one set-up time prior to the Low-to-High clock transition No change Don't care High impedance "off" state Low to High clock transition Not a Low-to-High clock transition
1998 Feb 27
4
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop with reset and enable (3-State)
74ABT16823A 74ABTH16823A
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL VCC IIK VI IOK VOUT IO OUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 VO < 0 output in Off or High state output in Low state DC output current output in High state Storage temperature range -64 -65 to 150 C VI < 0 CONDITIONS RATING -0.5 to +7.0 -18 -1.2 to +7.0 -50 -0.5 to +5.5 128 mA UNIT V mA V mA V
DC output diode current DC output voltage3
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VI VIH VIL IOH IOL t/v Tamb DC supply voltage Input voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature range 0 -40 PARAMETER MIN 4.5 0 2.0 0.8 -32 64 10 +85 MAX 5.5 VCC V V V V mA mA ns/V C UNIT
1998 Feb 27
5
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop with reset and enable (3-State)
74ABT16823A 74ABTH16823A
DC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25C MIN VIK Input clamp voltage VCC = 4.5V; IIK = -18mA VCC = 4.5V; IOH = -3mA; VI = VIL or VIH VOH High-level output voltage VCC = 5.0V; IOH = -3mA; VI = VIL or VIH VCC = 4.5V; IOH = -32mA; VI = VIL or VIH VOL VRST II Low-level output voltage Power-up output low voltage3 Input leakage curent In ut VCC = 4.5V; IOL = 64mA; VI = VIL or VIH VCC = 5.5V; IOL = 1mA; VI = GND or VCC VCC = 5.5V VI = VCC or GND 5.5V; VCC = 5.5V; VI = VCC or GND II Input leakage current In ut 74ABTH16823A VCC = 5.5V; VI = VCC VCC = 5.5V; VI = 0 VCC = 4.5V; VI = 0.8V IHOLD Bus Hold current inputs5 74ABTH16823A VCC = 4.5V; VI = 2.0V VCC = 5.5V; VI = 0 to 5.5V IOFF IPU/PD IOZH IOZL ICEX IO ICCH ICCL ICCZ ICC Additional supply current per input pin2 Quiescent supply current Power-off leakage current Power-up/down 3-State output current4 3-State output High current 3-State output Low current Output High leakage current Output current1 VCC = 0.0V; VO or VI 4.5V VCC = 2.1V; VO = 0.5V; VI = GND or VCC, VOE = Don't care VCC = 5.5V; VO = 2.7V; VI = VIL or VIH VCC = 5.5V; VO = 0.5V; VI = VIL or VIH VCC = 5.5V; VO = 5.5V; VI = GND or VCC VCC = 5.5V; VO = 2.5V VCC = 5.5V; Outputs High, VI = GND or VCC VCC = 5.5V; Outputs Low, VI = GND or VCC VCC = 5.5V; Outputs 3-State; VI = GND or VCC VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND -50 35 -75 800 5.0 5.0 1.0 -1.0 50 -80 0.5 9.0 0.5 0.2 100 50 10 -10 50 -180 1 19 1 1 -50 100 50 10 -10 50 -180 1 19 1 1 A A A A A mA mA mA mA mA Control pins Data pins -2 -3 35 -75 A -5 2.5 3.0 2.0 TYP -0.9 2.9 3.4 2.4 0.42 0.13 0.01 0.01 0.01 0.55 0.55 1 1 1 MAX -1.2 2.5 3.0 2.0 0.55 0.55 1 1 1 Tamb = -40C to +85C MIN MAX -1.2 V V V V V V A A A A UNIT
NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V 10% a transition time of up to 100sec is permitted. 5. This is the bus hold overdrive current required to force the input to the opposite logic state.
1998 Feb 27
6
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop with reset and enable (3-State)
74ABT16823A 74ABTH16823A
AC CHARACTERISTICS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM MIN fMAX tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ Maximum clock frequency Propagation delay nCP to nQx Propagation delay nMR to nQx Output enable time to High and Low level Output disable time from High and Low level 1 1 2 4 5 4 5 140 1.4 1.2 2.0 1.3 1.2 1.7 1.6 Tamb = +25C VCC = +5.0V TYP 190 2.3 1.9 3.3 2.4 2.1 2.9 2.3 3.2 2.6 4.3 3.2 2.9 4.0 3.2 MAX Tamb = -40C to +85C VCC = +5.0V 0.5V MIN 140 1.4 1.2 2.0 1.3 1.2 1.7 1.6 3.7 2.9 5.0 3.9 3.4 4.7 3.4 MAX MHz ns ns ns ns UNIT
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM Tamb = +25C VCC = +5.0V MIN ts(H) ts(L) th(H) th(L) tw(H) tw(L) ts(H) ts(L) th(H) th(L) tw(L) trec Setup time, High or Low nDx to nCP Hold time, High or Low nDx to nCP nCP pulse width High or Low Setup time, High or Low nCE to nCP Hold time, High or Low nCE to nCP nMR pulse width, Low Recovery time nMR to nCP 3 3 1 3 3 2 2 2.0 1.5 1.5 1.5 3.3 3.3 1.5 2.0 1.5 1.5 3.0 2.5 TYP 1.3 0.9 -0.9 -1.2 1.7 1.7 0.9 0.9 -0.8 -0.9 1.7 1.0 Tamb = -40 to +85C VCC = +5.0V 0.5V MIN 2.0 1.5 1.5 1.5 3.3 3.3 1.5 2.0 1.5 1.5 3.0 2.5 ns ns ns ns ns ns ns UNIT
1998 Feb 27
7
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop with reset and enable (3-State)
74ABT16823A 74ABTH16823A
AC WAVEFORMS
For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance.
3.0V or VCC whichever is less 0V tPZH tPHZ VOH VOH-0.3V 0V
1/fMAX
nCP
VM tw(H) tPHL tw(L)
VM tPLH
3.0V or VCC whichever is less 0V
nOE VM VM
VOH nQx VM VM 0V nQx
VM
SH00020 SH00017
Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency
Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level
nMR
VM tw(L)
VM tREC VM tPHL
3.0V or VCC whichever is less 0V 3.0V or VCC whichever is less 0V VOH
3.0V or VCC whichever is less nOE VM VM 0V tPZL tPLZ 3.0V or VCC whichever is less VOL +0.3V VOL
nCP
nQx
VM
nQx
VM 0V SH00018
SH00021
Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
Waveform 2. Master Reset Pulse WIdth, Master Reset to Output Delay and Master Reset to Clock Recovery Time
nDx, nCE ts(H) nCP
VM
VM th(H) VM ts(L)
VM
VM th(L) VM
3.0V or VCC whichever is less 0V 3.0V or VCC whichever is less 0V
SH00019
Waveform 3. Data Setup and Hold Times
1998 Feb 27
8
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop with reset and enable (3-State)
74ABT16823A 74ABTH16823A
TEST CIRCUIT AND WAVEFORM
VCC 7.0V VIN PULSE GENERATOR RT D.U.T. VOUT RL NEGATIVE PULSE 90% VM 10% tTHL (tf ) CL RL tTLH (tr ) 90% POSITIVE PULSE 10% tTHL (tf ) AMP (V) 90% VM tW 10% 0V tW VM 10% tTLH (tr ) 0V AMP (V)
90%
Test Circuit for 3-State Outputs SWITCH POSITION TEST tPLZ tPZL All other SWITCH closed closed open
VM
VM = 1.5V Input Pulse Definition
DEFINITIONS: RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
INPUT PULSE REQUIREMENTS FAMILY Amplitude 74ABT16 3.0V Rep. Rate 1MHz tw 500ns tR 2.5ns tF 2.5ns
SH00022
1998 Feb 27
9
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop with reset and enable (3-State)
74ABT16823A 74ABTH16823A
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
1998 Feb 27
10
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop with reset and enable (3-State)
74ABT16823A 74ABTH16823A
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
SOT364-1
1998 Feb 27
11
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop with reset and enable (3-State)
74ABT16823A 74ABTH16823A
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-03502
Philips Semiconductors
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