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UCB1510
AC97 digital modem codec
Rev. 01 -- 4 February 2000 Preliminary specification
1. Description
The UCB1510 is a single chip, integrated mixed signal telecom codec that can directly be connected to a DAA and supports high speed modem protocols. The general purpose I/O pins provide programmable inputs and/or outputs to the system. The UCB1510 has a serial AClink interface intended to communicate to the system controller. Both the codec input data and codec output data and the control register data are multiplexed on this interface.
2. Features
s Sigma delta telecom codec with programmable sample rate, including digitally controlled input voltage level, mute, loop back and clip detection functions. The telecom codec can be directly connected to a Data Access Arrangement (DAA) and includes a built in sidetone suppression circuit s AClink (rev 2.1) interface with secondary codec support s 3.3 V supply voltage and built in power saving modes make the UCB1510 optimal for portable and battery powered applications s 5 V tolerant interface for motherboard/PC add on s Maximum operating current 25 mA s 8 general purpose IO pins for line interface control s Interrupt detection driven wake up sequence for ring detect s Low cost 12.288 MHz crystal
c c
3. Applications
s s s s Standalone modems Integrated modems Audio/Modem Riser (AMR) Cards Mobile Daughter Cards (MDC)
Philips Semiconductors
UCB1510
AC97 digital modem codec
4. Ordering information
Table 1: Ordering information Package Name UCB1510DB SSOP28 Description plastic shrink small outline package, 28 leads, body width 5.3mm Version SOT341-1 Type number
5. Block diagram
A0
PON
TINP ADC TINN
down sample filter
Line1 PCM flow
Serial bus interface
SDOUT SDIN SYNC
TOUTP DAC TOUTN
up sample filter
data / control registers
RESET BIT_CLK
Clock buffers & sample rate dividers Voltage reference
VREFBYP
GPIO
XTAL_IN/A1
XTAL_OUT
IO[7:0]
Fig 1. Block diagram
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6. Pinning information
6.1 Pinning
VDDD IO0 IO1 IO2 IO3 RESET A0 PON SYNC
1 2 3 4 5 6 7 8 9
28 27 26 25 24 23 22
XTAL_OUT XTAL_IN/A1 VSSA TINN TINP VREFBYP TOUTN TOUTP VDDA VSSD IO7 IO6 IO5 IO4
UCB1510
21 20 19 18 17 16 15
SDOUT 10 VSSD 11 SDIN 12 BIT_CLK 13 VDDD 14
Fig 2. Pin configuration
6.2 Pin description
Table 2: Symbol VDDD IO0 IO1 IO2 IO3 RESET A0 PON SYNC SDOUT VSSD SDIN BIT_CLK VDDD IO4 Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reset state [1] input input input input 0 [4] - [3] input Type [2] S I/OC I/OC I/OC I/OC IC IC IC I/OC IC S OC I/OC S I/OC Description digital supply general purpose I/O pins general purpose I/O pins general purpose I/O pins general purpose I/O pins asynchronous reset input address select (for secondary codec) inverted polarity asynchronous cold reset AClink synchronization input AClink data input digital ground AClink data output AClink serial interface clock digital supply general purpose I/O pins
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AC97 digital modem codec
Pin description...continued Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 Reset state [1] input input input hi Z hi Z hi Z - [3] - [3] Type [2] I/OC I/OC I/OC S S OA OA I/OA IA IA S IA/IC OA Description general purpose I/O pins general purpose I/O pins general purpose I/O pins digital ground analog supply positive telecom codec output negative telecom codec output external reference voltage bypass positive telecom codec input negative telecom codec input analog ground Xtal oscillator/master clock input or inverted secondary address Xtal oscillator output
Table 2: Symbol IO5 IO6 IO7 VSSD VDDA TOUTP TOUTN
VREFBYP TINP TINN VSSA XTAL_IN/A1 XTAL_OUT
[1] [2] [3] [4]
After cold or warm reset, the AClink interface is active with MLNK bit reset. I/OC = CMOS bidirectional; ID = digital input; S = supply; OA = analog output; IC = CMOS input; IA = analog input; I/OA = analog bidirectional; OC = CMOS output. BIT_CLK is an input for AClink secondary codec, an output for primary codec. When BIT_CLK is an output, the XTAL oscillator is active. SDIN is driving a 0 until a valid SYNC framing signal is received after cold reset.
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AC97 digital modem codec
7. Functional description
The functional description of the devices id described in Section 8 through Section 15.
8. Telecom codec
The telecom codec contains an input channel, built up from a 64 times oversampling sigma delta analog to digital converter (ADC) with digital decimation filters, programmable gain and attenuation and built-in sidetone suppression circuit. The output path consists of a digital up sample filter, a 64 time oversampling 4 bit digital to analog converter (DAC) circuit with integrated filter followed by a differential output driver, capable of directly driving a 600 isolation transformer. The output path includes a mute function. The telecom codec also incorporates loop back modes, in which codec output path and the input path are connected in series. The loop back tap and entry points are identified as circled letters in Figure 3, loop back modes are described in the AClink register definition.
sidetone_enable
ADC[3:2]
TINP TINN
SIDETONE SUPPRESSION CIRCUIT
ADC
J
H
DIGITAL DECIMATION FILTER
14
G
TOUTP
E
TOUTN
D
DAC
C
DIGITAL NOISE SHAPER
14
B
DAC Mute
Fig 3. Telecom codec block diagram
The telecom sample rate (fst) is derived from the AC master clock and is programmable using the sample rate registers. Not all AC97 specified sample rates are supported, refer to Table 3 "Sampling frequencies" for details. PCM data is transferred in the slot 5 of the AClink.
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AC97 digital modem codec
Sampling frequencies Register 0x40 value 0x1C20 0x1F40 0x2024 0x20D0 0x2328 0x2580 0x282D 0x2EE0 0x3592 0x3E80 0x4B00 0x5DC0 0xBB80 Support no yes no no no yes no yes yes yes yes yes no AC `97 requirements recommended required recommended recommended recommended required recommended recommended required required recommended recommended recommended
Table 3:
Sampling frequency (Hz) 7200 8000 8228.57 (57600/7) 8400 9000 9600 10285.71 (72000/7) 12000 13714.29 (96000/7) 16000 19200 24000 48000
Any programmed vlaue above 24 kHz will lead to a 24 kHz sampling rate. Changing the sampling rate while the codec is active may lead to unpredictable results in the ADC and DAC chains and should be avoided. The output section of the telecom codec is designed to interface with a 600 line through an isolation transformer. The built in mute function is activated by the DAC Mute bit in register 0x46. The output driver remains active in the mute mode, however no output signal is produced.
8.1 Digital filters
These filters are tailored for high speed modem performance. A voice band filter can be activated to reduce the noise in the lower frequencies.
Table 4: Filter characteristics Condition Value 25 samples 0.1 dB >0.55 fs (no voice band filter) 0-0.0018 fs -50 dB 0.0016 to 0.45 fs 0.45 to 0.55 fs 30 dB 0.05 fs
Parameter Group delay Pass band ripple Out of band rejection Pass band Transition band Voice band filter rejection band Voice band filter cutoff frequency
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8.2 Analog interface
UCB1510
TOUTP Ro
Rg 1:1 transformer A
Central Office
TINP Ri Rs
+ + Rg
Rt
Rt
B
Rt
Rt TINN Ro TOUTN
Rs Ri
Fig 4. Typical telecom codec sidetone suppression circuit (without protection circuits).
An important built-in feature of the telecom codec is the sidetone suppression circuit. The sidetone suppression circuit is activated when sidetone_enable of register 0x5A is set.The sidetone suppression circuit subtracts part of the telecom output signal from the telecom input signal. As a result the available dynamic range of the input path can be more effectively utilized. If the sidetone suppression circuit is disabled, the telecom input dynamic range can be largely occupied by the telecom output signal. The built-in side tone suppression circuit, shown in Figure 4, has a fixed subtraction ratio, set be the resistors Rs and Ri, which equals 600456. This ratio is calculated from the following relations. The impedance seen by the telephone line equals: Ro x Ri Z line = 2 x R t + R t + ----------------- , differential, in which Rt represents winding resistance R +R
o i
of the transformer, divided by 2. Assuming Ri >> Ro, then R line = R t + R t + R o = 600 2 = 300 single ended. A typical transformer has 156 winding impedance, thus Ro should be 144 . The ratio of the telecom input and output voltage is, therefore: 456 156 + 300 V i(tel) = V o(tel) x --------------------------------------- = V o(tel) x -------600 156 + 300 + 144 Proper sidetone suppression thus requires Rs/Ri to be Vi/Vo.
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AC97 digital modem codec
9. On-chip reference circuit
The UCB1510 contains an on chip reference voltage source, which generates the bias currents and the virtual analog ground. Alternatively the UCB1510 can be driven from an external reference voltage source.
Bias ENA
vref_external
&
internal analog ground
ena internal bandgap Vbg reference voltage circuitry
&
VREFBYP
vref_bypass
Fig 5. Block diagram of the reference circuit.
Two bits in the control register 0x5A determine the mode of operation of this reference voltage circuit. vref_bypass connects the internal reference voltage to the VREFBYP pin, while vref_external disables the internal reference voltage and switches the UCB1510 into the external voltage reference mode. If the internal reference voltage is connected to the VREFBYP pin, an external capacitor could be connected to filter this reference voltage. When choosing a capacitor, the internal impedance (around 50 k) should be taken into account. If vref_external is set, an external voltage reference connected to the VREFBYP pin is used as the voltage reference by UCB1510.
10. Power supply strategy
Since all the control logic of the UCB1510 is powered by the VDDD, power should always be present on this pin for interrupts to be possible. VDDA needs not be present all the time although it is recommended to use the control bits to turn OFF the analog sections.
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AC97 digital modem codec
11. Register definition
11.1 Supported registers
Table 5: Register 0x00 to 0x3A 0x3C 0x3E 0x40 0x42 and 0x44 0x46 0x48 and 0x4A 0x4C 0x4E 0x50 0x52 0x54 0x56 0x58 0x5A 0x5C 0x5E 0x5E to 0x7A 0x7C 0x7E Supported registers Name All audio registers are ignored Extended Modem ID Extended Modem Status and Control Line1 DAC/ADC Rate Reserved for future use Line1 DAC/ADC Level Reserved for future use GPIO Pin Configuration GPIO Pin Polarity GPIO Pin Sticky GPIO Pin Wake-up Mask GPIO Pin Status Miscellaneous Modem AFE Status and Control Ignored Codec control Mode control Test control Ignored Vendor ID1 Vendor ID2
11.2 Register detail
Shaded areas indicate read only data. 11.2.1 Extended Modem ID
Table 6: Extended Modem ID Register Register address: 0x3C; default: N/A Bit Symbol Bit Symbol Table 7: Bit D15:14 D0
[1]
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D15 ID1 D7
D14 ID0 D6
D13 D5
D12 D4 0
D11 D3 0
D10 D2 0
D9 D1 0
D8 D0 LIN1
Description of Extended Modem ID bits Symbol Function/Value ID[1:0] LIN1 {A1,A0} where A0 is the inverse polarity of the A0 pin. A1 is the inverse polarity of XTAL_IN pin if A0 is HIGH (A0 pin is LOW), otherwise A1 is 0. Line 1 support indicator = 1 (i.e., Line 1 is supported).
Writing this register will cause a register reset: all modem registers will then take their default values.
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AC97 digital modem codec
11.2.2
Extended Modem Status and Control
Table 8: Extended Modem Status and Control Register Register address: 0x3E; default: 0xFFxx Bit Symbol Bit Symbol Table 9: Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 PRH D7 HDAC D14 PRG D6 HADC D13 PRF D5 DAC2 D12 PRE D4 ADC2 D11 PRD D3 DAC1 D10 PRC D2 ADC1 D9 PRB D1 MREF D8 PRA D0 GPIO
Description of Extended Modem status and Control bits Symbol Function/Value PRH PRG PRF PRE PRD PRC PRB PRA HDAC HADC DAC2 ADC2 DAC1 ADC1 MREF GPIO Reserved, should be 1 Reserved, should be 1 Reserved, should be 1 Reserved, should be 1 1 -> Line1 DAC OFF 1 -> Line1 ADC OFF 1 -> Line1 VREF OFF 1 -> GPIO OFF 0 (not supported) 0 (not supported) 0 (not supported) 0 (not supported) 1 indicates Line1 DAC ready (means that the Line1 DAC and the VREF are enabled and ready) 1 indicates Line1 ADC ready (means that the Line1 ADC and the VREF are enabled and ready) 1 indicates Line1 VREF up to nominal level. 1 indicates GPIO ready.
11.2.3
Line 1 Sample Rate
Table 10: Line 1 Sample Rate Register Register address: 0x40; default: 0x1F40 Bit Symbol Bit Symbol D15 SR15 D7 SR7 D14 SR14 D6 SR6 D13 SR13 D5 SR5 D12 SR12 D4 SR4 D11 SR11 D3 SR3 D10 SR10 D2 SR2 D9 SR9 D1 SR1 D8 SR8 D0 SR0
Refer to Table 3 "Sampling frequencies" for supported sample rates.
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AC97 digital modem codec
11.2.4
Line 1 DAC/ADC Level
Table 11: Line 1 DAC/ADC Level Register Register address: 0x46; default: 0x8080 Bit Symbol Bit Symbol D15 DAC mute D7 ADC mute D6 D5 D4 D3 ADC3 D2 ADC2 D1 ADC1 D0 ADC0 D14 D13 D12 D11 D10 D9 D8
Table 12: Description of Line1 DAC/ADC Level bits Bit D15 D7 D3-D2 D1-D0 Symbol DAC mute ADC[3:2] ADC[1:0] Function/Value DAC section is active, but no signal will be sent. ADC Gain (0 -> 0 dB, 1 -> 6 dB, 2 -> 12 dB, 3 -> 18 dB) These bits are ignored.
ADC mute ADC section is active, but no signal will be sent.
11.2.5
GPIO Pin Configuration
Table 13: GPIO Pin Configuration Register Register address: 0x4C; default: 0x00FF Bit Symbol Bit Symbol D7 GC7 D6 GC6 D5 GC5 D4 GC4 D3 GC3 D2 GC2 D1 GC1 D0 GC0 D15 D14 D13 D12 D11 D10 D9 D8
The GPIO Pin Configuration register specifies whether a GPIO pin is configured for input (1) or for output (0). 11.2.6 GPIO Pin Polarity
Table 14: GPIO Pin Polarity Register Register address: 0x4E; default: 0xFFFF Bit Symbol Bit Symbol D7 GP7 D6 GP6 D5 GP5 D4 GP4 D3 GP3 D2 GP2 D1 GP1 D0 GP0 D15 D14 D13 D12 D11 D10 D9 D8
The GPIO Pin Polarity register defines GPIO Input Polarity (0 = Low, 1 = High) when a GPIO pin is configured as an input.
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AC97 digital modem codec
11.2.7
GPIO Pin Sticky
Table 15: GPIO Pin Sticky Register Register address: 0x50; default: 0x0000 Bit Symbol Bit Symbol D7 GS7 D6 GS6 D5 GS5 D4 GS4 D3 GS3 D2 GS2 D1 GS1 D0 GS0 D15 D14 D13 D12 D11 D10 D9 D8
The GPIO Pin Sticky register defines GPIO Input Type (0 = Non-Sticky, 1 = Sticky) when a GPIO pin is configured as input. Sticky is defined as Edge sensitive, Non-Sticky as Level-sensitive. GPIO inputs configured as Sticky are cleared by writing a 0 to the corresponding bit of the GPIO Pin Status register 0x54, and by reset. Remark: Changing GPIO control registers while a GPIO is sticky may cause unwanted interrupts and should be done carefully. 11.2.8 GPIO Wake-up Mask
Table 16: GPIO Wake-up Mask Register Register address: 0x52; default: 0x0000 Bit Symbol Bit Symbol D7 GW7 D6 GW6 D5 GW5 D4 GW4 D3 GW3 D2 GW2 D1 GW1 D0 GW0 D15 D14 D13 D12 D11 D10 D9 D8
The GPIO Pin Wake-up Mask register provides a mask for determining if an input GPIO change will generate a wake-up or GPIO_INT (0 = No, 1 = Yes). When the AC-link is powered down, a wake-up event will trigger the assertion of SDIN. When the AC-link is powered up, a wake-up event will appear as GPIO_INT = 1 on bit 0 of input slot 12. 11.2.9 GPIO Pin Status
Table 17: GPIO Pin Status Register Register address: 0x54; default: N/A Bit Symbol Bit Symbol D7 GI7 D6 GI6 D5 GI5 D4 GI4 D3 GI3 D2 GI2 D1 GI1 D0 GI0 D15 D14 D13 D12 D11 D10 D9 D8
The GPIO Status register reflects the state of all GPIO pins (inputs and outputs) on slot 12. When the GPIO is an output pin, the value set on slot #12 is transmitted directly to the pin. When the GPIO pin is a non-sticky input, the status of the pin is accessible in read mode. When the GPIO is a sticky Input, a transition, either from high to low (polarity = 0) or from low-to-high (polarity = 1), will assert the corresponding GI bit to 1. The GI bit will remain asserted until it is cleared by a write of 0.
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11.2.10
Miscellaneous Modem AFE Status and Control
Table 18: Miscellaneous Modem AFE Status and Control Register Register address: 0x56; default: 0x0000 Bit Symbol Bit Symbol D7 D6 D15 D14 D13 MLNK D5 D4 D3 reserved, should be 0x0 D12 D11 D10 D2 L1B2 D9 D1 L1B1 D8 D0 L1B0 reserved, should be 0x0
Table 19: Description of Miscellaneous Modem AFE Status and Control bits Bit D13 D[2:0] Symbol MLNK L1B[2:0] Function/Value 1 -> AClink goes to sleep. Line1 loop back modes (refer to Table 20).
Table 20: Loop back modes See Figure 3. Mode 0 1 2 Description Disabled ADC loop back (incoming analog signal is amplified, digitized, down-sampled, LOOPED, up-sampled, converted to analog, amplified/filtered) (G) to (B) loop. Local analog loop back (digital signal is up-sampled, converted to analog, amplified/filtered, LOOPED, amplified, digitized, down-sampled, sent back) (E) to (J) loop. DAC loop back (digital signal is up-sampled, converted to analog, LOOPED digitized, down-sampled, sent back) (E) to (J) loop. Same as mode 2. Remote analog loop back (incoming analog signal is amplified, LOOPED, amplified/filtered, sent back) (J) to (D) loop. Digital loop back: signal is captured from the AC-link and sent back as is. Slot request for slot#5 is controlled according to the programmed sampling rate.
3 4 7
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AC97 digital modem codec
11.2.11
Vendor Specific Codec Control
Table 21: codec_control Register Register address: 0x5A; default: 0x0400 Bit Symbol Bit Symbol D7 0 D6 0 D5 0 D15 D14 D13 D12 AC D4 SE D3 0 D11 D10 ME D2 0 D9 VE D1 0 D8 VB D0 VF
Table 22: codec_control bits Bit D12 D10 D9 D8 D[7:5], D[3:1] D4 D0 Symbol AC ME VE VB 0 SE VF Function/Value adc_clip, in read mode, this bit indicates clipping in the line1 ADC. This indicator is sticky and should be cleared by writing it with a 0. reserved, should be 1 vref_external, overwrites VB vref_bypass Bits marked `0' are reserved for future use and should be programmed with 0. sidetone_enable voice_filter:1->enable voice band digital filter.
11.2.12
Vendor Specific Mode Control
Table 23: mode_control Register Register address: 0x5C; default: 0x0000 Bit Symbol Bit Symbol
[1]
D15 D7
D14 D6 0
D13 D5 0
D12 D4 0
D11 D3
D10 D2
D9 reserved: 0x0 D1 0
D8 D0 BITSTREAM
Bits marked 0 are reserved for future use and should be programmed with 0.
Table 24: mode_control bits Bit D0 Symbol Function/Value BITSTREAM line1 ADC bitstream data is sent directly to IO4. The associated clock is sent to IO6.
11.2.13
Vendor specific Test Control
Table 25: Test_control Register Register address: 0x5E; default: N/A Bit Symbol Bit Symbol D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8
This register cannot be reset. It has no effect until the IC is put in vendor test mode (see Table 29 "Mode selection with AC pins").
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11.2.14
Vendor ID1
Table 26: Vendor ID1 Register Register address: 0x7C; default: 0x5053 Bit Symbol Bit Symbol D15 0 D7 0 D14 1 D6 1 D13 0 D5 0 D12 1 D4 1 D11 0 D3 0 D10 0 D2 0 D9 0 D1 1 D8 0 D0 1
11.2.15
Vendor ID2
Table 27: Vendor ID2 Register Register address: 0x7E; default: 0x4301 Bit Symbol Bit Symbol D15 0 D7 0 D14 1 D6 0 D13 0 D5 0 D12 0 D4 0 D11 0 D3 0 D10 0 D2 0 D9 1 D1 0 D8 1 D0 1
11.3 Register reset modes
11.3.1 Warm reset When a warm reset is activated, MLNK is set to 0 but the other registers retain their values. If the codec is primary, the BIT_CLK is started and stabilized after 200 ms. 11.3.2 Cold reset When a cold reset is activated, MLNK is set to 0 and all registers are programmed to their default values. If the codec is primary, the BIT_CLK is started and stabilized after 200 ms. 11.3.3 Register reset A register reset causes all registers to return to their default values. Initiated by a write to register 0x3C.
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12. AC97 interface
12.1 Control register data transfer
The AClink frames is made of 13 slots. Slot0 is a 16-bit long tag slot, the remaining 12 slots are 20-bit long data transfer.
48KHz SYNC
Clock:12.288MHz SDOUT (SLOT #)
16 bits
20bits
#0 SLOT #0: TAG
#1 SLOT #1: CMD ADDR
#2 SLOT #2: CMD DATA
#3
#4
#5 SLOT #5: LINE1 DAC
#6
#7
#8
#9
#10
#11
#12 SLOT #12: I/O CTRL
#0
SLOT #3 & #4: not supported by UCB1510
Fig 6. AClink frame slot definition
Register update is done at the end of slot 2. The new register value is effective thereafter. Slot #0 and slot #3 to #12 are shared by all codecs (primary and secondary). Multiple codecs using the same slot cannot be used at the same time. Slot #1 and slot #2 are used for register transfer and are codec specific. Addressing is defined in the Tag slot #0: The UCB1510 will send a 1 as Tag slot bit 15 whenever the AClink is active (MLNK is 0).
SLOT #6.. #9: not supported by UCB1510
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SYNC SYNC SDOUT (bit numbers) BIT_CLK BIT_CLK SDIN (bit numbers) Bit 15: If 1 then Valid Frame; if 0 then frame can be ignored
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Bit 15: If 1 then Valid Frame; if 0 then frame can be ignored
Bit 14: If 1 then Slot #1 (CMD_ADDR) is valid
Bit 13: If 1 then Slot #2 (CMD_DATA) is valid
Bit 14: If 1 then Slot #1 (CMD_ADDR) is valid
Bit 12: If 1 then Slot #3 is valid - should be 0 for UCB1510 Bit 11: If 1 then Slot #4 is valid - should be 0 for UCB1510 Bit 10: If 1 then Slot #5 (Line 1) is valid Bit 9: If 1 then Slot #6 is valid - should be 0 for UCB1510 Bit 8: If 1 then Slot #7 is valid - should be 0 for UCB1510 Bit7: If 1 then Slot #8 is valid - should be 0 for UCB1510 Bit 6: If 1 then Slot #9 is valid - should be 0 for UCB1510 Bit 5: If 1 then Slot #10 is valid - should be 0 for UCB1510 Bit 4: If 1 then SLot #11 s valid - should be 0 for UCB1510 Bit3: If 1 then Slot #12 (I/O Control) is valid Bit 2: Unused, set to 0 Bit 1: Codec ID A1 Bit 0: Codec ID A0 Bit 19: Read/Write (1-> read) Bit 18: Register index[6] Bit 17: Register index[5] Bit 16: Register index[4] Bit 15: Register index[3]
Bit 13: If 1 then Slot #2 (CMD_DATA) is valid
Bit 12: 0
Fig 8. Tag slot bit definition (codec to controller)
0 15 14 13 12 11 10 9 0 15 14 13 12 11 10 9 8 8 16 BIT_CLKs 16 BIT_CLKs 7 7 6 6 SLOT #0 SLOT #0 5 5 4 4
Fig 7. Tag slot bit definition (controller to codec)
Bit 11: 0
Bit 10: If 1 then Slot #5 is valid
Bit 9: 0
Bit 8: 0
Bit7: I0
Bit 6: 0
Bit 5: 0 3
Rev. 01 -- 4 February 2000
2 1 SLOT #1 0 19 18 17 16 15
Bit 4: 0
3
Bit3: If 1 then Slot #12 (I/O Control) is valid
2
Bit 2: Unused, set to 0
1
Bit 1: 0
Bit 0: 0 Bit 19: Register_read
Bit 18: Register index[6]
Bit 17: Register index[5]
SLOT #1
Bit 16: Register index[4]
0 19 18 17 16 15
AC97 digital modem codec
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Bit 15: Register index[3]
UCB1510
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12.2 Codec addressing
Table 28: Codec addressing examples CMD ADDR slot #0 bit 14 0 1 1 x x CMD DATA slot #0 bit 13 0 x 1 x x Codec ID (A1, A0) slot #0 bits 1 and 0 00 00 00 01 11 Read/Write slot #1 bit 19 x 1 0 1 0 idle primary read primary write secondary read secondary write No register data is transferred, slots 1 and 2 are not valid Read for primary codec register Write to a primary codec register Read from the 01 secondary codec register Write to a 11 secondary codec register Transfer Description
12.2.1
Primary codec addressing For addressing a primary codec, bits 1 and 0 of the Tag slot (codec ID A1 and A0) should be 0. The bits 13 and 14 are used for register data transfer. When the controller is not sending/receiving control data, it should be addressing the primary codec. When writing to a register, the bits 14 and 13 (ADDR and DATA valid) should be set to 1. When reading from a register, only the bit 14 is required to be 1.
12.2.2
Secondary codec addressing When the Codec ID (A1,A0) is not 00, the controller is addressing a secondary codec in a read or write sequence. The direction is defined in the slot 1 read/write bit (bit 19).
12.3 PCM sample transfer
Since the AClink frame frequency is defined to be 48kHz, exchanging samples with the controller at a different sampling rate requires the support of on demand sample transfer (slot request). The UCB1510 will send samples to the controller and assert the slot 5 valid bit in the slot#0 (bit10)of the AClink frame. When it needs a new sample from the controller, it will put a 0 on the slot5req bit in the slot#1 (bit9) of the AClink frame. When the slot5req bit is 1, it indicates to the controller that no new sample is needed. When the DAC is not active, the slot5req bit is kept at 0.
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12.4 Interrupt request from UCB1510
MLNK BIT_CLK SDIN
Interrupt request Interrupt request is enabled
Fig 9. Setting the SDIN for interrupt request
12.4.1
When BIT_CLK is running The AClink is active and the interrupt request is transmitted by setting the interrupt bit of slot 12 in the AClink frame. If UCB1510 is configured as a primary codec, this is the case when MLNK is set to 0. If UCB1510 is configured as a secondary codec, this is the case whether MLNK is set to 0 or 1.
12.4.2
When BIT_CLK is stopped In order to request an interrupt, the UCB1510 will assert the SDIN pin, if MLNK is set to 1. BIT_CLK is not needed for this to happen. This applies when UCB1510 is used as a primary or secondary codec. If UCB1510 is configured as a primary codec, BIT_CLK is stopped as a result of MLNK being set to 1. If UCB1510 is configured as a secondary codec, BIT_CLK is stopped when the controller shuts down the primary codec. For UCB1510 to generate interrupt while BIT_CLK is stopped, MLNK has to be set to 1 before BIT_CLK is stopped. After BIT_CLK is stopped, SDIN will be brought to 0, unless an interrupt asserts it to 1. It is recommended that a level triggered interrupt detection is used in case the interrupt request is asserted at the same time BIT_CLK is stopped.
12.5 Wake-up request to the UCB1510
A cold reset will program the registers to their default value and will wake up the AClink. When the AClink is not active (no BIT_CLK present), a rising SYNC will cause a warm reset. If MLNK is set to 1, a rising RESET will also cause a warm reset. After a warm reset, MLNK will be reset to 0.
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13. General purpose I/O
The UCB1510 has 8 programmable digital input/output (I/O) pins. These pins can be independently programmed for polarity, value, direction and interrupt through the GPIO control registers.
14. Interrupt generation
The UCB1510 contains a programmable interrupt control block. The internal interrupt signal presents the 'OR' function of all interrupt status bits and can be used to give an interrupt to the system controller using the AClink interrupt protocol The interrupt controller is implemented asynchronously. This provides the possibility to generate interrupts when BIT_CLK is stopped, e.g. an interrupt can be generated in power down mode, when the state of one of the IO pins changes (e.g. ring detect).
15. Reset circuit and mode selection
The AC97 specification rev 2.1 describes a number of states and reset functions for a modem codec either in primary or secondary codec.
15.1 Resets
15.1.1 Pulling the PON pin LOW The PON pin acts as a hardware reset and is typically connected to a power detection circuit. 15.1.2 Activating the RESET pin Pulling the RESET pin low will start a cold or a warm reset sequence. If the circuit is active (MLNK = 0). A cold reset is started. The reset sequence will end after the rising edge of RESET. Only then will the AClink be available. Vendor test modes are inactive as soon as the reset sequence starts so that mode sensing is possible. If the MLNK bit is set when the RESET pin is pulled low, a warm reset is activated when RESET goes high again. 15.1.3 Activating the SYNC pin when AClink is inactive When the AClink is not active (no BIT_CLK present), a rising SYNC will cause a warm reset. 15.1.4 Writing reg 0x3C When written, the reg 0x3C will initiate a register reset. All registers are set to their default values.
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15.2 Vendor test modes
When starting a RESET pin induced cold reset, the AClink pins are sensed for Vendor Test mode selection. BIT_CLK does not need to be running at that moment
Table 29: Mode selection with AC pins SYNC 0 0 1 1 SDOUT 0 1 0 1 Mode Normal mode, the AClink is operating properly. ATE test mode. All AClink pins are set to input thus allowing board level JTAG testing. Vendor test mode. ATE test mode.
When the vendor test mode is activated, the vendor test register takes action. This mode is for test only and should not be used in normal operation. Exiting this mode requires a cold reset.
15.3 Primary/secondary codec selection
Secondary codec implementation is selected by wiring the A0 pin low. When A0 is low (A0 is 1), the XTAL_IN is used as A1 thus allowing `01' and `11' as secondary addresses. `10' is not possible. The ID register will then reflect the A1,A0. Details can be found in the description of register 0x3C. When the UCB1510 is a secondary codec, it derives its internal clock from BIT_CLK. BITCLK is therefore configured as input.
16. Limiting values
Table 30: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). [1]. Symbol VDD Vi Vo Ii(d) Io(d) Io Tstg
[1]
[2]
Parameter supply voltage DC input voltage DC output voltage diode input current diode output current continuous output current, digital outputs storage temperature
Conditions
Min -0.5 -0.5 - - - - -55
Max +4.0 VDD + 0.5 VDD + 0.5 10 10 4 +150
Unit V V V mA mA mA C
[2]
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the Absolute Maximum Rating section of this specification is not implied Parameters are valid over the ambient operating temperature unless otherwise specified. All voltages are with respect to VSSD, unless otherwise noted.
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17. Thermal characteristics
Table 31: Thermal characteristics Symbol Rth(j-a) Parameter thermal resistance from junction to ambient in free air Conditions Value 55 Unit K/W
18. Static characteristics
Table 32: Static characteristics VSSD = VSSA1 = 0 V; Tamb =25 C; all voltages referenced to VSSD; unless otherwise specified. Symbol VDDD VDDA1 IDDD IDDA1 IDDA2 VIL VIH VOL VOH fBIT_CLK Tamb
[1]
Parameter digital supply voltage analog supply voltage digital supply current digital supply current analog supply current LOW level input voltage HIGH level input voltage LOW level output voltage HIGH level output voltage serial interface clock frequency operating ambient temperature
Conditions
Min 3.0 3.0
[1]
Typ 3.3 3.3 19 t.b.d.
Max 3.6 3.6 - -
Unit V V mA mA
- -
full functionality Power down, only oscillator is on
[1]
-0.5 0.8VDDD IOL = 4 mA IOH = 4 mA - 0.8VDDD -20
- - - - 12.288 -
+0.2VDDD 0.5VDDD 0.4 - 70
V V V V MHz C
Indicative value measured during the initial characterization.
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19. Dynamic characteristics
Table 33: Dynamic characteristics VSSD = VSSA = 0 V; VDDD = VDDA = 3.3 V 10%; Tamb = 25 C; VI(ref) = 1.2 V; fBIT_CLK = 12.288 MHz; unless otherwise specified. Symbol Telecom fst Vi(rms) Parameter input [1] sample frequency input voltage (RMS value) differentially applied to TINN and TINP; ADC[3:2] = 1 (6 dB) in register 0x46 TINN/TINP 2 LSBs ignored, Bit 3 step - 330 8 370 - 410 kHz mV Conditions Min Typ Max Unit
Vi(bias) i Zi S/N THD LE(d)(ADC) RES PBRR
DC bias voltage input gain input gain step size input impedance signal-to-noise ratio total harmonic distortion ADC differential linearity error codec resolution pass-band ripple rejection
1.2 0 4 25 60 - - -
- 6 6 - 75 -75 - 14 - - - - - -
1.6 18 8 - - -60 2 - 1.2 1.2 - - 50 -
V dB dB k dB dB LSB bit dB dB dB dB LSB dB
fplt < fsig < fpht; no voice filter fvht < fsig < fpht; voice filter activated
[3], [6] [3], [6]
- - 30 50 - 20
SBRvti SBRsht Doffset Ssup
stop-band rejection digital offset sidetone suppression effectiveness
[2]
fsig < fvti; voice filter activated fsht < fsig no signal applied to input 600 line impedance; 1:1 transformer with 156 winding resistance
[3], [6] [3], [6]
Telecom output fst Vo(rms) Vo(bias) RES S/N THD PBRR SBR OBR(rms) Zo(load) Eoffset
sample frequency output voltage (RMS value) DC bias voltage codec resolution signal-to-noise ratio total harmonic distortion pass-band ripple rejection stop-band rejection out-of-band rejection (RMS value) load impedance offset error
[5] [4], [6]
- differentially measured between TOUTP and TOUTN TOUTP/TOUTN; telecom O/P path enabled 1.35 1.2 - 60 - - 50 - 600 - fsht < f < fst f > fst
[4], [6]
8 - - 14 75 -75 - - - - -
- 1.85 1.6 - - - 1.2 - 25 - 100
kHz V V bit dB dB dB dB mV mV
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Table 33: Dynamic characteristics...continued VSSD = VSSA = 0 V; VDDD = VDDA = 3.3 V 10%; Tamb = 25 C; VI(ref) = 1.2 V; fBIT_CLK = 12.288 MHz; unless otherwise specified. Symbol Vi(ref) tSTRTU Parameter reference voltage applied to VREFBYP start-up time of internal reference voltage circuit Operating frequency start-up time of internal reference voltage circuit CLK input frequency CLK duty factor RESET pulse width internal reset pulse width 0 - 5 Conditions Min 1.0 - Typ 1.2 - Max 1.4 1000 Unit V ns On-chip reference circuit
Xtal oscillator fxtal Zxtal 12.288 10 MHz k
AClink control register data transfer facclk Dacclk tW(NRESET) tW(rst)
[1] [2] [3] [4] [5] [6]
12.288 50 - 32 tCLK - - -
MHz % ns ns
Reset circuit
Additional test conditions: Fsample = 8 kHz; input signal 1 kHz, 300 mV (RMS); Line1_ADC_ON = 1; TEL_VOICE_ENA = 0, input gain +6 dB Additional test conditions: Fsampling 8 kHz; 0 dB output attenuation; 90% of digital full scale input voltage; 1200 load. See Figure 10. See Figure 11. Deviation of the analog output from 0, with 0 code input to telecom output path. All curves repeat around the sample frequency fsa or fst for telecom codec.
PBRR 0dB
f plt = 0.0016 x f st f pht = 0.42 x f st f sht = 0.6 x f st f vlt = 0.018 x f st f vht = 0.05 x f st
SBRvti
Voice filter enabled
SBRsht
Fplt
Fvlt
Fvht
Fpht
Fsht
Fig 10. Telecom input frequency response
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PBRR 0dB
f plt = 0.0016 x f st f pht = 0.42 x f st f sht = 0.6 x f st
SBR
Fplt
Frequency [Hz]
Fpht
Fsht
Fig 11. Telecom output frequency response
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20. Package outline
SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1
D
E
A X
c y HE vMA
Z 28 15
Q A2 pin 1 index A1 (A 3) Lp L 1 e bp 14 wM detail X A
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.0 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 10.4 10.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.1 0.7 8 0o
o
Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT341-1 REFERENCES IEC JEDEC MO-150AH EIAJ EUROPEAN PROJECTION
ISSUE DATE 93-09-08 95-02-04
Fig 12. SSOP28 package; SOT341-1.
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21. Soldering
21.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used.
21.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C.
21.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle
to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.
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Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
21.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
21.5 Package related soldering information
Table 34: Suitability of surface mount IC packages for wave and reflow soldering methods Package BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC [3], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO
[1]
Soldering method Wave not suitable not suitable [2] Reflow [1] suitable suitable suitable suitable suitable
suitable not not recommended [3] [4] recommended [5]
[2]
[3] [4] [5]
All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
22. Revision history
Table 35: Revision history Rev Date 01 991111 CPCN Description Converted to DBII format. The format of this specification has been redesigned to comply with Philips Semiconductors' new presentation and information standard.
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23. Data sheet status
Datasheet status Objective specification Preliminary specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Product specification
Production
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
24. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
25. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
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NOTES
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AC97 digital modem codec
Contents
1 2 3 4 5 6 6.1 6.2 7 8 8.1 8.2 9 10 11 11.1 11.2 11.2.1 11.2.2 11.2.3 11.2.4 11.2.5 11.2.6 11.2.7 11.2.8 11.2.9 11.2.10 11.2.11 11.2.12 11.2.13 11.2.14 11.2.15 11.3 11.3.1 11.3.2 11.3.3 12 12.1 12.2 12.2.1 12.2.2 12.3 12.4 12.4.1 12.4.2 12.5 13 14 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 5 Telecom codec . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Analog interface . . . . . . . . . . . . . . . . . . . . . . . . 7 On-chip reference circuit . . . . . . . . . . . . . . . . . 8 Power supply strategy. . . . . . . . . . . . . . . . . . . . 8 Register definition . . . . . . . . . . . . . . . . . . . . . . . 9 Supported registers . . . . . . . . . . . . . . . . . . . . . 9 Register detail. . . . . . . . . . . . . . . . . . . . . . . . . . 9 Extended Modem ID . . . . . . . . . . . . . . . . . . . . . 9 Extended Modem Status and Control. . . . . . . 10 Line 1 Sample Rate . . . . . . . . . . . . . . . . . . . . 10 Line 1 DAC/ADC Level . . . . . . . . . . . . . . . . . . 11 GPIO Pin Configuration . . . . . . . . . . . . . . . . . 11 GPIO Pin Polarity . . . . . . . . . . . . . . . . . . . . . . 11 GPIO Pin Sticky . . . . . . . . . . . . . . . . . . . . . . . 12 GPIO Wake-up Mask . . . . . . . . . . . . . . . . . . . 12 GPIO Pin Status . . . . . . . . . . . . . . . . . . . . . . . 12 Miscellaneous Modem AFE Status and Control 13 Vendor Specific Codec Control. . . . . . . . . . . . 14 Vendor Specific Mode Control . . . . . . . . . . . . 14 Vendor specific Test Control. . . . . . . . . . . . . . 14 Vendor ID1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Vendor ID2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Register reset modes . . . . . . . . . . . . . . . . . . . 15 Warm reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Cold reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Register reset . . . . . . . . . . . . . . . . . . . . . . . . . 15 AC97 interface . . . . . . . . . . . . . . . . . . . . . . . . . 16 Control register data transfer . . . . . . . . . . . . . 16 Codec addressing. . . . . . . . . . . . . . . . . . . . . . 18 Primary codec addressing . . . . . . . . . . . . . . . 18 Secondary codec addressing . . . . . . . . . . . . . 18 PCM sample transfer . . . . . . . . . . . . . . . . . . . 18 Interrupt request from UCB1510. . . . . . . . . . . 19 When BIT_CLK is running . . . . . . . . . . . . . . . 19 When BIT_CLK is stopped . . . . . . . . . . . . . . . 19 Wake-up request to the UCB1510 . . . . . . . . . 19 General purpose I/O. . . . . . . . . . . . . . . . . . . . . 20 Interrupt generation. . . . . . . . . . . . . . . . . . . . . 20 15 Reset circuit and mode selection . . . . . . . . . . 15.1 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.1 Pulling the PON pin LOW . . . . . . . . . . . . . . . . 15.1.2 Activating the RESET pin . . . . . . . . . . . . . . . . 15.1.3 Activating the SYNC pin when AClink is inactive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.4 Writing reg 0x3C . . . . . . . . . . . . . . . . . . . . . . . 15.2 Vendor test modes . . . . . . . . . . . . . . . . . . . . . 15.3 Primary/secondary codec selection . . . . . . . . 16 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 17 Thermal characteristics. . . . . . . . . . . . . . . . . . 18 Static characteristics . . . . . . . . . . . . . . . . . . . . 19 Dynamic characteristics . . . . . . . . . . . . . . . . . 20 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21 Soldering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.1 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.2 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 21.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 21.4 Manual soldering. . . . . . . . . . . . . . . . . . . . . . . 21.5 Package related soldering information . . . . . . 22 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 23 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 24 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 20 20 20 20 20 21 21 21 22 22 23 26 27 27 27 27 28 28 28 29 29 29
(c) Philips Electronics N.V. 2000.
Printed in the U.S.A.
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 4 February 2000 Document order number: 9397 750 06856

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