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HV9906
Initial Release
HV9906 FlexSwitch
Features
Drive one or hundreds of LEDs including White LEDs Programmable Current Source (mA to A) Programmable Voltage Source (Steps Up or Down) 2 Integrator Lock Loop Technology (IL ) o Built in Soft Start o Allows Discontinuous Feedback o Eliminates Compensation Components o Eliminates Output Averaging Filters o Inherent Dither to Reduce EMI Eliminates High Voltage Input Electrolytic Capacitor Smallest and Most Reliable Off-Line Solution Isolated or Non-Isolated Applications Can be Operated Directly from Rectified AC Mains 10V to 400V Input Range Internal Regulator <1.5mA Operating Supply Current Programmable Feed Forward Regulation Programmable Feedback Sense Threshold (mV to V) Integrating Differential Sense Feedback Seamlessly Change from AC to Battery Operation
TM
(Simple Off-Line/PFC & >9V DC/DC Switcher) General Description
The Supertex HV9906 allows the development of the smallest possible, most reliable, offline and wide DC/DC conversion range converters for driving LEDs and other applications. The HV9906 combines internally all the components required to operate directly from the rectified AC line with a feedback mechanism that eliminates filters & compensation components, and which can close the loop with feedback from a discontinuous waveform (eg. LED current). The HV9906 is capable of driving multiconverters, which have been shown to provide the best performance to component count trade off for wide conversion range applications like offline converters. Applicable multiconverters include bucking & boosting topologies, in isolated & non-isolated configurations, as well as power factor correcting topologies from <1W up to 150W. Proper choice of external components will allow the programming of currents from <1mA to several amps and will allow stepping up or stepping down from the input without the need to change components. For example, the same HV9906 converter nominally regulating to 60VDC output may operate from 12VDC, or from rectified AC input to 265VRMS. The HV9906 utilizes a programmable inversely proportional fast feed forward algorithm to calculate output on time and a novel 2 Integrating Lock Loop (IL ) feedback with programmable threshold differential sensing. The sensed feedback may be positive or negative with respect to ground and the signal may be discontinuous. In some topologies this control method permits the elimination of the bulky input filter capacitor (a small high voltage ceramic or film capacitor is required to maintain a high frequency path). This algorithm when used with certain multiconverters such as the flyback-buck, with a fixed load, results in near constant frequency with only a small dither which helps meet FCC requirements.
Applications
LED driver Power Factor Correction Constant Current or Voltage Source Battery Charger / PWM Housekeeping Supplies Traffic Lights / Street Lights Back Lighting of Flat Panel Displays Advertising Signs Automotive
Typical Application Circuit
1N4007 D1 D2 12VDC to 400VDC or 65VAC to 280VAC D4 D3 C1 0.047uF 400V NPN Bipolar Transistor Array or Matched 2N2222 D5 MURS160 D6 MURS160 L2 15uH Q1 Q2 Q3 Negative Voltage C3 0.033uF L1 56uH D7 MURS160 C4 Optional Q25
+
LED-1 Row 1 20mA LED-1 Row 2 20mA LED-9 Row 2 LED-10 Row 2 LED-1 Row 3 20mA LED-9 Row 3 LED-10 Row 3 LED-1 Row 25 20mA LED-9 Row 25 LED-10 Row 25
R1 8M Von R2 100k C2 1uF to 6.8uF
U1 GATE NS HV9906 PS Vdd AGND PGND +Vin
M1 IRFBC30AF
R3 900k R4 300k R5 100
LED-9 Row 1
1 07/23/02 Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com
HV9906 Absolute Maximum Ratings*
-0.3V to +450V +VIN Input Voltage -0.3V to +15V VDD -0.3 to +10V VON Pulse Width Control Voltage PS & NS Pin Feedback Voltage -0.3V to +10V Operating Ambient Temperature Range -40C to +85C Operating Junction Temperature Range -40C to +150C Storage Temperature Range -65C to +150C Thermal Resistance Junction to Ambient, SOIC 159C/W Thermal Resistance Junction to Case, SOIC 45C/W Thermal Resistance Junction to Ambient, Plastic DIP 110C/W Thermal Resistance Junction to Case, Plastic DIP 35C/W
*All voltages referenced to AGND and PGND connected together.
Ordering Information
8 Pin Plastic DIP HV9906P Package Options 8 Pin SOIC HV9906LG Dice HV9906X
Electrical Characteristics (Unless otherwise noted TA = 25C)
Symbol Parameter Min Typ Max Units TA Conditions
Input Regulator/Vdd Supply
+VIN +IIN VDD(REG) VUVLO VHYST Input Voltage Input Current Internal Regulator Output Voltage Under Voltage Lockout Threshold Under Voltage Lockout Hysteresis 10 8.0 0.50 8.5 400 1.5 11 V mA V V V * * * Decaying VDD Typical under UVLO Gate pin open and operating at FMAX
MOSFET Gate Drive Output
tR tF Rise Time Fall Time 75 75 nSec nSec CGATE = 750pF CGATE = 750pF
PWM
P(VON) P(VON) PMAX fMIN fMAX Output Pulse Width at VON Output Pulse Width at VON Maximum Output Pulse Width Minimum Output Frequency Maximum Output Frequency 10 250 2 215 3.35 17.8 13.5 17 450 300 nSec uSec uSec KHz KHz VON = 5.0V VON = 0.2V VON = 0V
Current Sense
VPS VNS Positive Sense Pin Voltage Negative Sense Pin Voltage 0.9 0.9 1 1 1.1 1.1 V V * * Note: VPS and VNS are matched Note: VPS and VNS are matched
Pulse Width Control Feed Forward Voltage
VON Effective Pulse Width Control Voltage Range 0.2 6.0 V *
The "*" denotes specifications that apply over the full temperature range (-40C to +85C)
2 07/23/02 Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com
HV9906 Pinout Pin Description
+VIN - This pin is the input to the internal linear regulator. VON -The voltage applied to this pin by a resistor voltage divider from +VIN controls the on time (pulse width) of the gate output. VDD - This pin is the output of the internal linear regulator and the supply pin for the internal circuits. It must be bypassed with a low ESR capacitor to provide a low impedance path for the gate drive and be capable of storing sufficient energy so that the voltage does not decay below the UVLO threshold during the time when the input voltage is below the minimum required by the regulator. AGND - This pin is the common connection for analog circuits. GATE - This pin is the output for driving the gate of an external Nchannel MOSFET. PGND - This is the common connection for the GATE drive circuit. NS - This pin is the negative terminal of the differential sense feedback circuit. PS - This pin is the positive terminal of the differential sense feedback circuit. __________________________________________________________________________________________________________________
+Vin
1
8
GATE
Von
2 HV9906
7
PGND
Vdd
3
6
NS
AGND
4
5
PS
Functional Block Diagram
+Vin
High Voltage Regulator UVLO and POR
Bandgap Reference
1V Vref Vdd
Von
Vdd
Vdd
Vref R _ Q Q S VCO PGND Driver GATE
C
C
AGND Reset Pulse Delay Sample Pulse
Delay
Vdd
1V
1V NS PS
3 07/23/02 Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com
HV9906 Functional Description
The HV9906 consists of the following functional blocks: High Voltage Regulator Bandgap Reference Under Voltage Lockout and Power On Reset Voltage Controlled Oscillator Feed Forward On Time Control Differential Sense Circuit and Programmable Reference Integrator Sample and Hold VCO Control Gate Driver Soft Start The following sections provide a detailed explanation of each of these blocks. High Voltage Regulator All internal circuits operate from a nominal 10V VDD supply provided by an onboard linear regulator capable of accepting input voltages up to 400V. This regulator blocks reverse current flow from VDD to +VIN, such as in the case when the input voltage is a full wave rectified sine wave. Therefore, if a sufficiently large bypass capacitor (>1F) is connected to VDD, the operation of the circuit can be maintained during the times when the full wave rectified input voltage is less than the regulated output voltage. High operating frequency and high input voltage applications will result in increased power dissipation in the regulator. For these applications efficiency may be improved by bootstrapping the VDD pin if a non-isolated +10V output is available. Supertex's high voltage technology allows a very low current regulator, rather than a shunt, to power the IC. This makes it possible to continuously operate the IC from the AC line, within thermal limits & without bootstrapping, in certain applications. Bandgap Reference As the regulator turns on and the VDD voltage rises, a bandgap reference is activated to establish the regulation point of the regulator and provide the required references for the internal circuits. The references are strictly internal and not available at any pin of the device. Under Voltage Lockout and Power On Reset On initial power application the high input voltage (up to 400V) linear regulator charges the capacitor connected to VDD and seeks to provide a stable supply for the internal circuitry. Under voltage lockout (UVLO) holds the voltage controlled oscillator (VCO) disabled until the VDD supply rises above a nominal 8.5V and power on reset (POR) clamps the capacitors in the sample and hold and integrator circuits low for a short time thereafter, thus setting the VCO to its lowest frequency state. The UVLO has a 0.5V hysteresis to prevent false triggering due to ripple on VDD. Voltage Controlled Oscillator The period of the voltage controlled oscillator (VCO) is determined by the output of the sample and hold circuit while the feed forward control from the VON pin provides fast direct control of the oscillator output on time. For unusual operating circumstance the VCO may be driven to its maximum frequency and the on time may exceed the period of the oscillator. This will cause cycle skipping or an effective reduction in output frequency by an integer factor.
To Least Negative Sense Node Relative to +1 Volt
Feed Forward On Time Control The output signal to the gate driver is controlled by a latch that is set by the output of the VCO and reset by the feed forward on time control, thus the voltage applied to the VON pin provides direct and continuous control of the gate drive on time. The on time is inversely proportional to the applied voltage and there is an internally set limit to the maximum on time (17.8S) so that 0V will not result in an infinite on time. Refer to "Programming On Time" in the Design Information section. To operate in discontinuous conduction mode with constant energy transfer per cycle a resistor divider from the input voltage is connected to the VON pin, thereby providing fast feed forward input regulation control. This control loop can easily track a rectified sine wave of input voltage at 50Hz, 60Hz or 400Hz provided that the capacitor connected at VDD can store sufficient energy to prevent decay below the UVLO threshold during the time when the rectified sine wave input voltage at +VIN is below 10V. For a 100V 50Hz rectified sine wave a 3.3F capacitor connected to VDD is sufficient to guarantee stable operation. For power factor correction applications an input voltage peak detector or a low pass filter can be used to drive the VON pin. This will provide an essentially constant on time control voltage resulting in an energy transfer per oscillator cycle directly proportional to the input voltage. Differential Sense Circuit and Programmable Reference The following simplified equivalent circuit is provided to clarify the operation and programming of this circuit.
Vdd
+1V
20pF
+1V
PS R PS To Sample and Hold Comparators RNS
NS
To Most Negative Sense Node Relative to +1Volt
This differential sense circuit is typically used to monitor the output voltage or current of a power converter. The circuit operates by sourcing current (typically 5A) from both the PS and NS pins which are regulated at a nominal +1V and the control loop seeks to maintain a sense node voltage (voltage across a current sense resistor or the voltage across a resistor divider) that will make the NS and PS currents equal. Regulation is established when there is zero current difference in the PS and NS pins. This differential common mode sense method reduces noise sensitivity and enables the user to define the magnitude of the sensed voltage (i.e. +100mV for high efficiency or -2.5V to escape the noise floor) and thus the effective reference, provided the sensed nodes are at less than +1V with respect to ground.
4 07/23/02 Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com
HV9906 Functional Description - continued
The voltage difference between the sensed nodes will require the selection of resistor values in series with the NS and PS pins that will result in current balance. While balance can be achieved even if neither sensed node is at ground potential, care must be taken to assure that the dynamic voltage excursions of the sensed node within the design operating range (i.e. 50KHz to 250KHz) of the particular application does not result in common mode current swings in the PS and NS pins that would result in saturation of the integrators. Saturation at frequencies below the minimum operating frequency of the application is permitted* since by design the circuit will soft start from its lowest frequency. To regulate on a sense node voltage of +0.5V with respect to ground connect a 200k resistor from the NS pin to the ground end of the sense element and a 100k resistor from the PS pin to the +0.5V end of the sense element. Since the voltage drop on the 200k resistor connected to the NS pin is 1V, a reference current of 5A is established. To achieve current balance in the PS pin the sensed node must rise to +0.5V. For regulating a sense node voltage of -1V with respect to ground connect a 200k resistor from the PS pin to the ground end of the sense element and a 400k resistor from the NS pin to the -1V end of the sense element. Since the voltage drop on the 200k resistor connected to the PS pin is 1V, a reference current of 5A is established. To achieve current balance in the NS pin the sensed node must fall to -1V. For calculating the required resistor values refer to "Programming the Sense Inputs" in the Design Information section. Integrator The differential output current of the differential sense circuit is fed to two matched internal 20pF capacitors that make up the differential integrator circuit. The tolerances of these integrated capacitors are typically 5%, however, since they are matched, their absolute values only affect the peak voltage of the integrators. Operating at the lowest frequency results in the highest peak voltage on the integrators, which will saturate if the peak voltage on the capacitors exceeds 6V, resulting in a loss of regulation. This must be taken into consideration when deciding on the value of the sense currents in the PS and NS pins. The signals at the sensed nodes may be discontinuous (i.e. controlling the average output current into LEDs) since the signals are cycle-averaged by the differential integrator. The differential output of the integrator is fed to the sample and hold comparators. *The circuit soft starts from the lowest frequency, therefore it is very likely that the integrators will saturate during startup. By design the VCO frequency will be incremented in the event of a saturated condition, thereby guaranteeing that the circuit will start. Sample and Hold VCO Control The cycle-averaged outputs of the differential integrator are compared by the window comparator of the sample and hold circuit. If the differential integrator outputs are unequal the sample and hold circuit increments or decrements the VCO control voltage by a fixed small step resulting in a shorter or longer subsequent VCO cycle and thus an increased or decreased frequency. When the cycle-averaged signals from the differential integrator are nearly equal (within the hysteresis band of the comparators) the sample and hold function is halted and the off time is unchanged. Since the frequency is incremented or decremented in small fixed steps at the end of each cycle the rate of frequency increase or decrease is a function of the frequency and thus the oscillator frequency will change exponentially. In this manner the Integrator Lock Loop (IL ) feedback controls the oscillator frequency based on a cycle-averaged sensed value to maintain output regulation. For certain off-line topologies, the result is near fixed frequency operation for a fixed load with a dither of a few KHz which helps in meeting FCC conducted emission requirements. Gate Driver The gate driver buffers the output of the VCO and provides sufficient gate drive power to achieve rise and fall times below 75nS into a 750pF equivalent MOSFET gate. The under voltage lockout (UVLO) assures that sufficient voltage is available to drive the gate of standard or logic level threshold MOSFETs. Soft Start On initial power application the UVLO and POR resets the output latch and sets the VCO to its lowest frequency state, which represents minimum power transfer per VCO cycle. Thereafter, the differential sense feedback loop increments the frequency in small steps, increasing the power transfer rate until output regulation is achieved, thereby providing the required soft start function.
2
5 07/23/02 Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com
HV9906 Design Information
Programming On Time The instantaneous voltage applied to the VON pin determines the gate drive output on time for the VCO cycle. The on time is inversely proportional to the voltage applied to the VON pin and may be calculated using the following equation:
Where INS = IPS = average current in the NS and PS pins at stable output regulation, VNSENSE is the most negative sensed node voltage with respect to +1V and VPSENSE is the least negative sensed node voltage with respect +1V. VNSENSE and VPSENSE must be less than +1V and VNSENSE is always more negative than VPSENSE. Example 1. For a converter operating at a minimum frequency of 50KHz and sensing a -1V feedback node voltage with respect to ground, the resistors connected in series with the PS and NS pins will be determined as follows. IPS(MAX ) = 1.14 x 10 -10 x 5 x 10 4 = 5.7A To provide a margin of safety let IPS(MAX) = 5A. Since in this configuration the resistor in series with the PS pin is connected to ground, the sense node voltage VPSENSE(MIN) = 0V. RPS = 1V - VPSENSE(MIN) IPS(MAX ) = 1 - (0 ) 5 x 10 -6 = 200k
0.65 -6 P(VON ) 0.085 + x 10 VON Where the effective control range of VON is limited between 0.2V and 6V. For VON = 0V P(VON) defaults to a nominal maximum of 17.8S. Depending on the converter topology and worst case operating conditions the minimum on time and thus the duty cycle may be programmed.
Programming the Sense Inputs
The PS and NS sense pins are regulated at +1V and each needs to be programmed to source the same current at the converter output regulation set point. In order to calculate the values of RNS and RPS, the maximum sense current, which will avoid integrator saturation, must be determined. Since by design the circuit will inherently soft start from its lowest frequency, the designer only needs to establish the lowest operating frequency (fMIN) for the design, which corresponds to minimum converter output power under closed loop control. Once this frequency is established the maximum PS pin sense current IPS(MAX), which occurs during start up when VPSENSE = VNSENSE, can be calculated using the following equation.
IPS(MAX ) = CMIN x VSAT x fMIN Where CMIN is the minimum value of the integrator capacitors, VSAT is the minimum saturation level of the integrators and fMIN is the minimum operating frequency of the converter. Inserting these values the above equation can be simplified.
IPS = INS =
1V - VPSENSE 1- 0 = = 5A RPS 200k
RNS = Example 2.
1V - VNSENSE 1 - ( -1) = 400k = INS 5 x 10 -6
For a converter operating at a minimum frequency of 100KHz and sensing a +0.5V feedback node voltage with respect to ground, the resistors connected in series with the PS and NS pins will be determined as follows. IPS(MAX ) = 1.14 x 10 -10 x 1x 10 5 = 11.4A To provide a margin of safety let IPS(MAX) = 10A. In this configuration the most negative value of VPSENSE(MIN) occurs during startup at which time it is 0V. RPS = 1V - VPSENSE(MIN) IPS(MAX ) = 1- 0 10 x 10 -6 = 100k
IPS(MAX ) = (0.95) x (20 x 10 -12 ) x 6 x fMIN IPS(MAX ) = 1.14 x 10 -10 x fMIN For the general case, where at regulation neither sensed node might be at ground potential, the following equation may be used to calculate the required RPS resistor value where VPSENSE(MIN) is the most negative value that the node will see during starting or normal operation. RPS = 1V - VPSENSE(MIN) IPS(MAX )
IPS = INS =
1V - VPSENSE 1 - ( +0.5) = = 5A RPS 100k
RNS =
Protection
1V - VNSENSE 1- 0 = 200k = INS 5 x 10 -6
Once the value of RPS has been determined the IPS and INS sense currents at the regulation point can be calculated and the value of RNS can be determined as follows.
IPS = INS = 1V - VPSENSE RPS
RNS =
1V - VNSENSE INS
The HV9906 used as a current source is inherently protected in the case of an output short. Over voltage protection is easily accomplished, in the flyback-buck application for example, with no more than two diodes. Simple protection for voltage mode applications, and other topologies is easy to accomplish. Call for more information.
6 07/23/02 Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com
HV9906 Design Information - continued
Managing Power Dissipation
The maximum IDD current required is the sum of the chip operating current plus the current required to drive the gate of the external MOSFET at the maximum operating frequency of the particular application. Depending on the available data on the MOSFET the current can be calculated by one of the following methods. IGATE = f x Q GATE or IGATE = f x C GATE x VGATE Where f is the maximum operating frequency for the application, QGATE is the total gate charge, CGATE is the effective gate capacitance and VGATE is the maximum gate drive voltage, which is approximately equal to VDD. The input regulator supplies all the current and the worst-case total regulator current may be calculated as follows. IIN = 1.5 x 10 -3 + IGATE = 1.5 x 10 -3 + f x Q GATE or IIN = 1.5 x 10 -3 + IGATE = 1.5 x 10 -3 + f x CGATE x VGATE As an example for a particular application where CGATE = 750pF and the maximum operating frequency is f = 200KHz the regulator input current IIN = 1.5 x 10 -3 + 200 x 10 3 x 750 x 10 -12 x 10 = 3mA If the application is operating in an open-air environment with a known maximum ambient temperature, then the maximum allowable input voltage may be calculated using the following equation. VIN(max) = Tj - Ta R ja x IIN
In the event that this maximum allowable input voltage is less than what is required by the application, then the following means may be considered to reduce the dissipation in the regulator. 1. Bootstrapping VDD from an output of the converter 2. If the input is DC then a resistor can be added in series with VIN 3. If the input is AC then a depletion MOSFET may be added in series with VIN 4. Encapsulating the circuit with a high thermal conductivity material 5. Boostrapping VDD from an auxiliary bifilar inductor winding or from an auxiliary transformer winding. Bootstrapping VDD Forcing VDD to a voltage greater than the regulation set point voltage of the internal regulator (i.e. 13V) will force the regulator to turn off and all the required operating current will be provided by the forcing source of power. If this power source is derived from the output of the converter, possibly by means of a secondary winding on one of the inductors or an additional winding on a transformer, then the internal regulator will provide the required current during startup only. Care must be taken to assure that the absolute maximum voltage rating of the VDD pin is not exceeded. After initial startup, bootstrapping will reduce the power dissipated, even at the absolute maximum VDD voltage, to an essentially negligible level (VDD(max) x IIN =15V x 3mA = 45mW). Operating from a DC input For DC applications there is usually some minimum operating voltage. A resistor may be added in series with +VIN which can reduce the effective input voltage to +VIN(min) , thereby transferring some of the power dissipation to the series resistor. Using the input current of 3mA previously calculated and assuming an operating input voltage range (VS) of 100VDC to 250VDC for the application, the maximum value of the series resistor can be calculated as follows.
Where Tj is the maximum operating junction temperature, Ta is the maximum ambient temperature, Rja is the thermal resistance for the particular package from junction to ambient and IIN is the required input current. Using the IIN calculated in the previous example in a 50C maximum ambient and a plastic DIP package the maximum allowable input voltage is as follows.
R series =
VS(min) - VIN(min) IIN
=
100 - 10 3 x 10 -3
= 30k
The maximum power dissipation in the resistor will be
2 WR = R series x IIN = 30 x 10 3 x (3 x 10 -3 )2 = 0.27 W
VIN(max) =
150 - 50 110 x 3 x 10 -3
= 303 V DC or RMS
and the maximum power dissipation in the HV9906 will be WIC = VIN(max) x IIN - WR = 250 x 3 x 10 -3 - 0.27 = 0.48 W which for an SOIC packaged device will result in junction to ambient temperature difference of 159C/W x 0.48W = 76.32C, thereby allowing operation up to an ambient temperature of 73.68C for the absolute maximum junction temperature of 150C.
7 07/23/02 Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com
HV9906 Design Information - continued
Operating from a full wave rectified AC input For these applications there is no minimum input voltage, thus adding a fixed value series resistor is not possible. However, a dynamic resistor consisting of a depletion MOSFET may be added as depicted in the following diagram. Using High Thermal Conductivity Encapsulation For an encapsulated application the required thermal resistance of the encapsulating material can be calculated using the following equation. R ca =
DN3145N8 Vs HV9906 1 2 3 4 +Vin Von Vdd AGND GATE PGND NS PS 8 7 6 5
Tj - Ta - (R jc x VIN(max) x IIN ) VIN(max) x IIN
Rca is the required thermal resistance of the encapsulating material. Tj is the maximum junction temperature. Ta is the maximum ambient temperature. Rjc is the junction to case thermal resistance of the package.
This method limits the +VIN voltage to VDD + VGS(OFF) of the depletion MOSFET for all input voltages and in fact raises the maximum allowable peak input voltage to the breakdown voltage rating of the depletion MOSFET. The worst-case power dissipation in the HV9906 is now given by the equation Power Dissipation HV9906 = ( VDD + VGS( OFF )max ) x IIN and the dissipation in the depletion MOSFET is given by the equation Power Dissipation in MOSFET ( VS - VDD - VGS( OFF ) ) x IIN Which for the previously calculated input current of 3mA, 265VRMS input voltage and using the DN3145N8 depletion MOSFET yields the following results. Power Dissipation HV9906 = (11 + 3.5) x 3 x 10 -3 = 43.5mW Power Dissipation in MOSFET (265 - 10 - 1.5) x 3 x 10 -3
VIN(max) is the maximum DC or RMS input voltage. IIN is the input current required at the highest operating frequency. As an example, consider an application where the input current is 3mA as calculated earlier, operating with a maximum input voltage of 265VRMS in an 85C ambient and an SOIC packaged device will be used. The thermal resistance of the encapsulating material can then be calculated as follows. R ca = 150 - 85 - ( 45 x 265 x 3 x 10 -3 ) 265 x 3 x 10 -3 = 36.76C / W
High Thermal Conductivity Encapsulant
R ca R jc
Dice
Printed Circuit Board
Power Dissipation in MOSFET 0.76W
8 07/23/02 Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com
HV9906 Application Information
Universal Input Non-Isolated Constant 10mA Average Current LED Lamp Power Supply
1N4007 D1 D2 12VDC to 400VDC or 65VAC to 280VAC D4 D3 C1 0.1uF 400V
D5 MURS120T3
D6 MURS120T3
L2 220uH
C3 0.01uF L1 1mH
D7 MURS120T3
C4 Optional
+
10mA 1 to 8 LEDs
R1 8M
U1 +Vin GATE Von NS HV9906 Vdd PS AGND PGND
M1 VN2460N8
R3 700k R4 200k R5 250
R2 100k
C2 1uF to 6.8uF
This circuit provides a constant average current output, which may be used to power LED lamps. The circuit maintains a constant average current and the value of C4 capacitor controls the peak-topeak ripple, which decreases with increasing capacitor value.
If current ripple is permissible then C4 may be omitted.
Universal Input Non-Isolated Constant 0.5A Average Current LED Lamp Power Supply
1N4007 D1 D2 12VDC to 400VDC or 65VAC to 280VAC D4 D3 C1 0.047uF 400V NPN Bipolar Transistor Array or Matched 2N2222 D5 MURS160 D6 MURS160 L2 15uH Q1 Q2 Q3 Negative Voltage C3 0.033uF L1 56uH D7 MURS160 C4 Optional Q25
+
LED-1 Row 1 20mA LED-1 Row 2 20mA LED-9 Row 2 LED-10 Row 2 LED-1 Row 3 20mA LED-9 Row 3 LED-10 Row 3 LED-1 Row 25 20mA LED-9 Row 25 LED-10 Row 25
R1 8M Von
U1 +Vin GATE NS HV9906 Vdd PS AGND PGND
M1 IRFBC30AF
R3 900k R4 300k R5 100
LED-9 Row 1
R2 100k
C2 1uF to 6.8uF
This circuit provides 0.5A constant average current output to power 249 LEDs , each operating at 20mA to form a large LED lamp or array. The circuit maintains a constant average current and the value of C4 capacitor controls the peak-to-peak ripple, which decreases with increasing capacitor value.
If current ripple is permissible then C4 may be omitted.
9 07/23/02 Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com
HV9906 Application Information - continued
Power Factor Corrected Average Current LED Lamp Power Supply
D1 80VAC to 135VAC D4 D3 D2 D6 D7 L2 Negative Voltage LED-1 Row 1 LED-2 Row 1 M1 LED-1 Row 2 LED-2 Row 2 LED-1 Row 3 LED-2 Row 3
C9
D8
C1 L1 R10 R1 Von HV9906 Vdd R2 C2 R3 C4 AGND PS PGND R5 R4 C7 C8 U1 +Vin D5 C3 GATE NS R6 C5 R9 C6 R7 R8 Q1
LED-5 Row 1
LED-5 Row 2
LED-5 Row 3
This power factor corrected circuit provides a constant average current output to power LED lamps.
It is intended to meet the following specifications: Input Voltage 80VAC to 135VAC LED String Forward Voltage 20V Power Factor >0.95 THD <15% P 10W
12V (6 cell) Lead-Acid Battery Charger
1N4007 D1 D2 12VDC to 400VDC or 65VAC to 280VAC D4 D3
D5 MURS120T3
D6 MURS120T3
L2 12V Lead-Acid Battery
C3 L1
C1 0.1uF 400V
D7 MURS120T3
+
R3 225k R1 8M U1 +Vin GATE Von NS HV9906 Vdd PS AGND PGND M1
R5 13.3k R6 500 R7 0.5
R1 100k
C2 10uF
R4 150k
This floating battery charger circuit will charge a 6 cell 12V leadacid battery to a float voltage of 13.8V and provides a 1A charging current limit for a severely discharged or shorted battery.
When the discharged battery terminal voltage is at 12V, the charging current is 130mA. The charging current decreases as the battery charges and the terminal voltage rises. When the maximum float voltage of 13.8V is reached the current into the battery will be essentially zero.
10 07/23/02 Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com

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