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W83971D
AC'97 AUDIO CODEC
W83971D Data Sheet Revision History
Pages 1 2 3 4 5 6 7 8 9 10 n.a. n.a. All Dates 09/30/98 01/04/99 7/16/1999 Version 0.5 0.51 0.52 0.55 Version on Web n.a. n.a. n.a. First published. Correct performance spec and app. circuit. Add Layout guideline and reference schematic . Main Contents
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
Preliminary W83971D AC'97 AUDIO CODEC
Table of Contents
1. GENERAL DESCRIPTION ......................................................................................................................... 4 2. FEATURE LIST........................................................................................................................................... 4 3. FUNCTIONAL BLOCK DIAGRAM.............................................................................................................. 5 4. PINOUT AND PACKAGE ........................................................................................................................... 6 5. PIN DESCRIPTION..................................................................................................................................... 8 5.1 Digital I/O ............................................................................................................................................ 8 5.2 Analog I/O ........................................................................................................................................... 8 5.3 Filter and Reference Pins.................................................................................................................... 9 5.4 Power Supplies ................................................................................................................................... 9 6. REGISTER DESCRIPTION ...................................................................................................................... 10 6.1 Register Map..................................................................................................................................... 10 6.2 Reset Register (Index 00h) ............................................................................................................... 11 6.3 Stereo Output Control Register (Index 02h) ...................................................................................... 11
6.3.1 Mute Stereo Output Mute Control..............................................................................................11 6.3.2 ML[5:0] Master Output (Left Channel) Volume Control ..............................................................11 6.3.3 MR[5:0] Master Output (Right Channel) Volume Control ...........................................................11 6.3.4 Output Volume Control Map......................................................................................................12
6.4 Mono Output Control Register (Index 06h)........................................................................................ 13
6.4.1 Mute Mono Output Mute Control ...............................................................................................13 6.4.2 MM[5:0] Mono Output Volume Control ......................................................................................13 6.4.3 Stereo and Mono Output Attenuation ........................................................................................13
6.5 PC_BEEP Input Volume Control Register (Index 0Ah) ..................................................................... 14
6.5.1 Mute PC Beep Input Mute Control .............................................................................................14 6.5.2 PV[3:0] PC Beep Input Volume Control .....................................................................................14
6.6 Phone Input Volume Control Register (Index 0Ch)............................................................................ 14
6.6.1 Mute Phone Input Mute Control.................................................................................................14 6.6.2 GN[4:0] PC Phone Input Volume Control ..................................................................................14 6.6.3 Programmable Input and Output Gain Levels............................................................................15
6.7 Mic Input Volume Control Register (Index 0Eh) ................................................................................ 16
6.7.1 Mute Mic Input Mute Control .....................................................................................................16 6.7.2 20dB Mic Boost Control ............................................................................................................16
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Preliminary W83971D
6.7.3 GN[4:0] Mic Input Volume Control.............................................................................................16
6.8 Line Input Control Register (Index 10h) ............................................................................................. 16
6.8.1 Mute Line Input Mute Control ....................................................................................................16 6.8.2 GL[4:0] Left Channel Gain Control ............................................................................................16 6.8.3 GR[4:0] Right Channel Gain Control .........................................................................................17
6.9 CD Input Control Register (Index 12h) .............................................................................................. 17
6.9.1 Mute Line Input Mute Control ....................................................................................................17 6.9.2 GL[4:0] Left Channel Gain Control ............................................................................................17 6.9.3 GR[4:0] Right Channel Gain Control .........................................................................................17
6.10 Video Input Control Register (Index 14h) ........................................................................................ 17
6.10.1 Mute Line Input Mute Control ..................................................................................................17 6.10.2 6.10.2 GL[4:0] Left Channel Gain Control ............................................................................18 6.10.3 GR[4:0] Right Channel Gain Control .......................................................................................18
6.11 Auxiliary Input Control Register (Index 16h)..................................................................................... 18
6.11.1 Mute Line Input Mute Control ..................................................................................................18 6.11.2 GL[4:0] Left Channel Gain Control ..........................................................................................18 6.11.3 GR[4:0] Right Channel Gain Control .......................................................................................18
6.12 PCM Output Control Register (Index 18h)....................................................................................... 19
6.12.1 Mute Line Input Mute Control ..................................................................................................19 6.12.2 GL[4:0] Left Channel Gain Control ..........................................................................................19 6.12.3 GR[4:0] Right Channel Gain Control .......................................................................................19
6.13 Record Select Register (Index 1Ah)................................................................................................ 19
6.13.1 Record Source Select(Left Channel) Record Source Select(Right Channel) ................19
6.14 Record Gain Control Register (Index 1Ch)...................................................................................... 20
6.14.1 Mute Record Mute Control ......................................................................................................20 6.14.2 GL[3:0] Record Gain Control (Left Channel)............................................................................20 6.14.3 GR[3:0] Record Gain Control (Right Channel) .........................................................................20
6.15 General Purpose Register (Index 20h)............................................................................................ 20
6.15.1 3D Stereo Enhancement .........................................................................................................20 6.15.2 MIX Mono Output Mode ..........................................................................................................20 6.15.3 MS Microphone Select ............................................................................................................20 6.15.4 LPBK Loopback Mode.............................................................................................................20
6.16 3D Control Register (Index 22h)...................................................................................................... 21
6.16.1 Depth of 3D Control Level .......................................................................................................21
6.17 Power Down and Status Register (Index 26h) ................................................................................ 21
6.17.1 PR[5:0] Power Down Mode Bits ..............................................................................................21 6.17.2 Status (READ Only) bits .........................................................................................................21
6.18 Vendor Identification Registers (Index 7Ch, 7Eh)............................................................................ 22
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Preliminary W83971D
7. MULTIPLE CODEC EXTENSION ............................................................................................................ 23 7.1 Multiple Codec Mode Select ............................................................................................................. 23 7.2 Multiple Codec Example ................................................................................................................... 24 8. ELECTRICAL SPECIFICATIONS............................................................................................................. 25 8.1 DC Characteristics ............................................................................................................................ 25 8.2 AC Timing Characteristics................................................................................................................. 25 8.3 BIT_CLK / SYNC .............................................................................................................................. 26 8.4 Setup and Hold ................................................................................................................................. 27 8.5 Rise and Fall ..................................................................................................................................... 28 8.6 AC_Link Low Power Mode ............................................................................................................... 29 8.7 ATE/ Vendor Test Mode ................................................................................................................... 30 9. PERFORMANCE SPECIFICATIONS....................................................................................................... 31 9.1 Analog Characteristics ...................................................................................................................... 31 9.2 Miscellaneous Analog Performance Characteristics: ........................................................................ 33 9.3 Power Consumption:......................................................................................................................... 34 10. POWER MANAGEMENT ....................................................................................................................... 34 10.1 Power Down / Power Up ................................................................................................................ 35 11. TEST MODE OPERATION..................................................................................................................... 37 11.1 ATE Test Mode:.............................................................................................................................. 37 11.2 Vendor Test Mode: ......................................................................................................................... 37 12. TYPICAL CONNECTION DIAGRAM ...................................................................................................... 38 13. HOW TO READ THE TOP MARKING ................................................................................................... 39 14. PACKAGE DIMENSIONS....................................................................................................................... 40 15. APPENDIX A: TEST REPORT ............................................................................................................... 41 16. APPENDIX B: LAYOUT GUIDE ............................................................................................................. 54 16. APPENDIX B: LAYOUT GUIDE ............................................................................................................. 55
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Publication Release Date: July 1999 Revision A1
Preliminary W83971D
1. GENERAL DESCRIPTION
The Winbond W83971D is a high performance codec compliant with Audio Codec97 Rev1.03 requirements, in addition to 3D stereo enhancement. The definition of AC Link serial interface allows the W83971D to be used with DC97 controller as well as various digital controller which have AC Link interface. Packaged in a small 48-pin LQFP , the W83971D can be placed on the motherboard, daughter board, add-on cards, PCMCIA cards, or outside the main chassis such as in speakers.
2. FEATURE LIST
* 16-bit stereo full-duplex codec with fixed 48KHz sampling rate * S/N ratio: 85dB (analog to analog), 75dB(analog to digital), 85dB(digital to analog) * Four analog line-level stereo inputs for connection from LINE IN, CD, VIDEO, and AUX * Two analog line-level mono inputs for speakerphone and PC BEEP * Mono mic input switchable from two external sources * High quality pseudo-differential CD input * Stereo line-level output * Mono output for speakerphone * 3D stereo enhancement * Multiple Codec Support * Power management support * Single 5V supply or analog 5V, digital 3.3V * Packaged in 48-pin LQFP
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Preliminary W83971D
3. FUNCTIONAL BLOCK DIAGRAM
PC_BEEP PHONE PCM OUT LINE CD VIDEO AUX MIC1 MIC2 M U X VOL +20dB DAC VOL VOL VOL VOL VOL VOL MUTE MUTE MUTE MUTE MUTE MUTE MASTER VOLUME
LINE_OUT
3D 3D
M U X
MONO VOLUME
MONO_OUT
SYNC BIT_CLK SDATA_OUT SDATA_IN RESET# XTL_IN XTL_OUT
AC'97 Digital Interface
M U X
MASTER INPUT VOLUME
ADC
PCM IN
OSC
OSC
Figure 3.1: W83971D Functional Block Diagram
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Preliminary W83971D
4. PINOUT AND PACKAGE
DVdd1 1 XTL_IN 2 XTL_OUT 3 DVss1 4 SDATA_OUT 5 BIT_CLK 6 DVss2 7 SDATA_IN 8 DVdd2 9 SYNC 10 RESET# 11 PC_BEEP 12
48 47 46 45 44 43 42 41 40 39 38 37
NC NC ID1# ID0# NC NC AVss2 NC NC NC AVdd2 MONO_OUT
W83971D
48 LQFP
36 35 34 33 32 31 30 29 28 27 26 25
LINE_OUT_R LINE_OUT_L NC NC NC NC AFLT2 AFLT1 Vrefout Vref AVss1 AVdd1
Figure 4.1: W83971D 48-pin Package and Pinout
PHONE AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND CD_R MIC1 MIC2 LINE_IN_L LINE_IN_R
13 14 15 16 17 18 19 20 21 22 23 24
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Preliminary W83971D
W83971D 48-LQFP Pin List
PIN# 1 2 3 4 5 6 7 8 9 10 11 12 SIGNAL NAME DVdd1 XTL_IN XTL_OUT DVss1 SDATA_OUT BIT_CLK DVss2 SDATA_IN DVdd2 SYNC RESET# PC_BEEP PIN# 13 14 15 16 17 18 19 20 21 22 23 24 SIGNAL NAME PHONE AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND CD_R MIC1 MIC2 LINE_IN_L LINE_IN_R PIN# 25 26 27 28 29 30 31 32 33 34 35 36 SIGNAL NAME AVdd1 AVss1 Vref Vrefout AFLT1 AFLT2 NC NC NC NC LINE_OUT_L LINE_OUT_R PIN# 37 38 39 40 41 42 43 44 45 46 47 48 SIGNAL NAME MONO_OUT AVdd2 NC NC NC AVss2 NC NC ID0# ID1# NC NC
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Publication Release Date: July 1999 Revision A1
Preliminary W83971D
5. PIN DESCRIPTION
5.1 Digital I/O
SIGNAL NAME RESET# XTL_IN XTL_OUT SYNC BIT_CLK SDATA_OUT SDATA_IN TYPE I I O I I/O I O DESCRIPTION AC'97 Master Reset 24.576 MHz Crystal 24.576 MHz Crystal 48 KHz Fixed Rate Sync Pulse 12.288 MHz Serial Data Clock AC'97 Serial Data Input Stream AC'97 Serial Data Output Stream
5.2 Analog I/O
SIGNAL NAME PC_BEEP PHONE MIC1 MIC2 LINE_IN_L LINE_IN_R CD_L CD_GND CD_R VIDEO_L VIDEO_R AUX_L AUX_R LINE_OUT_L LINE_OUT_R MONO_OUT TYPE I I I I I I I I I I I I I O O O DESCRIPTION PC Speaker Beep Pass Through Telephony Subsystem Speakerphone Desktop Microphone Second Microphone Line In Left Channel Line In Right Channel CD Audio Left Channel CD Audio Analog Ground CD Audio Right Channel Video Left Channel Video Right Channel Auxiliary Left Channel Auxiliary Right Channel Line Out Left Channel Line Out Right Channel Mono Output
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Preliminary W83971D
5.3 Filter and Reference Pins
SIGNAL NAME Vref Vrefout AFLT1 AFLT2 TYPE I O I I DESCRIPTION Reference Voltage Reference Voltage Output Left Channel Anti-Aliasing Filter Capacitor Right Channel Anti-Aliasing Filter Capacitor
5.4 Power Supplies
SIGNAL NAME AVdd1 AVdd2 AVss1 AVss2 DVdd1 DVdd2 DVss1 DVss2 TYPE I I I I I I I I Digital Ground Digital Ground DESCRIPTION Analog Supply Voltage, 5V Analog Supply Voltage, 5V Analog Ground Analog Ground Digital Supply Voltage, 5V or 3.3V
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Preliminary W83971D
6. REGISTER DESCRIPTION
6.1 Register Map
Reg# 00h 02h 06h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 20h 22h 26h 28h .. .. 7Ah 7Ch 7Eh Name Reset Master Volume Master Volume Mono PC_BEEP Volume Phone Volume Mic Volume Line in Volume CD Volume Video Volume Aux Volume PCM Out Volume Record Select Record Gain General Purpose 3D Control Pwrdwn Control/Status Reserved .. .. Vendor Reserved Vendor ID1 Vendor ID2 D15 x Mute Mute Mute Mute Mute Mute Mute Mute Mute Mute x Mute x x x x .. .. x F7 T7 D14 SE4 x x x x x x x x x x x x x x x x .. .. x F6 T6 D13 SE3 ML5 x x x x x x x x x x x 3D x PR5 x .. .. x F5 T5 D12 SE2 ML4 x x x x GL4 GL4 GL4 GL4 GL4 x x x x PR4 x .. .. x F4 T4 D11 SE1 ML3 x x x x GL3 GL3 GL3 GL3 GL3 x GL3 x x PR3 x .. .. x F3 T3 D10 SE0 ML2 x x x x GL2 GL2 GL2 GL2 GL2 SL2 GL2 x x PR2 x .. .. x F2 T2 D9 ID9 ML1 x x x x GL1 GL1 GL1 GL1 GL1 SL1 GL1 MIX x PR1 x .. .. x F1 T1 D8 ID8 ML0 x x x x GL0 GL0 GL0 GL0 GL0 SL0 GL0 MS x PR0 x .. .. x F0 T0 D7 ID7 x x x x x x x x x x x x LPBK x x x .. .. x S7
REV7
D6 ID6 x x x x 20db x x x x x x x x x x x .. .. x S6
REV6
D5 ID5 MR5 MM5 x x x x x x x x x x x x x x .. .. x S5
REV5
D4 ID4 MR4 MM4 PV3 GN4 GN4 GR4 GR4 GR4 GR4 GR4 x x x x x x .. .. x S4
REV4
D3 ID3 MR3 MM3 PV2 GN3 GN3 GR3 GR3 GR3 GR3 GR3 x GR3 x DP3 REF x .. .. x S3
REV3
D2 ID2 MR2 MM2 PV1 GN2 GN2 GR2 GR2 GR2 GR2 GR2 SR2 GR2 x DP2 ANL x .. .. x S2
REV2
D1 ID1 MR1 MM1 PV0 GN1 GN1 GR1 GR1 GR1 GR1 GR1 SR1 GR1 x DP1 DAC x .. .. x S1
REV1
D0 ID0 MR0 MM0 x GN0 GN0 GR0 GR0 GR0 GR0 GR0 SR0 GR0 x DP0 ADC x .. .. x S0
REV0
Default 6C00h 8000h 8000h 0000h 8008h 8008h 8808h 8808h 8808h 8808h 8808h 0000h 8000h 0000h 0800h 000Fh x .. .. x 5745h 4301h
Table 1: Mixer Register
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Preliminary W83971D
6.2 Reset Register (Index 00h)
D15 Reg# 00h 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0000h D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
The Reset register is used to configure the hardware to a known state or is used to read the status of the current hardware configuration. Writing data to this register will set all the mixer registers to their default values. Reading data from this register will return the ID code for the device. Register Map: Register Write: Register Read: D10~D13: sets all mixer registers to default value returns ID code for device 3D stereo enhancement ID
6.3 Stereo Output Control Register (Index 02h)
D15 Reg# 02h Mute ML5 ML4 ML3 ML2 ML1 ML0 MR5 MR4 MR3 MR2 MR1 MR0 8000h D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
6.3.1 Mute Stereo Output Mute Control "1" : Mute enabled "0" : Mute disabled 6.3.2 ML[5:0] Master Output (Left Channel) Volume Control These six bits select the level of attenuation applied to the Left channel of the Stereo Output signal. The level of attenuation is programmable from 0dB to -94.5dB in 1.5dB increments, providing a total of 64 programmable levels. 6.3.3 MR[5:0] Master Output (Right Channel) Volume Control These six bits select the level of attenuation applied to the Right channel of the Stereo Output signal. The level of attenuation is programmable from 0dB to -94.5dB in 1.5dB increments, providing a total of 64 programmable levels.
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Preliminary W83971D
6.3.4 Output Volume Control Map MR0 0 1 2 3 4 5 .. .. 60 61 62 63 0 0 0 0 0 0 .. .. 1 1 1 1 MR1 0 0 0 0 0 0 .. .. 1 1 1 1 MR2 0 0 0 0 0 0 .. .. 1 1 1 1 MR3 0 0 0 0 1 1 .. .. 1 1 1 1 MR4 0 0 1 1 0 0 .. .. 0 0 1 1 MR5 0 1 0 1 0 1 .. .. 0 1 0 1 Level(dB) 0.0 -1.5 -3.0 -4.5 -6.0 -7.5 .. .. -90.0 -91.5 -93.0 -94.5
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Preliminary W83971D
6.4 Mono Output Control Register (Index 06h)
D15 Reg# 06h Mute MM5 MM4 MM3 MM2 MM1 MM0 8000h D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
6.4.1 Mute Mono Output Mute Control "1" : Mute enabled "0" : Mute disabled 6.4.2 MM[5:0] Mono Output Volume Control These six bits select the level of attenuation applied to the Mono Output signal. The level of attenuation is programmable from 0dB to -94.5dB in 1.5dB increments, providing a total of 64 programmable levels. Please refer to Stereo and Mono Output Attenuation. 6.4.3 Stereo and Mono Output Attenuation MM0 0 1 2 3 4 5 .. .. 60 61 62 63 0 0 0 0 0 0 .. .. 1 1 1 1 MM1 0 0 0 0 0 0 .. .. 1 1 1 1 MM2 0 0 0 0 0 0 .. .. 1 1 1 1 MM3 0 0 0 0 1 1 .. .. 1 1 1 1 MM4 0 0 1 1 0 0 .. .. 0 0 1 1 MM5 0 1 0 1 0 1 .. .. 0 1 0 1 LEVEL(DB) 0.0 -1.5 -3.0 -4.5 -6.0 -7.5 .. .. -90.0 -91.5 -93.0 -94.5
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Preliminary W83971D
6.5 PC_BEEP Input Volume Control Register (Index 0Ah)
D15 Reg# 0Ah PV3 PV2 PV1 PV0 0000h D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
6.5.1 Mute PC Beep Input Mute Control "1" : Mute enabled "0" : Mute disabled 6.5.2 PV[3:0] PC Beep Input Volume Control These four bits select the level of attenuation applied to the PC beep input signal. The level of attenuation is programmable from 0dB to -45dB in 3dB increments, providing a total of 16 programmable levels. The beep gain is set at 0dB when PV[3:0] = 0h.
6.6 Phone Input Volume Control Register (Index 0Ch)
D15 Reg# 0Ch Mute GN4 GN3 GN2 GN1 GN0 8008h D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
6.6.1 Mute Phone Input Mute Control "1" : Mute enabled "0" : Mute disabled 6.6.2 GN[4:0] PC Phone Input Volume Control These five bits select the gain applied to the Phone Input signal. The gain is programmable from 34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Programmable Input and Output Gain Levels .
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Preliminary W83971D
6.6.3 Programmable Input and Output Gain Levels G4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
G3
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
G2
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
G1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
G0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
LEVEL(DB)
12.0 10.5 9.0 7.5 6.0 4.5 3.0 1.5 0.0 -1.5 -3.0 -4.5 -6.0 -7.5 -9.0 -10.5 -12.0 -13.5 -15.0 -16.5 -18.0 -19.5 -21.0 -22.5 -24.0 -25.5 -27.0 -28.5 -30.0 -31.5 -33.0 -34.5
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Publication Release Date: July 1999 Revision A1
Preliminary W83971D
6.7 Mic Input Volume Control Register (Index 0Eh)
D15 Reg# 0Eh Mute 20dB GN4 GN3 GN2 GN1 GN0 8008h D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
6.7.1 Mute Mic Input Mute Control "1" : Mute enabled "0" : Mute disabled 6.7.2 20dB Mic Boost Control "1" :Fixed 20dB gain enabled "0" : Fixed 20dB gain disabled 6.7.3 GN[4:0] Mic Input Volume Control These five bits select the gain applied to the Mic Input signal. The gain is programmable from 34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Programmable Input and Output Gain Levels .
6.8 Line Input Control Register (Index 10h)
D15 Reg# 10h Mute GL4 GL3 GL2 GL1 GL0 GR4 GR3 GR2 GR1 GR0 8808h D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
6.8.1 Mute Line Input Mute Control "1" : Mute enabled "0" : Mute disabled 6.8.2 GL[4:0] Left Channel Gain Control These five bits select the gain applied to the LEFT channel of the Line Input signal. The gain is programmable from -34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Programmable Input and Output Gain Levels .
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Preliminary W83971D
6.8.3 GR[4:0] Right Channel Gain Control These five bits select the gain applied to the RIGHT channel of the Line Input signal. The gain is programmable from -34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Programmable Input and Output Gain Levels.
6.9 CD Input Control Register (Index 12h)
D15 Reg# 12h Mute GL4 GL3 GL2 GL1 GL0 GR4 GR3 GR2 GR1 GR0 8808h D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
6.9.1 Mute Line Input Mute Control "1" : Mute enabled "0" : Mute disabled 6.9.2 GL[4:0] Left Channel Gain Control These five bits select the gain applied to the LEFT channel of the Line Input signal. The gain is programmable from -34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Programmable Input and Output Gain Levels . 6.9.3 GR[4:0] Right Channel Gain Control These five bits select the gain applied to the RIGHT channel of the Line Input signal. The gain is programmable from -34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Table 3: Programmable Input and Output Gain Levels .
6.10 Video Input Control Register (Index 14h)
D15 Reg# 14h Mute GL4 GL3 GL2 GL1 GL0 GR4 GR3 GR2 GR1 GR0 8808h D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
6.10.1 Mute Line Input Mute Control "1" : Mute enabled "0" : Mute disabled
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Preliminary W83971D
6.10.2 6.10.2
GL[4:0] Left Channel Gain Control
These five bits select the gain applied to the LEFT channel of the Line Input signal. The gain is programmable from -34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Programmable Input and Output Gain Levels . 6.10.3 GR[4:0] Right Channel Gain Control These five bits select the gain applied to the RIGHT channel of the Line Input signal. The gain is programmable from -34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Programmable Input and Output Gain Levels .
6.11 Auxiliary Input Control Register (Index 16h)
D15 Reg# 16h Mute GL4 GL3 GL2 GL1 GL0 GR4 GR3 GR2 GR1 GR0 8808h D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
6.11.1 Mute Line Input Mute Control "1" : Mute enabled "0" : Mute disabled 6.11.2 GL[4:0] Left Channel Gain Control These five bits select the gain applied to the LEFT channel of the Line Input signal. The gain is programmable from -34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Programmable Input and Output Gain Levels . 6.11.3 GR[4:0] Right Channel Gain Control These five bits select the gain applied to the RIGHT channel of the Line Input signal. The gain is programmable from -34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Programmable Input and Output Gain Levels .
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Preliminary W83971D
6.12 PCM Output Control Register (Index 18h)
D15 Reg# 18h Mute GL4 GL3 GL2 GL1 GL0 GR4 GR3 GR2 GR1 GR0 8808h D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
6.12.1 Mute Line Input Mute Control "1" : Mute enabled "0" : Mute disabled 6.12.2 GL[4:0] Left Channel Gain Control These five bits select the gain applied to the LEFT channel of the Line Input signal. The gain is programmable from -34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Programmable Input and Output Gain Levels . 6.12.3 GR[4:0] Right Channel Gain Control These five bits select the gain applied to the RIGHT channel of the Line Input signal. The gain is programmable from -34.5dB to 12dB in 1.5dB increments, providing a total of 32 programmable levels. Please refer to Programmable Input and Output Gain Levels .
6.13 Record Select Register (Index 1Ah)
D15 Reg# 1Ah SL2 SL1 SL0 SR2 SR1 SR0 0000h D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
6.13.1 Record Source Select(Left Channel)
SL<2:0> <000> <001> <010> <011> <100> <101> <110> <111> Left Record Source Mic CD_L Video In_L Aux In_L Line In_L Stereo Mix_L Mono Mix Phone
Record Source Select(Right Channel)
SR<2:0> <000> <001> <010> <011> <100> <101> <110> <111> Right Record Source Mic CD_R Video In_R Aux In_R Line In_R Stereo Mix_R Mono Mix Phone
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Publication Release Date: July 1999 Revision A1
Preliminary W83971D
6.14 Record Gain Control Register (Index 1Ch)
D15 Reg# 1Ch Mute GL3 GL2 GL1 GL0 GR3 GR2 GR1 GR0 8000h D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
6.14.1 Mute Record Mute Control "1" : Mute enabled "0" : Mute disabled 6.14.2 GL[3:0] Record Gain Control (Left Channel) These four bits select the gain applied to the LEFT channel recording source. The gain is programmable from 0dB to 22.5dB in 1.5dB increments, providing a total of 16 programmable levels. The gain is set at 0dB when GL[3:0] = 0h. 6.14.3 GR[3:0] Record Gain Control (Right Channel) These four bits select the gain applied to the RIGHT channel recording source. The gain is programmable from 0dB to 22.5dB in 1.5dB increments, providing a total of 16 programmable levels.
6.15 General Purpose Register (Index 20h)
D15 Reg# 20h 3D MIX MS LPBK 0000h D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
6.15.1 3D Stereo Enhancement
"1" : Enabled "0" : Disabled
6.15.2 MIX Mono Output Mode
"1" : Mic Output "0" : Mono mix output
6.15.3 MS Microphone Select
"1" : Microphone 2 "0" : Microphone 1
6.15.4 LPBK Loopback Mode
"1" : DAC/ADC Loopback enabled "0" : DAC/ADC Loopback disabled
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Preliminary W83971D
6.16 3D Control Register (Index 22h)
D15 Reg# 22h DP3 DP2 DP1 DP0 0000h D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
This Register is used to control the depth of the 3D stereo enhancement function built into of the AC97 controller. 6.16.1 Depth of 3D Control Level
DP3 ... DP0 0 1 ... 14 15 Depth 0% 6.67% ... 93.33% 100%
6.17 Power Down and Status Register (Index 26h)
D15 Reg# 26h PR5 PR4 PR3 PR2 PR1 PR0 REF ANL DAC ADC 0000h D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
6.17.1 PR[5:0] Power Down Mode Bits These read/write bits are used to control the power down states of the W83971D. Each power down function bit is enabled by setting the respective bit high. The power down modes controlled by each bit is described in the table below: 6.17.2 Status (READ Only) bits These bits are used to monitor the readiness of some sections of the W83971D. Reading a "1" from any of these bits would be an indication of a "ready" state.
D<3:0> REF ANL DAC ADC Status Read Only Bits Vref at Nominal Levels Mixers, Mux & Volume Controls Ready DAC Ready to Accept Data ADC Ready to Transmit Data PR<5:0> PR0 PR1 PR2 PR3 PR4 PR5 Power Down Mode Bits ADC & Mux Power down DAC Power down Mixer (Vref on) Power down Mixer (Vref off) Power down AC-Link (BIT_CLK off) Power down Internal Clock Disable
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Publication Release Date: July 1999 Revision A1
Preliminary W83971D
6.18 Vendor Identification Registers (Index 7Ch, 7Eh)
D15 Reg# 7Ch 7Eh 0 0 1 1 0 0 1 0 0 0 1 0 1 1 1 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 1 5745h 4301h D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
The upper and lower byte of this register (index 7Ch), in conjunction with the upper byte of index register 7Eh, make up the vendor identification code for the W83971D. The Vendor ID Code (in ASCII format) is equal to WEC (Winbond Elec. Inc.,), where: F[7:0] Upper Byte (Index 7Ch) D[15:8] = W S[7:0] Lower Byte (Index 7Ch) D[7:0] = E T[15:8] Upper Byte (Index 7Eh) D[15:8] = C The upper byte of this register is used in conjunction with index register 7Ch to make up the Vendor ID code for the W83971D. The lower byte identifies the revision code of the W83971D. T[15:8] See description in Vendor Identification Register. REV[7:0] Revision ID "01" as Revision Number.
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Preliminary W83971D
7. MULTIPLE CODEC EXTENSION
One primary and a maximum of three secondary codecs may be supported as an option.
7.1 Multiple Codec Mode Select
ID0 NC pull down NC pull down ID1 NC NC pull down pull down Codec Mode Primary Codec Secondary Codec 1 Secondary Codec 2 Secondary Codec 3
Note: Digital Controller supports four DATA_IN pins to support one primary and three secondary codecs. BIT_CLK is an output for the primary codec and an input pin for the controller and secondary codecs.
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Preliminary W83971D
7.2 Multiple Codec Example
One primary codec and three secondary codecs, with ID0 and ID1 defining which codec is primary and the order of the secondary codecs. Note that the ID0 and ID1 are internally pulled up; therefore, when left floating they configure Codec as Primary. Note: 1 = pull up. 0 = pull down.
DC '97 SYNC BIT_CLK SDATA_OUT RESET# SDATA_IN0 SDATA_IN1 SDATA_IN2 SDATA_IN3
AC'97 ~ Primary SYNC BIT_CLK SDATA_OUT RESET# SDATA_IN
ID1 ID0
1 1
AC'97 ~ Secondary #1 SYNC BIT_CLK SDATA_OUT RESET# SDATA_IN
ID1 ID0
1 0
AC'97 ~ Secondary #2 SYNC BIT_CLK SDATA_OUT RESET# SDATA_IN
ID1 ID0
0 1
AC'97 ~ Secondary #3 SYNC BIT_CLK SDATA_OUT RESET# SDATA_IN
ID1 ID0
0 0
Figure 7.1: Multiple Codec Example
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Preliminary W83971D
8. ELECTRICAL SPECIFICATIONS
8.1 DC Characteristics
TA = 25C, DVDD = 5.0V or 3.3V +/- 5%; AVss = DVss = 0V; 50 pF load
PARAMETERS Input Voltage Range Input Voltage (low) Input Voltage (high) Output Voltage (low) Output Voltage (high) Input Leakage Current (AC-Link) Output Leakage Current (AC-Link and Hi-Z) Output Buffer Drive Current
SYMBOL VIN VIL VIH VOL VOH
MIN. -0.3 0.4 x VDD
TYP.
MAX. VDD + 0.3 0.3 x VDD 0.2 x VDD
UNITS V V V V V A A mA
0.5 x VDD -10 -10 5 10 10
8.2 AC Timing Characteristics
Timing Diagrams
TA = 25C, DVDD = 5.0V or 3.3V +/- 5%; AVss = DVss = 0V; 50 pF load
Cold Reset/Warm Reset
Trst2clk Cold Reset RESET# Trst_low
BIT_CLK
PARAMETERS RESET# active low pulse width RESET# inactive to BIT_CLK startup delay
SYMBOL Trstlow Trst2clk
MIN. 1 162.8
TYP.
MAX.
UNITS S S
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Preliminary W83971D
Warm Reset
Tsync2clk Tsync_high
SYNC BIT_CLK
PARAMETERS SYNC active high pulse width SYNC inactive to BIT_CLK startup delay
SYMBOL Tsync_high Tsync2clk
MIN.
TYP. 1.3
MAX.
UNITS S nS
162.8
8.3 BIT_CLK / SYNC
Duty Cycle: 40/60 (worst case)
Tclk_low Tclk_high
BIT_CLK Tclk_period Tsync_high Tsync_low
SYNC Tsync_period
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Preliminary W83971D
PARAMETERS BIT_CLK frequency BIT_CLK period BIT_CLK output jitter BIT_CLK pulse width (high) BIT_CLK pulse width (low) SYNC frequency SYNC period SYNC pulse width (high) SYNC pulse width (low)
SYMBOL Tclk_period Tclk_high Tclk_low Tsync_period Tsync_high Tsync_low
MIN.
TYP. 12.288 81.4
MAX.
UNITS MHz nS
750 32.56 32.56 40.7 40.7 48 20.8 1.3 19.5 48.84 48.84
pS nS nS KHz S S S
8.4 Setup and Hold
Load Capacitance: 50 pF
Thold Tsetup
BIT_CLK
SDATA_IN, SDATA_OUT Thold Tsetup SYNC
PARAMETERS SDATA_OUT setup to falling edge of BIT_CLK SDATA_OUT hold from falling edge of BIT_CLK SYNC setup to rising edge of BIT_CLK SYNC hold from rising edge of BIT_CLK
SYMBOL Tsetup Thold Tsetup Thold
MIN. 15 5 15 5
TYP.
MAX.
UNIT S nS nS nS nS
Note: SDATA_IN setup and hold calculations determined by AC'97 Controller propagation delay
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Publication Release Date: July 1999 Revision A1
Preliminary W83971D
8.5 Rise and Fall
BIT_CLK, SYNC
SDATA_IN, SDATA_OUT Trise Tfall
PARAMETERS BIT_CLK rise time BIT_CLK fall time SYNC rise time SYNC fall time SDATA_IN rise time SDATA_IN fall time SDATA_OUT rise time SDATA_OUT fall time
SYMBOL Trise Tfall Trise Tfall Trise Tfall Trise Tfall
MIN. 2 2 2 2 2 2 2 2
TYP.
MAX. 6 6 6 6 6 6 6 6
UNITS nS nS nS nS nS nS nS nS
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Preliminary W83971D
8.6 AC_Link Low Power Mode
SYNC
Slot 1
Slot 2
BIT_CLK Ts2_pdown
SDATA_OUT
SDATA_IN
PARAMETERS End of Slot 2 to BIT_CLK/SDATA_IN low
Note: BIT_CLK not to scale
SYMBOL Ts2_pdown
MIN.
TYP.
MAX. 1
UNITS S
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Publication Release Date: July 1999 Revision A1
Preliminary W83971D
8.7 ATE/ Vendor Test Mode
RESET# Tsetup2rst SDATA_OUT, SYNC Toff SDATA_IN, BIT_CLK Hi-Z
PARAMETERS SDATA_OUT/SYNC setup to RESET# rising edge RESET# rising edge to Hi-Z state
SYMBOL Tsetup2rst Toff
MIN. 15
TYP.
MAX.
UNITS nS
25
nS
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Preliminary W83971D
9. PERFORMANCE SPECIFICATIONS
9.1 Analog Characteristics
TA = 25C, AVDD = DVDD = 5.0V +/- 5%; AVss = DVss = 0V; 10 K/50 pF load Fs = 48 KHz, 0 dB = 1 Vrms; BW: 20 Hz ~ 20 KHz, 0 dB attenuation
PARAMETERS Full Scale Input Voltage: Line Inputs Mic Inputs (20dB = 0) Mic Inputs (20dB = 1) Full Scale Output Voltage: Line Outputs Mono Output Analog S/N: CD to LINE_OUT Other to LINE_OUT Analog Frequency Response: Digital S/N: D/A A/D Total Harmonic Distortion: Line Outputs D/A & A/D Frequency Response: D/A A/D Transition Band: D/A A/D Stop Band: D/A A/D Stop Band Rejection: D/A A/D Out-of-Band Rejection: Group Delay: Power (1kHz) Supply Rejection Ratio:
SYMBOL
MIN.
TYP. 1.0 1.0 0.1 1.0 1.0
MAX.
UNITS Vrms Vrms Vrms Vrms Vrms dB
90 85 20 85 75 90 80 0.007 20 20 19,200 19,200 28,800 28,800 -74 -74 -40 1 -40 0.02 19,200 19,200 28,800 28,800 infinite infinite 20,000
dB Hz dB dB % Hz Hz Hz Hz Hz Hz dB dB dB mS dB
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Preliminary W83971D
PARAMETERS (1kHz) Input Channel Crosstalk: Spurious Tone Reduction: Attenuation, Gain Step Size Input Impedance: Input Capacitance: Vrefout
Notes: VIL = 0.8V, VIH = 2.4V Analog Frequency Response has 1dB limits SNR of rms output level with 1 KHz full-scale input to rms output level with all zeros into digital input Measured "A wtd" over a 20 Hz ~ 20 KHz bandwidth (AES17-1991 Idle Channel Noise or EIAJ CP-307 SNR) THD: 0dB gain, 20 KHz BW, Fs = 48 KHz A/D & D/A Frequency Response has 0.25 dB limits Stop Band Rejection determines filter requirements Out-of-Band rejection determines audible noise Integrated Out-of-Band noise generated by DAC during normal PCM audio playback over: BW = 28.8 KHz ~ 100 KHz, with respect to 1 Vrms DAC output
SYMBOL
MIN.
TYP.
MAX. -70
UNITS dB dB dB K ohm pF V
-100 1.5 10 50 15 1.5
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Preliminary W83971D
9.2 Miscellaneous Analog Performance Characteristics:
TA = 25C, AVDD = DVDD = 5.0V +/- 5%; AVss = DVss = 0V; 10 K/50 pF load Fs = 48 KHz, 0 dB = 1 Vrms; BW: 20 Hz ~ 20 KHz, 0 dB attenuation
PARAMETERS
Mixer Gain Range Span: LINE_IN, PHONE PC_BEEP LINE_OUT, MONO_OUT Mixer Step Size: All Volume Controls Except PC_BEEP PC_BEEP Mixer Mute Level: Mixer Gain: Interchannel Gain Mismatch Gain Drift A/D and Analog Inputs: (Rs = 50 ohms) Resolution Gain Error Offset Error Input Impedance D/A and Analog Outputs: Resolution Interchannel Isolation Interchannel Gain Mismatch Gain Error Gain Drift AUX, VIDEO, MIC1, MIC2,
SYMBOL
MIN
TYP
46.5 45 94.5
MAX
UNITS
dB dB dB
1.5 3.0 110
dB dB dB
-0.5 100
0.5
dB ppm/C
16 2 10 50 5
bits % mV k ohm
16 85 0.1 0.2 5 60
bits dB dB % ppm/C
Note: Gain Error and Offset Error expressed in terms of values
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Publication Release Date: July 1999 Revision A1
Preliminary W83971D
9.3 Power Consumption:
TA = 25C, AVDD = DVDD = 5.0V +/- 5%; AVss = DVss = 0V; 50 pF load
PARAMETERS Digital Supply Current: Power Up Power Down Analog Supply Current: Power Up Power Down
SYMBOL lvdd lvdd lavd lavd
MIN.
TYP. 70 0.1 28 0.1
MAX.
UNITS mA mA mA mA
10. POWER MANAGEMENT
Power Management is capable of shutting down portions of the Codec with Control Bits PR<5:0> PR0 PR1 PR2 PR3 PR4 PR5 POWER DOWN MODE BITS PCM_IN ADC & Input MUX Powerdown PCM_OUT DAC Powerdown Analog Mixer Powerdown (Vref on) Analog Mixer Powerdown (Vref off) Digital Interface (AC-Link) Powerdown (BIT_CLK off) Internal Clock Disable
Note: Registers maintain values in sleep mode (PR4 write) and wake up with a warm reset (register values) or a cold reset (default values). Power Down and Status Register (Index 26) read action verifies stability before powerdown write action occurs.
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Preliminary W83971D
10.1 Power Down / Power Up
PR0=1
PR1=1
PR2=1
PR4=1
Normal
ADC's off PR0
DAC's off PR1
Analog off PR2 / PR3
Digital I/F off PR4
Shut off
PR0=0 & ADC=1
PR1=0 & DAC=1
PR2=0 & ANL=1 Warm Reset
Default Ready = 1 Cold Reset
Figure 10.1: Power down/Power up Procedure
Note: In the example above, the Analog Mixer has been disabled, but the Vref is still on.
Complete Power Down of the AC'97 device is achieved by sequential writes to the Power Down and Status Control Register (Index 26h): Normal Operation: ADCs and Input Mux: DACs: Analog Mixer: Vrefout: AC-Link: Internal Clocks: PR<5:0> = 0 PR0 = 1 (write) PR1 = 1 (write) PR2 = 1 (write) PR3 = 1 (write) PR4 = 1 (write) PR5 = 1 (write)
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Preliminary W83971D
PR0=1
PR1=1
PR4=1
Normal
ADC's off PR0
DAC's off PR1
Digital I/F off PR4
Shut off
PR0=0 & ADC=1
PR1=0 & DAC=1 Warm Reset
Figure 10.2: Power Down Procedure with Analog Section Still Active
Note: To Power Up the Codec, a Warm Reset or a Cold Reset is required; PR4 is reset to zero upon either reset.
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Preliminary W83971D
11. TEST MODE OPERATION
11.1 ATE Test Mode:
PCB In-Circuit Testing of the W83971D SDATA_OUT is sampled at the rising edge of RESET# to enter ATE test mode SDATA_IN and BIT_CLK outputs are driven to a high impedance (Hi-Z) state
Note: this case never occurs during normal operation
11.2 Vendor Test Mode:
Vendor test mode is entered when SYNC is sampled at the rising edge of RESET# .
Note: this case never occurs during normal operation
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Preliminary W83971D
12. TYPICAL CONNECTION DIAGRAM
DVDD
AVDD
10uF
0.1uF
0.1uF
0.1uF
0.1uF
10uF
DGND 25 38 1 9 24.576MHz 3 2 AVDD 22pF DGND 4.7K 47K PC_BEEP 1uF PHONE 1uF AUX_L 1uF AUX_R 1uF VIDEO_L 1uF VIDEO_R 1uF CD_L 1uF CD_GND 1uF CD_R 1uF MIC1 1uF MIC2 1uF LINE_IN_L 1uF LINE_IN_R 1uF 22pF DGND 11 6 10 8 5 12 13 14 15 16 17 18 19 20 21 22 23 24 47 48 35 36 37 33 34 39
AGND 1uF 1uF 1uF
DVDD1
DVDD2
AVDD1
AVDD2
XTL_OUT XTL_IN RESET# BIT_CLK SYNC SDATA_IN SDATA_OUT PC_BEEP PHONE AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND
LINE_OUT_L LINE_OUT_R MONO_OUT M_VREF/CAP3 M_AFLIT/CAP4 HP_OUT_L/CAP11 HP_OUT_C/CAP12 HP_OUT_R/CAP13 HXAN/CAP5 HXAP/CAP6 TXAN/CAP7 TXAP/CAP8 VREFOUT
LINE_OUT_L LINE_OUT_R MONO_OUT
47K
47K
47K
AGND 40 41 43 44 45 46 28 AGND 27 29 30 31 32 270pF AGND 270pF AGND 0.1uF 10uF
AGND
AGND
0.1uF
10uF
CD_R VREF MIC1 AFILT1 MIC2 AFILT2 LINE_IN_L AFILT3/CAP1 LINE_IN_R CAP2 RXAN/CAP9 RXAP/CAP10 DVSS1 4 DVSS2 DGND 7 AVSS1 26 AVSS2 AGND 42 W83971D
AGND
Note: We suggest to use 3.3V digital power and 5.0V analog power. The performance will be better
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Preliminary W83971D
13. HOW TO READ THE TOP MARKING
The top marking of W83781D
W83971D 745AA
Left: Winbond logo 1st line: Type number W83971D, D means LQFP (Thickness = 1.4 mm). 2nd line: Tracking code 745 A A 745: packages made in '97, week 45 A: assembly house ID; A means ASE, O means OSE A: IC revision; A means version A, B means version B
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Publication Release Date: July 1999 Revision A1
Preliminary W83971D
14. PACKAGE DIMENSIONS
48-pin QFP
HD D
36 25
Dimension in inch
Dimension in mm Min.
--0.05 1.35 0.17 0.09
Symbol
Min.
Nom.
Max.
Nom.
----1.40 0.20 --7.00 7.00 0.50 9.00 9.00
Max.
1.60 0.15 1.45 0.27 0.20
37
24
E
HE
48
13
1
e
b
12
A A1 A2 b c D E e HD HE L L1 y 0
Notes:
c
0.45
0.60 1.00
0.75
--0
0.08 3.5
--7
A2
A
Seating Plane
See Detail F
A1 y
L L1 Detail F
1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec.
Headquarters
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792646 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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Preliminary W83971D
15. APPENDIX A: TEST REPORT
W83971D ALPHA TEST REPORT (V1.0)
Features:
. 16-bit stereo full-duplex codec with fixed 48KHz sampling rate . S/N ratio: 85dB (analog to analog), 75dB (analog to digital), 85dB (digital to analog) . Four analog line-level stereo inputs for connection from LINE IN, CD, VIDEO, and AUX . Two analog line-level mono inputs for speakerphone and PC BEEP . Mono mic input switchable from two external sources . High quality pseudo-differential CD input . Stereo line-level output . Mono output for speakerphone . 3D stereo enhancement . Multiple Codec Support . Power management support . Single 5V supply or analog 5V, digital 3V . Package: 48-pin LQFP
Test Environment:
. Auido Precision System II, Apwin v1.5 . Motherboard: Micro Star PII MS_6119 . Hard Disk: Quantum Big Foot . VGA: Triplex S3 Trio/Virge . Test board with ForteMedia sound controller. . Windows 95 English. . SpectraPlus . Sound Forge V4.5 . Audio Codec Test Program.
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Publication Release Date: July 1999 Revision A1
Preliminary W83971D
1. Functionality Test
1.1 Playback . PC(DAC) - LINE_OUT: . PC_BEEP - LINE_OUT: . PHONE - LINE_OUT: . LINE_IN - LINE_OUT: . CD - LINE_OUT: . VIDEO - LINE_OUT: . AUX - LINE_OUT: . MIXER - MONO_OUT: . MIC1 - MONO_OUT: . MIC2 - MONO_OUT: 1.2 Record . PHONE: . LINE_IN: . CD: . VIDEO: . AUX: . MIC: . STEREO: . MONO_MIX: 1.3 Attenuation and Gain . PC(DAC): . PC_BEEP: . PHONE: . LINE_IN: . CD: . VIDEO: . AUX: . MIC1: . MIC2: . +20 dB of MIC: ok ok ok ok ok ok ok ok ok ok ok ok ok ok ok ok ok ok ok ok ok ok ok ok ok ok ok ok
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Preliminary W83971D
1.4 Resets of cold, warm and register: ok 1.5 Power Management: ok 1.6 3D depth function: ok
2. Performance
2.1 Input Full Scale . PC_BEEP: . PHONE: . LINE_IN: . CD: . VIDEO: . AUX: . MIC1: . MIC2: 2.2 Output Full Scale . LINE_OUT: . MONO_OUT: . PC_BEEP - LINE_OUT: . PHONE - LINE_OUT: . LINE_IN - LINE_OUT: . CD - LINE_OUT: . VIDEO - LINE_OUT: . AUX - LINE_OUT: . MIC1 - MONO_OUT: . MIC2 - MONO_OUT: 2.4 Analog Frequency Response . PC_BEEP - LINE_OUT: . PHONE - LINE_OUT: . LINE_IN - LINE_OUT: . CD - LINE_OUT: . VIDEO - LINE_OUT: . AUX - LINE_OUT: . MIC1 - MONO_OUT: . MIC2 - MONO_OUT: pass pass pass pass pass pass pass pass Publication Release Date: July 1999 Revision A1 pass pass pass pass pass pass pass pass pass pass pass pass pass pass pass pass pass pass
2.3 Analog SNR (Analog input to Analog output)
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Preliminary W83971D
2.5 Digital SNR (For more details, please refer to the attached figures created by using Audio Precision System II) D/A (Digital to Analog path) pass
. PC(DAC) - LINE_OUT: A/D
(Analog to Digital Record path) pass pass pass pass pass pass
. PHONE: . LINE_IN: . CD: . VIDEO: . AUX: . MIC:
2.6 THD+N (Total Harmonic Distortion + Noise) A/A (Analog input to Analog output) pass pass pass pass pass pass pass pass . PC_BEEP - LINE_OUT: . PHONE - LINE_OUT: . LINE_IN - LINE_OUT: . CD - LINE_OUT: . VIDEO - LINE_OUT: . AUX - LINE_OUT: . MIC1 - MONO_OUT: . MIC2 - MONO_OUT: D/A
(Digital to Analog path)
. PC(DAC) - LINE_OUT: pass A/D (Analog to Digital Record path) pass pass pass pass pass pass
. PHONE: . LINE_IN: . CD: . VIDEO: . AUX: . MIC:
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Preliminary W83971D
2.7 D/A Frequency Response
(Digital to Analog path)
. PC(DAC) - LINE_OUT: pass 2.8 A/D Frequency Response . PHONE: . LINE_IN: . CD: . VIDEO: . AUX: . MIC: pass pass pass pass pass pass (Analog to Digital Record path)
2.9 Cross Talk between Inputs channels . LINE_IN - LINE_OUT: . CD - LINE_OUT: . VIDEO - LINE_OUT: . AUX - LINE_OUT: . PC(DAC) - LINE_OUT: 2.10 Power Consumption . Analog Power Up . Analog Power Down . Digital Power Up . Digital Power Down 21.7 mA 0.4 mA 68.5 mA 1.8 mA pass pass pass pass pass
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Publication Release Date: July 1999 Revision A1
Preliminary W83971D
Audio Precision
Winbond W83971D A-A THD+N (LINE_IN)
01/12/99 12:03:35
+0 -20 -40 d B V 0 5k 10k Hz
THD+N -91dBV (L), -91dBV (R); -3dBV amplitude a-weighted. 0.003% wb_aa_line_in_thdn-3db.at2
-60 -80
15k
20k
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Preliminary W83971D
Audio Precision
Winbond W83971D A-A SNR (LINE_IN)
01/12/99 11:18:03
+0 -20 -40 d B V 0 5k 10k Hz
SNR -92dBV (L), -92dBV (R) -60dBV amplitude a-weighted. wb_aa_line_in_snr-60db.at2
-60 -80
15k
20k
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Preliminary W83971D
Audio Precision
Winbond W83971D A-A Freq Response (LINE_IN)
01/12/99 11:20:03
+1 +0 d B r A -1 -2 -3 -4 20 50 100 200 500 1k Hz 2k 5k 10k 20k
0dBV Frequency Response wb_aa_line_in_fr.at2
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Preliminary W83971D
Audio Precision
Winbond W83971D A-D-A THD+N (LINE_IN)
01/12/99 12:06:04
+0 -20 -40 d B V 0 5k 10k Hz
THD+N -80dBV (L), -80dBV (R); -3dBV amplitude a-weighted. 0.01% wb_ada_line_in_thdn-3db.at2
-60 -80
15k
20k
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Publication Release Date: July 1999 Revision A1
Preliminary W83971D
Audio Precision
Winbond W83971D A-D-A SNR (LINE_IN)
01/12/99 11:26:55
+0 -20 -40 d B V 0 5k 10k Hz
SNR -88dBV (L), -88dBV (R) -60dBV amplitude a-weighted. wb_ada_line_in_snr-60db.at2
-60 -80
15k
20k
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Preliminary W83971D
Audio Precision
Winbond W83971D A-D-A Freq Response (LINE_IN)
01/12/99 11:32:26
+1 +0 d B r A -1 -2 -3 -4 20 50 100 200 500 1k Hz 2k 5k 10k 20k
0dBV Frequency Response wb_ada_line_in_fr.at2
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Publication Release Date: July 1999 Revision A1
Preliminary W83971D
Audio Precision
Winbond W83971D D-A THD+N (LINE_IN)
01/12/99 11:56:12
+0 -20 -40 d B V 0 5k 10k Hz
THD+N -83dBV (L), -83dBV (R); -3dBV amplitude a-weighted. 0.007% wb_da_line_out_thdn-3db.at2
-60 -80
15k
20k
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Preliminary W83971D
Audio Precision
Winbond W83971D D-A SNR (LINE_IN)
01/12/99 11:54:05
+0 -20 -40 d B V 0 5k 10k Hz
SNR -85dBV (L), -85dBV -60dBV amplitude a-weighted. wb_da_line_out_snr-60db.at2
-60 -80
15k
20k
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Preliminary W83971D
16.
Audio Precision
Winbond W83971D D-A Freq Response (LINE_IN)
01/12/99 12:00:02
+1 +0 d B r A -1 -2 -3 -4 20 50 100 200 500 1k Hz 2k 5k 10k 20k
0dB Frequency Response wb_da_line_out_fr.at2
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Preliminary W83971D
APPENDIX B: LAYOUT GUIDE
Vrefout to via 270pF NPO 10uF 0.1uF To +5VA
To+5VA AFLT2 AFLT1 AVdd2 0.1uF To Analog Ground Analog Ground AVss2 VREF AVss1 AVdd1
To Analog Ground
DVss1 Pin1
DVdd1
0.1uF
DVss2
DVdd2 0.1uF To+5VD
To+5VD To Digital Ground
* The above figure is the suggested layout for W83971D. * The decoupling capacitors should be located physically as close to the pins as possible. * The device should be located on a locally separate analog ground plane to keep noise from the digital ground return currents from modulating the W83971D" ground potential and degrading performance.
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Publication Release Date: July 1999 Revision A1
Preliminary W83971D
* The digital ground pins should be connected to the digital ground plane and kept separate from any of the analog ground connections and analog circuitry. * The common connection point between the two ground planes should be located near the W83971D just under the digital ground connections. * The AC-Link digital interface connection traces should be routed such that digital ground plane lies underneath these signals from the AC97 controller continuously to the W83971D.
Headquarters
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792646 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
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