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PRELIMINARY
W144
440BX AGPset Spread Spectrum Frequency Synthesizer
Features
* Maximized EMI suppression using Cypress's Spread Spectrum technology * Single chip system frequency synthesizer for Intel(R) 440BX AGPset * Two copies of CPU output * Six copies of PCI output * One 48-MHz output for USB * One 24-MHz output for SIO * Two buffered reference outputs * One IOAPIC output * Thirteen SDRAM outputs provide support for 3 DIMMs * Supports frequencies up to 150 MHz * I2CTM interface for programming * Power management control inputs Table 1. Mode Input Table Mode 0 1 PCI_STOP# REF0 Pin2
Table 2. Pin Selectable Frequency FS3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Input Address CPU_F, CPU1 FS2 FS1 FS0 (MHz) PCI_F, 1:5 (MHz) 1 1 1 133.3 33.3 (CPU/4) 1 1 0 124 31 (CPU/4) 1 0 1 150 37.5 (CPU/4) 1 0 0 140 35 (CPU/4) 0 1 1 105 35 (CPU/3) 0 1 0 110 36.7 (CPU/3) 0 0 1 115 38.3 (CPU/3) 0 0 0 120 40 (CPU/3) 1 1 1 100 33.3 (CPU/3) 1 1 0 133.3 44.43 (CPU/3) 1 0 1 112 37.3 (CPU/3) 1 0 0 103 34.3 (CPU/3) 0 1 1 66.8 33.4 (CPU/2) 0 1 0 83.3 41.7 (CPU/2) 0 0 1 75 37.5 (CPU/2) 0 0 0 124 41.3 (CPU/3)
Key Specifications
CPU Cycle-to-Cycle Jitter: ......................................... 250 ps CPU to CPU Output Skew: ........................................ 175 ps PCI to PCI Output Skew: ............................................ 500 ps VDDQ3: .................................................................... 3.3V5% VDDQ2: .................................................................... 2.5V5% SDRAMIN to SDRAM0:11 Delay: ..........................3.7 ns typ. SDRAM0:11 (leads) to SDRAM_F Skew: ..............0.4 ns typ.
Logic Block Diagram
VDDQ3 REF0/(PCI_STOP#) X1 X2 XTAL OSC
PLL Ref Freq
Pin Configuration
REF1/FS2 VDDQ2 IOAPIC VDDQ2
I/O Pin Control
Stop Clock Control
CLK_STOP#
PLL 1
/2,3,4
Stop Clock Control
CPU1 CPU_F VDDQ3 PCI_F/MODE PCI1/FS3 PCI2 PCI3 PCI4 PCI5 VDDQ3 48MHz/FS0
/2
Stop Clock Control
SDATA SCLK
I2C Logic PLL2
VDDQ3 REF0/(PCI_STOP#) GND X1 X2 VDDQ3 PCI_F/MODE PCI1/FS3 GND PCI2 PCI3 PCI4 PCI5 VDDQ3 SDRAMIN GND SDRAM11 SDRAM10 VDDQ3 SDRAM9 SDRAM8 GND SDATA I2C SCLK
{
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
VDDQ2 IOAPIC REF1/FS2* GND CPU_F CPU1 VDDQ2 CLK_STOP# SDRAM_F GND SDRAM0 SDRAM1 VDDQ3 SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDDQ3 SDRAM6 SDRAM7 VDDQ3 48MHz/FS0* 24MHz/FS1*
SDRAMIN
Stop Clock Control
12
24MHz/FS1 VDDQ3 SDRAM0:11 SDRAM_F
Note: 1. Internal pull-up resistors should not be relied upon for setting I/O pins HGH. Pin function with parentheses determined by MODE pin resistor strapping. Unlike other I/O pins, input FS3 has an internal pull down resistor.
W144
Intel is a registered trademark of Intel Corporation. I C is a trademark of Philips Corporation.
2
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 November 2, 1999, rev. **
PRELIMINARY
Pin Definitions
Pin Name CPU_F CPU1 PCI2:5 PCI1/FS3 Pin No. 44 43 10, 11, 12, 13 8 Pin Type O O O I/O
W144
PCI_F/MODE
7
I/O
CLK_STOP#
41
I
IOAPIC 48MHz/FS0
47 26
O I/O
24MHz/FS1
25
I/O
REF1/FS2
46
I/O
REF0/ (PCI_STOP#)
2
I/O
SDRAMIN SDRAM0:11
15 38, 37, 35, 34, 32, 31, 29, 28, 21, 20, 18, 17 40 24 23 4
I O
Pin Description Free-running CPU Clock: Output voltage swing is controlled by the voltage applied to VDDQ2. See Tables 2 and 6 for detailed frequency information. CPU Clock Output 1: This CPU clock output is controlled by the CLK_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ2. PCI Clock Outputs 2 through 5: These four PCI clock outputs are controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. Fixed PCI Clock Output: As an output. frequency is set by the FS0:3 inputs or through serial input interface, see Tables 2 and 6. This output is affected by the PCI_STOP# input. When an input, latches data selecting the frequency of the CPU and PCI outputs. Fixed PCI Clock Output: As an output, frequency is set by the FS0:3 inputs or through serial input interface, see Tables 2 and 6. This output is not affected by the PCI_STOP# input. When an input, sets function of pin 2. CLK_STOP# input: When brought LOW, affected clock outputs are stopped LOW after completing a full clock cycle (2-3 CPU clock latency). When brought HIGH, affected clock outputs start, beginning with a full clock cycle (2-3 CPU clock latency). IOAPIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage swing is controlled by VDDQ2. This output is disabled when CLK_STOP# is set LOW. 48-MHz Output: 48 MHz is provided in normal operation. In standard systems, this output can be used as the reference for the Universal Serial Bus. Upon power-up FS0 input will be latched, which will set clock frequencies as described in Table 2. 24-MHz Output: 24 MHz is provided in normal operation. In standard systems, this output can be used as the clock input for a Super I/O chip. Upon power-up FS1 input will be latched, which will set clock frequencies as described in Table 2. I/O Dual-Function REF0 and FS2 pin: Upon power-up, FS2 input will be latched, which will set clock frequencies as described in Table 2. When an output, this pin provides a fixed clock signal equal in frequency to the reference signal provided at the X1/X2 pins. Fixed 14.318-MHz Output 0 or PCI_STOP# Pin: Function determined by MODE pin. The PCI_STOP# input enables the PCI 1:5 outputs when HIGH and causes them to remain at logic 0 when LOW. The PCI_STOP signal is latched on the rising edge of PCI_F. Its effects take place on the next PCI_F clock cycle. When an output, this pin provides a fixed clock signal equal in frequency to the reference signal provided at the X1/X2 pins. Buffered Input Pin: The signal provided to this input pin is buffered to 13 outputs (SDRAM0:11, SDRAM_F). Buffered Outputs: These twelve dedicated outputs provide copies of the signal provided at the SDRAMIN input. The swing is set by VDDQ3, and they are deactivated when CLK_STOP# input is set LOW. Free-running Buffered Output: This dedicated output provides a copy of the SDRAMIN input which is not affected by the CLK_STOP# input Clock pin for I2C Circuitry Data pin for I2C Circuitry Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs, PCI outputs, reference outputs, 48-MHz output, and 24-MHz output. Connect to 3.3V supply. Power Connection: Power supply for IOAPIC, CPU_F, and CPU1 output buffers. Connect to 2.5V or 3.3V. Ground Connections: Connect all ground pins to the common system ground plane.
SDRAM_F SCLK SDATA X1
O I I/O I
X2 VDDQ3
5 1, 6, 14, 19, 27, 30, 36 42, 48 3, 9, 16, 22, 33, 39, 45
I P
VDDQ2 GND
P G
2
PRELIMINARY
Overview
The W144 was developed as a single-chip device to meet the clocking needs of the Intel 440BX AGPset. In addition to the typical outputs provided by standard 100-MHz 440BX FTGs, the W144 adds a thirteen output buffer, supporting SDRAM DIMM modules in conjunction with the chipset. Cypress's proprietary spread spectrum frequency synthesis technique is a feature of the CPU and PCI outputs. When enabled, this feature reduces the peak EMI measurements of not only the output signals and their harmonics, but also of any other clock signals that are properly synchronized to them.
W144
Upon W144 power up, the first 2 ms of operation is used for input logic selection. During this period, the five I/O pins (7, 8, 25, 26, 46) are three-stated, allowing the output strapping resistor on the l/O pins to pull the pin and their associated capacitive clock load to either a logic HIGH or LOW state. At the end of the 2ms period, the established logic "0" or "1" condition of the l/O pin is latched. Next the output buffer is enabled converting the l/O pins into operating clock outputs. The 2-ms timer starts when VDD reaches 2.0V. The input bits can only be reset by turning VDD off and then back on again. It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of clock outputs are <40 (nominal) which is minimally affected by the 10-k strap to ground or VDD. As with the series termination resistor, the output strapping resistor should be placed as close to the l/O pin as possible in order to keep the interconnecting trace short. The trace from the resistor to ground or VDD should be kept less than two inches in length to prevent system noise coupling during input logic sampling. When the clock outputs are enabled following the 2-ms input period, the specified output frequency is delivered on the pin, assuming that VDD has stabilized. If VDD has not yet reached full value, output frequency initially may be below target but will increase to target once VDD voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled.
VDD O utput S trapping R esistor S eries Term ination Resistor Clock Load
Functional Description
I/O Pin Operation Pins 7, 8, 25, 26, and 46 are dual-purpose l/O pins. Upon power-up these pins act as logic inputs, allowing the determination of assigned device functions. A short time after power-up, the logic state of each pin is latched and the pins become clock outputs. This feature reduces device pin count by combining clock outputs with input select pins. An external 10-k "strapping" resistor is connected between the l/O pin and ground or VDD. Connection to ground sets a latch to "0," connection to VDD sets a latch to "1." Figure 1 and Figure 2 show two suggested methods for strapping resistor connections.
10 k (Load O ption 1) W144 Power-on Reset Timer Output Buffer Output Three-state
Q
Hold Output Low
D
10 k (Load O ption 0)
Data Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Jumper Options
V DD 10 k W144 Power-on Reset Timer Output Buffer Output Three-state
Q
Output Strapping Resistor Series Termination Resistor R Clock Load
Hold Output Low
D
Resistor Value R
Data Latch
Figure 2. Input Logic Selection Through Jumper Option
3
PRELIMINARY
Spread Spectrum Feature
5dB/div
W144
As shown in Figure 3, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is dB = 6.5 + 9*log10(P) + 9*log10(F) Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The output clock is modulated with a waveform depicted in Figure 4. This waveform, as discussed in "Spread Spectrum Clock Generation for the Reduction of Radiated Emissions" by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is specified in Table 7. Figure 4 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. Spread Spectrum clocking is activated or deactivated by selecting the appropriate values for bits 1-0 in data byte 0 of the I2C data stream. Refer to Table 7 for more details.
Am p litud e (dB )
The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 3.
SSFTG
Typical Clock
-SS% Frequency Span (M Hz)
+SS%
Figure 3. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX (+0.5%)
FREQUENCY
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
MIN (-0.5%)
Figure 4. Typical Modulation Profile
4
100%
PRELIMINARY
Serial Data Interface
The W144 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Upon power-up, the W144 initializes with default register settings, therefore the use of this serial data interface is optional. The serial interface is write-only (to the clock chip) and is the dedicated function of device pins SDATA and SCLOCK. In motherboard applications, SDATA and SCLOCK are typically driven by two logic outputs of the Table 3. Serial Data Interface Control Functions Summary Control Function Clock Output Disable Description Any individual clock output(s) can be disabled. Disabled outputs are actively held LOW. Provides CPU/PCI frequency selections through software. Frequency is changed in a smooth and controlled fashion. Enables or disables spread spectrum clocking. Puts clock output into a high-impedance state. Reserved function for future device revision or production device testing. Common Application
W144
chipset. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Table 3 summarizes the control functions of the serial data interface. Operation Data is written to the W144 in eleven bytes of eight bits each. Bytes are written in the order shown in Table 4.
Unused outputs are disabled to reduce EMI and system power. Examples are clock outputs to unused PCI slots. For alternate microprocessors and power management options. Smooth frequency transition allows CPU frequency change under normal system operation. For EMI reduction. Production PCB testing. No user application. Register bit must be written as 0.
CPU Clock Frequency Selection
Spread Spectrum Enabling Output Three-state (Reserved)
Table 4. Byte Writing Sequence Byte Sequence 1 Byte Name Slave Address Bit Sequence 11010010 Byte Description Commands the W144 to accept the bits in Data Bytes 0-6 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the W144 is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). Unused by the W144, therefore bit values are ignored ("don't care"). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. Unused by the W144, therefore bit values are ignored ("don't care"). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. The data bits in Data Bytes 0-7 set internal W144 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 5, Data Byte Serial Configuration Map.
2
Command Code
Don't Care
3
Byte Count
Don't Care
4 5 6 7 8 9 10 11
Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7
Refer to Table 5
5
PRELIMINARY
Writing Data Bytes Each bit in Data Bytes 0-7 controls a particular device function except for the "reserved" bits, which must be written as a logic 0. Bits are written MSB (most significant bit) first, which is bit 7. Table 5 gives the bit formats for registers located in Data Bytes 0-7. Table 5. Data Bytes 0-7 Serial Configuration Map Affected Pin Bit(s) 7 6 5 4 3 2 1-0 Pin No. -------Pin Name -------(Reserved) SEL_2 SEL_1 SEL_0 Hardware/Software Frequency Select SEL_3 Bit 1 0 0 1 1 Bit 0 0 1 0 1 Control Function 0 -See Table 6 See Table 6 See Table 6 Hardware Software See Table 6 Function (See Table 7 for function details) Normal Operation (Reserved) Spread Spectrum On All Outputs Three-stated ----Low -Low Low -Low -Low Low Low Low Low --Low Low -Low ----Active -Active Active -Active -Active Active Active Active Active --Active Active -Active Data Byte 0 -Bit Control 1
W144
Table 6 details additional frequency selections that are available through the serial data interface. Table 7 details the select functions for Byte 0, bits 1 and 0.
Default 0 0 0 0 0 0 00
Data Byte 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Byte 3 7 6 5 4 3 2 --26 25 -21, 20, 18, 17 --48MHz 24MHz -SDRAM8:11 (Reserved) (Reserved) Clock Output Disable Clock Output Disable (Reserved) Clock Output Disable 0 0 1 1 0 1 ----40 -43 44 -7 -13 12 11 10 8 ----SDRAM_F -CPU1 CPU_F -PCI_F -PCI5 PCI4 PCI3 PCI2 PCI1 (Reserved) (Reserved) (Reserved) (Reserved) Clock Output Disable (Reserved) Clock Output Disable Clock Output Disable (Reserved) Clock Output Disable (Reserved) Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 1
Data Byte 2
6
PRELIMINARY
Table 5. Data Bytes 0-7 Serial Configuration Map (continued) Affected Pin Bit(s) 1 0 Pin No. 32, 31, 29, 28 38, 37, 35, 34 -----------47 --46 2 ----------------Pin Name SDRAM4:7 SDRAM0:3 Control Function Clock Output Disable Clock Output Disable 0 Low Low Bit Control 1 Active Active
W144
Default 1 1
Data Byte 4 7 6 5 4 3 2 1 0 Data Byte 5 7 6 5 4 3 2 1 0 Data Byte 6 7 6 5 4 3 2 1 0 Data Byte 7 7 6 5 4 3 2 1 0 --------(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) ----------------0 0 0 0 0 0 0 0 --------(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) ----------------0 0 0 0 0 0 0 0 ---IOAPIC --REF1 REF0 (Reserved) (Reserved) (Reserved) Clock Output Disable (Reserved) (Reserved) Clock Output Disable Clock Output Disable ---Low --Low Low ---Active --Active Active 0 0 0 1 0 0 1 1 --------(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) ----------------0 0 0 0 0 0 0 0
7
PRELIMINARY
Table 6. Additional Frequency Selections through Serial Data Interface Data Bytes Input Conditions Data Byte 0, Bit 3 = 1 Bit 2 SEL_3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Bit 6 SEL_2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 Bit 5 SEL_1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 Bit 4 SEL_0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 CPU, SDRAM Clocks (MHz) 133.3 124 150 140 105 110 115 120 100 133 112 103 66.8 83.3 75 124 Output Frequency
W144
PCI Clocks (MHz) 33.3 (CPU/4) 31 (CPU/4) 37.5 (CPU/4) 35 (CPU/4) 35 (CPU/3) 36.7 (CPU/3) 39.3 (CPU/3) 40 (CPU/3) 33.3 (CPU/3) 44.3 (CPU/3) 37.3 (CPU/3) 34.3 (CPU/3) 33.4 (CPU/2) 41.7 (CPU/2) 37.5 (CPU/2) 41.3 (CPU/3)
Table 7. Select Function for Data Byte 0, Bits 0:1 Input Conditions Data Byte 0 Function Normal Operation Spread Spectrum Three-state Bit 1 0 1 1 Bit 0 0 0 1 CPU_F, CPU1 Note 1 0.5% Hi-Z PCI_F, PCI1:5 Note 1 0.5% Hi-Z Output Conditions REF0:1, IOAPIC 14.318 MHz 14.318 MHz Hi-Z 48MHZ 48 MHz 48 MHz Hi-Z 24MHZ 24 MHz 24 MHz Hi-Z
Note: 2. CPU and PCI frequency selections are listed in Table 2 and Table 6.
8
PRELIMINARY
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions
.
W144
above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability Rating -0.5 to +7.0 -65 to +150 -55 to +125 0 to +70 2 (min) Unit V C C C kV
Parameter VDD, VIN TSTG TB TA ESDPROT
Description Voltage on any pin with respect to GND Storage Temperature Ambient Temperature under Bias Operating Temperature Input ESD Protection
DC Electrical Characteristics:
TA = 0C to +70C; VDDQ3 = 3.3V5%; VDDQ2 = 2.5V5% Parameter Supply Current IDD IDD Logic Inputs VIL VIH IIL IIH IIL IIH VOL VOH VOH IOL Input Low Voltage Input High Voltage Input Low Current[4] Input High Current
[4]
Description 3.3V Supply Current 2.5V Supply Current
Test Condition CPU_F, CPU1 = 100 MHz Outputs Loaded [3] CPU_F, CPU1 = 100 MHz Outputs Loaded [3]
Min.
Typ. 260 25
Max.
Unit mA mA
GND - 0.3 2.0
0.8 VDDQ3 + 0.3 -25 10 -5 +5
V V A A A A mV V V
Input Low Current (SEL100/66#) Input High Current (SEL100/66#) Output Low Voltage Output High Voltage Output High Voltage Output Low Current CPU_F,1, IOAPIC CPU_F, CPU1 PCI_F, PCI1:5 IOAPIC REF0:1 48MHz 24MHz IOL = 1 mA IOH = 1 mA IOH = -1 mA VOL = 1.25V VOL = 1.5V VOL = 1.25V VOL = 1.5V VOL = 1.5V VOL = 1.5V VOH = 1.25V VOH = 1.5V VOH = 1.25V VOH = 1.5V VOH = 1.5V VOH = 1.5V 3.1 2.2 27 20.5 40 25 25 25 25 31 40 27 27 25 57 53 85 37 37 37 55 55 87 44 44 37
Clock Outputs 50
97 139 140 76 76 76 97 139 155 94 94 76
mA mA mA mA mA mA mA mA mA mA mA mA
IOH
Output High Current
CPU_F, CPU1 PCI_F, PCI1:5 IOAPIC REF0:1 48MHz 24MHz
9
PRELIMINARY
DC Electrical Characteristics: (continued)
TA = 0C to +70C; VDDQ3 = 3.3V5%; VDDQ2 = 2.5V5% Parameter Crystal Oscillator VTH CLOAD CIN,X1 CIN COUT LIN X1 Input threshold Voltage[5] Load Capacitance, Imposed on External Crystal[6] X1 Input Capacitance[7] Input Pin Capacitance Output Pin Capacitance Input Pin Inductance Pin X2 unconnected Except X1 and X2 VDDQ3 = 3.3V 1.65 14 28 5 6 7 Description Test Condition Min. Typ. Max.
W144
Unit V pF pF pF pF nH
Pin Capacitance/Inductance
Notes: 3. All clock outputs loaded with 6" 60 traces with 22-pF capacitors. 4. W144 logic inputs (except FS3) have internal pull-up devices (pull-ups not full CMOS level). Logic input FS3 has an internal pull-down device. 5. X1 input threshold voltage (typical) is VDDQ3/2. 6. The W144 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal. 7. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
AC Electrical Characteristics
TA = 0C to +70C; VDDQ3 = 3.3V5%; V DDQ2 = 2.5V5%; fXTL = 14.31818 MHz AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; Spread Spectrum clocking is disabled. CPU Clock Outputs, CPU_F, CPU1 (Lump Capacitance Test Load = 20 pF) CPU = 66.6 MHz Parameter tP tH tL tR tF tD tJC Description Period High Time Low Time Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Test Condition/Comments Measured on rising edge at 1.25 Duration of clock cycle above 2.0V Duration of clock cycle below 0.4V Measured from 2.0V to 0.4V Measured on rising and falling edge at 1.25V Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.25V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 20 15 5.6 5.3 1.5 1.5 45 4 4 55 200 15.5 CPU = 100 MHz 10 3.3 3.1 1.5 1.5 45 4 4 55 200 10.5 ns ns ns V/ns V/ns % ps Min. Typ. Max. Min. Typ. Max. Unit
Output Rise Edge Rate Measured from 0.4V to 2.0V
tSK fST
Output Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance
250 3
250 3
ps ms
Zo
20
10
PRELIMINARY
SDRAM Clock Outputs, SDRAM, SDRAM0:11 (Lump Capacitance Test Load = 30 pF) CPU = 66.6 MHz Parameter tP tH tL tR tF tPLH tPHL tD Description Period High Time Low Time Output Rise Edge Rate Output Fall Edge Rate Prop Delay LH Prop Delay HL Duty Cycle Test Condition/Comments Measured on rising edge at 1.5V Duration of clock cycle above 2.4V, at min. edge rate (1.5 V/ns) Duration of clock cycle below 0.4V, at min. edge rate (1.5 V/ns) Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Input edge rate faster than 1 V/ns Input edge rate faster than 1 V/ns Measured on rising and falling edge at 1.5V, at min. sdge rate (1.5 V/ns) Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. Assumes full supply voltage reached within 1 ms from powerup. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 30 1.5 Min. 30 5.6 5.3 1.5 1.5 1 1 45 4 4 5 5 55 Typ. Max. CPU = 100 MHz Min. 30 3.3 3.1 1.5 1.5 1 1 45 4 4 5 5 55 Typ.
W144
Max.
Unit ns ns ns V/ns V/ns ns ns %
tJC
Jitter, Cycle-to-Cycle
250
250
ps
tSK tO
Output Skew CPU to PCI Clock Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance
250 4 1.5
250 4
ps ns
fST
3
3
ms
Zo
30
11
PRELIMINARY
PCI Clock Outputs, PCI_F and PCI1:5 (Lump Capacitance Test Load = 30 pF) CPU = 66.6/100 MHz Parameter tP tH tL tR tF tD tJC Period High Time Low Time Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Description Test Condition/Comments Measured on rising edge at 1.5V Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. 1.5 Min. 30 12.0 12.0 1 1 45 4 4 55 250 Typ. Max.
W144
Unit ns ns ns V/ns V/ns % ps
tSK tO fST
Output Skew CPU to PCI Clock Skew
500 4.0 3.0
ps ns ms
Frequency Stabilization Assumes full supply voltage reached within from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to frequency stabilization. AC Output Impedance Average value during switching transition. Used for determining series termination value. 30
Zo
IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 66.6/100 MHz Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Test Condition/Comments Frequency generated by crystal oscillator Measured from 0.4V to 2.0V Measured from 2.0V to 0.4V Measured on rising and falling edge at 1.25V 1 1 45 Min. Typ. 14.31818 4 4 55 1.5 Max. Unit MHz V/ns V/ns % ms
Frequency Stabilization Assumes full supply voltage reached within from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to frequency stabilization. AC Output Impedance Average value during switching transition. Used for determining series termination value. 15
Zo
REF0:1 Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 66.6/100 MHz Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Frequency generated by crystal oscillator Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 40 0.5 0.5 45 Min. Typ. 14.318 2 2 55 3 Max. Unit MHz V/ns V/ns % ms
Zo
12
PRELIMINARY
W144
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF = 66.6/100 MHz CPU = 66.6/100 MHz Parameter f fD p/q tR tF tD fST Description Frequency, Actual PLL Ratio Output Rise Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) Test Condition/Comments Determined by PLL divider ratio (see p/q below) (14.31818 MHz x 57/17 = 48.008 MHz) Measured from 0.4V to 2.4V 0.5 0.5 45 Min. Typ. 48.008 +167 57/17 2 2 55 3 V/ns V/ns % ms Max. Unit MHz ppm
Deviation from 48 MHz (48.008 - 48)/48
Output Fall Edge Rate Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization.
Zo
AC Output Impedance Average value during switching transition. Used for determining series termination value.
40
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF= 66.6/100 MHz CPU = 66.6/100 MHz Parameter f fD p/q tR tF tD fST Description Frequency, Actual PLL Ratio Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Determined by PLL divider ratio (see p/q below) (14.31818 MHz x 57/34 = 24.004 MHz) 0.5 0.5 45 Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 40 Min. Typ. 24.004 +167 57/34 2 2 55 3 V/ns V/ns % ms Max. Unit MHz ppm
Deviation from 24 MHz (24.004 - 24)/24 Output Rise Edge Rate Measured from 0.4V to 2.4V
Zo
Ordering Information
Ordering Code W144 Document #: 38-00791 Package Name H Package Type 48-Pin SSOP (300-mil)
13
PRELIMINARY
Package Diagram
48-Pin Shrink Small Outline Package (SSOP, 300 mils)
W144
Summary of nominal dimensions in inches: Body Width: 0.296 Lead Pitch: 0.025 Body Length: 0.625 Body Height: 0.102
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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