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1CY 621 28
fax id: 1072
PRELIMINARY
CY62128
128K x 8 Static RAM
Features
* 4.5V - 5.5V operation * CMOS for optimum speed/power * Low active power (70 ns, LL version) -- 330 mW (max.) (60 mA) * Low standby power (70 ns, LL version) -- 110 W (max.) (20 A) * Automatic power-down when deselected * TTL-compatible inputs and outputs * Easy memory expansion with CE1, CE2, and OE options feature that reduces power consumption by more than 75% when deselected. Writing to the device is accomplished by taking chip enable one (CE1) and write enable (WE) inputs LOW and chip enable two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking chip enable one (CE1) and output enable (OE) LOW while forcing write enable (WE) and chip enable two (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). The CY62128 is available in a standard 400-mil-wide SOJ, 525-mil wide (450-mil-wide body width) SOIC and 32-pin TSOP type I.
Functional Description
The CY62128 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), an active LOW output enable (OE), and three-state drivers. This device has an automatic power-down
Logic Block Diagram
Pin Configurations
Top View SOJ / SOIC
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3
I/O0
INPUT BUFFER
A0 A1 A2 A3 A4 A5 A6 A7 A8
I/O1 I/O2
512 x 256 x 8 ARRAY
I/O3 I/O4 I/O5
POWER DOWN A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CE1 CE2 WE OE
COLUMN DECODER
I/O6 I/O7
62128-1
TSOP I Top View (not to scale)
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 62128-2
OE A10 CE1 I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 GND I/O 2 I/O 1 I/O 0 A0 A1 A2 A3
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
* CA 95134 * 408-943-2600 July 1996 - Revised November 1996
PRELIMINARY
Selection Guide
CY62128-55 Maximum Access Time (ns) Maximum Operating Current Commercial L LL Maximum CMOS Standby Current Commercial L LL 55 115 mA 70 mA 70 mA 10 mA 100 A 20 A
CY62128
CY62128-70 70 110 mA 60 mA 60 mA 10 mA 100 A 20 A
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND[1] .... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] .....................................-0.5V to VCC +0.5V DC Input Voltage[1]..................................-0.5V to VCC +0.5V
Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA
Operating Range
Range Commercial Ambient Temperature[2] 0C to +70C VCC 5V 10%
Electrical Characteristics Over the Operating Range[3]
62128-55 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current Output Short Circuit Current[4] VCC Operating Supply Current GND VI VCC GND VI VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE1 VIH or CE2 < VIL, VIN VIH or VIN VIL, f = fMAX Max. VCC, CE1 VCC - 0.3V, or CE2 0.3V, VIN VCC - 0.3V, or VIN 0.3V, f=0 Com'l L LL ISB1 Automatic CE Power-Down Current -- TTL Inputs Automatic CE Power-Down Current -- CMOS Inputs Com'l L LL Com'l L LL Test Conditions VCC = Min., IOH = - 1.0 mA VCC = Min., IOL = 2.1mA 2.2 -0.3 -1 -5 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +5 -300 115 70 70 25 10 2 10 100 20 2.2 -0.3 -1 -5 Max. 62128-70 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +5 -300 110 60 60 25 10 2 10 100 20 Max. Unit V V V V A A mA mA mA mA mA mA mA mA A A
ISB2
Shaded areas contain advance information Notes: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. TA is the "instant on" case temperature. 3. See the last page of this specification for Group A subgroup testing information. 4. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
2
PRELIMINARY
Capacitance[5]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 9 9
CY62128
Unit pF pF
AC Test Loads and Waveforms
5V OUTPUT 100 pF INCLUDING JIG AND SCOPE (a) Equivalent to: R1 1800 R1 1800 5V OUTPUT R2 990 5 pF INCLUDING JIG AND SCOPE (b) R2 990 GND 5ns 3.0V 90% 10% 90% 10% 5 ns ALL INPUT PULSES
62128-3 62128-4
THEVENIN EQUIVALENT 639 1.77V OUTPUT
Switching Characteristics[3,6] Over the Operating Range
62128-55 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD WRITE tWC tSCE tAW tHA tSA tPWE tSD Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW to Data Valid, CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z[7, 8] Z[8] Z[7, 8] 0 55 55 45 45 0 0 45 45 70 60 60 0 0 50 55 5 20 0 70 CE1 LOW to Low Z, CE2 HIGH to Low 0 20 5 25 5 55 20 0 25 55 55 5 70 35 70 70 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. 62128-70 Min. Max. Unit
CE1 HIGH to High Z, CE2 LOW to High
CE1 LOW to Power-Up, CE2 HIGH to Power-Up CE1 HIGH to Power-Down, CE2 LOW to Power-Down CYCLE[9] Write Cycle Time CE1 LOW to Write End, CE2 HIGH to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End
Shaded areas contain advance information Notes: 5. Tested initially and after any design or process changes that may affect these parameters. 6. Test conditions assume signal transition time of 5ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 100pF load capacitance. 7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
3
PRELIMINARY
Switching Characteristics[3,6] Over the Operating Range (continued)
62128-55 Parameter tHD tLZWE tHZWE WE HIGH to Low Z[8] Description Data Hold from Write End WE LOW to High Z[7,8] Min. 0 5 20 Max.
CY62128
62128-70 Min. 0 5 25 Max. Unit ns ns ns
Shaded area contains advanced information.
Switching Waveforms
Read Cycle No.1[10,11]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
62128-5
Read Cycle No. 2 (OE Controlled)[11,12]
ADDRESS tRC CE1 CE2 tACE OE tHZOE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% tHZCE DATA VALID tPD 50% ISB
62128-6
HIGH IMPEDANCE
ICC
Notes: 10. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
4
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 1 (CE1 or CE2 Controlled)[13,14]
tWC ADDRESS tSCE CE1 tSA CE2 tSCE tAW tPWE WE tSD DATA I/O DATA VALID tHD tHA
CY62128
62128-7
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13,14]
tWC ADDRESS tSCE CE1
CE2 tSCE tAW tSA WE tPWE tHA
OE tSD DATA I/O NOTE 15 tHZOE
Notes: 13. Data I/O is high impedance if OE = VIH. 14. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state. 15. During this period the I/Os are in the output state and input signals should not be applied.
tHD
DATAIN VALID
62128-8
5
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No.3 (WE Controlled, OE LOW)[13,14]
tWC ADDRESS tSCE CE1
CY62128
CE2 tSCE tAW tSA WE tSD DATAI/O NOTE 15 tHZWE DATA VALID tLZWE
62128-9
tHA tPWE
tHD
Truth Table
CE1 H X L L L CE2 X L H H H OE X X L X H WE X X H L H I/O0 - I/O7 High Z High Z Data Out Data In High Z Mode Power-Down Power-Down Read Write Selected, Outputs Disabled Power Standby (I SB) Standby (I SB) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 55 Ordering Code CY62128-55VC CY62128-55SC CY62128-55ZC 70 CY62128-70VC CY62128-70SC CY62128-70ZC CY62128L-70SC CY62128L-70ZC CY62128LL-70SC CY62128LL-70ZC
Shaded area contains advanced information.
Package Name V33 S34 Z32 V33 S34 Z32 S34 Z32 S34 Z32
Package Type 32-Lead (400-Mil) Molded SOJ 32-Lead (450-Mil) Molded SOIC 32-Lead TSOP TypeI 32-Lead (400-Mil) Molded SOJ 32-Lead (450-Mil) Molded SOIC 32-Lead TSOP Type I 32-Lead (450-Mil) Molded SOIC 32-Lead TSOP Type I 32-Lead (450-Mil) Molded SOIC 32-Lead TSOP Type I
Operating Range Commercial
Commercial
Document #: 38-00524
6
PRELIMINARY
Package Diagrams
32-Lead (450 Mil) Molded SOIC S34
CY62128
32-Lead Thin Small Outline Package Z32
7
PRELIMINARY
Package Diagrams (continued)
32-Lead (400-Mil) Molded SOJ V33
CY62128
(c) Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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