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| Data Sheet, DS3, June 2001 TE3-MUX M13 Multiplexer and DS3 Framer PE B 3 4 4 5 E V 2 . 1 Datacom Never stop thinking. Edition 2001-06-29 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany (c) Infineon Technologies AG 7/26/01. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Data Sheet, DS3, June 2001 TE3-MUX M13 Multiplexer and DS3 Framer PE B 3 4 4 5 E V 2 . 1 Datacom Never stop thinking. PEB 3445 E Revision History: Previous Version: Page 21 55 64f., 66f. 185ff., 188ff. 84, 139 91, 101, 113, 118, 127, 151, 154 167, 179 2001-06-29 Preliminary Data Sheet 09.2000 DS3 Subjects (major changes since last revision) Changed document to new documentation guidelines. Recommendation for demultiplexed bus operation added to signal LALE. Added table content which was missing in previous version. Figure 16, Figure 17, Figure 18, Figure 19 corrected. LBHE respectively LBLE were wrong in previous version. Timings of LBHE in Figure 24 and Figure 25 redrawn. Figure 27 added. Merged timings for LA and LBHE. Timings of LBLE in Figure 28 and Figure 29 redrawn. Figure 31 added. Merged timings of LA and LBLE. Description of register bits SIDLE, SAISA, RDC extended. Description of register bits OD, XBIT, GN, RES, T1E1 corrected. Major parts of register description (FHND and PHND) rewritten. Register FHND: Bits ABORT and XTF removed. Register PHND: Bit XTF removed. Removed register bit XRA. Section 'DMA Interface Signals' added. RTD is updated with rising edge of RTC. This is corrected in Figure 49. Some minor documentation updates (wording, syntax, ...). Name change M13FX -> TE3-MUX. Removed PEF version. Corrected Table 27 "DS1/E1 Receive Data Timing" on Page 202. Changed figure 25 and 27. Removed timing 35. Changed timings 101,111,151,152,195,198. Changed table 11. Changed FEAC FHND register to contain XTF bit. 177 191 204 For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com PEB 3445 E 1 1.1 1.1.1 1.1.2 1.1.3 1.2 1.3 2 2.1 2.2 2.3 2.4 2.5 2.6 3 3.1 3.2 4 4.1 4.1.1 4.1.2 4.2 4.3 4.4 4.4.1 4.4.1.1 4.4.1.2 4.4.1.3 4.4.1.4 4.4.2 4.4.2.1 4.4.2.2 4.4.2.3 4.4.2.4 4.4.2.5 4.5 4.5.1 4.5.1.1 4.5.1.2 4.5.1.3 4.5.1.4 TE3-MUX Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M23 Multiplexer and DS3 Framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M12 Multiplexer and DS2 Framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Error Rate Tester . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply, Reserved Pins and No-connect Pins . . . . . . . . . . . . . . . . . 13 13 14 14 14 16 17 18 18 19 20 23 29 30 General Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Remote and Local Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Remote Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B3ZS Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tributary Mapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M12 Multiplexer/Demultiplexer and DS2 framer . . . . . . . . . . . . . . . . . . . . M12 multiplex format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loopback Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alarm Indication Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ITU-T G.747 format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parity Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Remote Alarm Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alarm Indication Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M23 multiplexer and DS3 framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M23 multiplex format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . X-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alarm Indication Signal, Idle Signal . . . . . . . . . . . . . . . . . . . . . . . . . . 5 34 34 34 34 36 37 40 40 41 41 41 42 43 43 43 44 44 44 45 45 46 46 46 47 Data Sheet 2001-06-29 PEB 3445 E 4.5.1.5 4.5.1.6 4.5.2 4.5.2.1 4.5.2.2 4.5.2.3 4.5.2.4 4.5.2.5 4.5.2.6 4.5.2.7 4.5.2.8 4.5.3 4.6 4.6.1 4.6.2 4.6.3 4.6.3.1 4.6.3.2 4.7 4.8 5 5.1 5.1.1 5.1.2 5.2 5.2.1 5.2.2 5.2.2.1 5.2.2.2 5.3 6 6.1 6.2 7 7.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 Loss of Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performance Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-bit parity format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . X-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Far End Alarm and Control Channel . . . . . . . . . . . . . . . . . . . . . . . . . Loopback Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alarm Indication Signal, Idle Signal . . . . . . . . . . . . . . . . . . . . . . . . . . Loss of Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performance Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Full Payload Rate Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signalling Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-bit Parity Path Maintenance Data Link Channel . . . . . . . . . . . . . . . . Far End Alarm And Control Channel (BOM) . . . . . . . . . . . . . . . . . . . . . Signalling controller FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Driven Microprocessor Operation . . . . . . . . . . . . . . . . . . . . DMA Supported Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . Test Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Motorola Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS3 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS1/E1 Interface/DS3 System Interface . . . . . . . . . . . . . . . . . . . . . . . . DS1/E1 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS3 System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 47 48 49 49 49 50 50 50 51 51 52 53 53 53 54 55 58 60 62 63 63 63 65 67 67 69 69 69 70 Reset and Initialization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Chip Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Mode Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 DS3 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 DS2 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Test Unit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Test Unit Framer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Far End Alarm and Control Channel (BOM) Registers . . . . . . . . . . . . 160 6 2001-06-29 Data Sheet PEB 3445 E 7.2.6 8 8.1 8.2 8.3 8.4 8.4.1 8.4.1.1 8.4.1.2 8.4.2 8.4.2.1 8.4.2.2 8.4.3 8.4.3.1 8.4.3.2 8.4.3.3 8.4.3.4 8.4.3.5 8.4.4 8.4.5 9 C-Bit Path Maintenance (HDLC) Registers . . . . . . . . . . . . . . . . . . . . . 171 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Important Electrical Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Microprocessor Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . Intel Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Motorola Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS3 Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overhead Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stuff Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS1/E1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS3 System Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 182 182 183 184 185 185 188 191 191 192 193 193 196 198 199 203 205 206 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Data Sheet 7 2001-06-29 PEB 3445 E Data Sheet 8 2001-06-29 PEB 3445 E List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Data Sheet Page Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Typical DS3 Channelized Application . . . . . . . . . . . . . . . . . . . . . . . . . 17 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Local Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Remote Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Tributary Mapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Tributary Mapper (Transmit Direction) . . . . . . . . . . . . . . . . . . . . . . . . . 38 Tributary Mapper (Receive Direction) . . . . . . . . . . . . . . . . . . . . . . . . . 39 Interrupt Driven Reception Sequence Example (32-byte Receive Threshold) 56 Interrupt Driven Transmit Sequence Example . . . . . . . . . . . . . . . . . . . 57 DMA Supported Receive Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 58 DMA supported Transmit Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Test Unit Access Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Pattern Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Intel Bus Mode (Demultiplexed Bus Operation) . . . . . . . . . . . . . . . . . . 64 Intel Bus Mode (Multiplexed Bus Operation) . . . . . . . . . . . . . . . . . . . . 64 Motorola Bus Mode (Demultiplexed Bus Operation) . . . . . . . . . . . . . . 66 Motorola Bus Mode (Multiplexed Bus Operation) . . . . . . . . . . . . . . . . 66 Receive Overhead Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Transmit Overhead Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Block Diagram of Test Access Port and Boundary Scan Unit . . . . . . . 70 Input/Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . 184 Intel Demultiplexed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Intel Multiplexed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Read, Write Control Interval in Demultiplexed Bus Mode . . . . . . . . . 187 Read, Write Control Interval in Multiplexed Bus Mode . . . . . . . . . . . 187 Motorola Demultiplexed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . 188 Motorola Multiplexed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Read, Write Control Interval in Demultiplexed Bus Mode . . . . . . . . . 190 Read, Write, ALE Control Interval in Multiplexed Bus Mode . . . . . . . 190 DMA Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 DMA Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 DS3 Transmit Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 DS3 Transmit Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 DS3 Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 DS3 Transmit Overhead Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 DS3 Transmit Overhead Synchronization Timing . . . . . . . . . . . . . . . 196 DS3 Receive Overhead Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 DS3 Transmit Stuff Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 9 2001-06-29 PEB 3445 E Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 DS3 Receive Stuff Bit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS1/E1 Transmit Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS1/E1 Transmit Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS1/E1 Receive Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS1/E1 Receive Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS3 System Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS3 System Transmit Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . DS3 System Receive Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 199 200 201 202 203 203 204 205 206 Data Sheet 10 2001-06-29 PEB 3445 E List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Page M12 multiplex format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 ITU-T G.747 format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 M23 multiplex format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 C-bit parity format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Data Bus Access 16-bit Intel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Data Bus Access 16-bit Motorola Mode. . . . . . . . . . . . . . . . . . . . . . . . 65 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Far End Alarm and Control Transmit Commands . . . . . . . . . . . . . . . 169 Path Maintenance Transmit Commands . . . . . . . . . . . . . . . . . . . . . . 180 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Intel Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Motorola Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 DMA Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 DMA Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 DS3 Transmit Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 DS3 Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 DS3 Transmit Overhead Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 DS3 Receive Overhead Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 DS3 Transmit Stuff Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 DS3 Receive Stuff Bit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 DS1/E1 Transmit Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 DS1/E1 Transmit Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 DS1/E1 Receive Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 DS1/E1 Receive Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 DS3 System Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 DS3 System Transmit Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 203 DS3 System Receive Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 204 JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Data Sheet 11 2001-06-29 PEB 3445 E Data Sheet 12 2001-06-29 M13 Multiplexer and DS3 Framer TE3-MUX PEB 3445 E V2.1 1 TE3-MUX Overview The TE3-MUX integrates a DS3 framer, with a M13 multiplexer, a tributary interchanger/ line selector and 32 serial line interfaces for DS1/E1/J1 lines with 4:28 line protection capability. It is an economical solution for applications, which require DS3 framing but no DS1/E1 framers. This is often required in a Central office where DS1/E1 from different equipment are multiplexed in a card. The TE3-MUX allows the DS1/E1 to be aggregated into DS3 without investing in the framers. Line and remote loopback capabilities can be used to trouble shoot in case of broken connections and other failures. The use of standard line interfaces to interconnect office equipment is called Office Repeater Bay (ORB) compliance. 1.1 General Features * Integrates a M13 multiplexer and a DS3 framer operating in M13 or C-bit parity mode * Optionally the M13 multiplexer can be disabled, which provides an integrated solution for combined channelized/unchannelized DS3 applications * Provides 32 tributary interfaces where each interface can be switched to any of the 28DS1/21E1 tributaries of the DS3 signal * Integrates a bit error rate tester * Integrates a 16-/8-bit switchable Intel or Motorola style microprocessor interface which operates in multiplexed or demultiplexed bus mode * JTAG boundary scan according to IEEE1149.1 (5 pins). * 0.25 m, 2.5V low power core technology * I/Os are 3.3V tolerant and have 3.3V driving capability * Package P-BGA-272-1 (27mm x 27mm; pitch 1.27mm) * Full scan path and BIST of on-chip RAMs for production test * Power consumption: 340mW (typical) * Temperature range -40..+85C Data Sheet 13 2001-06-29 PEB 3445 E TE3-MUX Overview 1.1.1 M23 Multiplexer and DS3 Framer * Multiplexing/demultiplexing of seven DS2 into/from M13 asynchronous format according to ANSI T1.107, ANSI T1.107a * Multiplexing/demultiplexing of seven DS2 into/from C-bit parity format according to ANSI T1.107, ITU-T G.704 * DS3 framing according to ANSI T1.107, T1.107a, ITU-T G.704 * Support of B3ZS encoded signals * Provides access to the DS3 overhead bits and the DS3 stuffing bits via a serial clock and data interface (overhead interface) * Insertion and Extraction of alarms according to ANSI T1.404 (remote alarm, AIS, far end receive failure) * Supports HDLC (Path Maintenance Data Link) and bit oriented message mode (Far End Alarm and Control Channel) in C-bit parity mode. An integrated signalling controller provides 2x32 byte deep FIFO's for each direction of both channels. * Detection of AIS and idle signal in presence of BER 10-3 * Detection of excessive zeroes and LOS * Alarm and performance monitoring with 16-bit counters for line code violations, excessive zeroes, parity error (P-bit), framing errors (F-bit errors with or without M-bit errors, far end block error (FEBE-bit) and CP-bit errors. * Automatic insertion of severely errored frame and AIS defect indication 1.1.2 M12 Multiplexer and DS2 Framer * Multiplexing/Demultiplexing of four asynchronous DS1 bit streams into/from M13 asynchronous format * Multiplexing/Demultiplexing of 3 E1 signals into/from ITU G.747 compliant DS2 signal. * DS2 line loopback detection/generation * Framing according to ANSI T1.107, T1.107a or ITU-T G.747 * Insertion and extraction of X-bit * Insertion and Extraction of alarms (remote alarm, AIS) * Detection of AIS in presence of BER 10-3 * Alarm and performance monitoring (framing bit errors, parity errors) * Reframe time below 7ms (TR-TSY-000009) for DS2 format and below 1 ms for ITU G.747 format * Bit Stuffing/Destuffing in M12 multiplex format or C-bit parity format * Insertion of AIS in lieu of low speed tributaries 1.1.3 Bit Error Rate Tester * User specified PRBS or Fixed Pattern with programmable length of 2 to 32 bits and programmable feedback tap (PRBS only) * Optional Bit Inversion * Two error insertion modes: Single or programmable bit rates Data Sheet 14 2001-06-29 PEB 3445 E TE3-MUX Overview * * * * * Optional zero suppression 32-bit counters for errors and received bits Programmable bit intervals for receive measurements Framed DS3, framed/unframed DS2 or framed/unframed DS1/E1 error insertion Additional framing error counters for DS1/E1 error insertion Data Sheet 15 2001-06-29 PEB 3445 E TE3-MUX Overview 1.2 * Logic Symbol Transmit Overhead Interface Receive Overhead Interface ROVHCK ROVHD ROVHSYN RSBD RSBCK Transmit Line Interface Receive Line Interface TCLKO44 TCLK44 TD44P TD44N RCLK44 RD44P RD44N TOVHD TOVHDEN TOVHSYN TSBD TSBCK TOVHCK TTC(1) TTC(32:1) TTD(32:1) Transmit Tributary Interface Receive Tributary Interface RTC(32:1) TE3-MUX PEB 3445 E RTD(32:1) SCANEN TDI TDO TMS TCK TRST RST VDD3 V DD25 VSS JTAG LCS LWR/LRDWR LRD/LDS LBHE/LBLE LALE DBW IM LINT DRR RMC LD(15:0) LA(7:0) Microprocessor interface DMA Support Figure 1 Logic Symbol Data Sheet 16 DRT TXME 2001-06-29 PEB 3445 E TE3-MUX Overview 1.3 Typical Applications Typical applications for the TE3-MUX support of channelized DS3 with serial line interfaces on the low speed side. The system partitioning due to ORB compliance may allow usage in following systems: * * * * * Terminal Multiplexers with DS1/E1 and HDSL interfaces Add Drop Multiplexers (ADM) with DS1/E1 and HDSL interfaces Digital Cross Connect devices with DS1/E1 and HDSL interfaces DLC COT and RT Channelized DS3 applications The TE3-MUX supports 32 low speed serial interfaces. These interfaces can be mapped to any of the 28 DS3 tributaries which provides for 4:28 protection. * DS1 digital QuadLIUTM #1 PEB22504 DS1 #1 analog DS3 analog TE3-LIUTM PEB3452 DS3 digital TE3-MUX PEB3445 QuadLIUTM #7 PEB22504 DS1 #28 analog Figure 2 Typical DS3 Channelized Application Data Sheet 17 2001-06-29 PEB 3445 E Pin Description 2 2.1 Pin Description Pin Diagram (top view) 20 Y NC23 19 RTD(25) 18 VDD25 17 TTD(24) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 NC22 TTD(23) RTC(22) TTC(22) RTC(21) RTC(20) RTC(19) TTD(19) RTD(18) RTD(17) TTC(17) TTD(16) RTC(15) RTD(14) RTC(14) RTC(13) W V U T R P N M L K J H G F E D C B A RTC(26) TTD(26) RTC(25) RTD(24) TTC(24) TTC(23) TTD(22) RTD(21) RTD(20) RTD(19) VDD25 RTC(18) RTC(17) RTD(16) TTC(16) TTD(15) RTD(13) TTD(13) NC21 TTC(13) RTD(27) RTD(26) TTC(26) TTD(25) RTC(24) RTD(23) RTD(22) VDD25 TTC(21) TTC(20) TTC(19) TTD(18) TTD(17) RTC(16) RTD(15) TTC(15) TTC(14) NC20 VDD25 TTD(12) VDD25 TTC(27) TTD(27) VSS TTC(25) VDD33 RTC(23) VSS TTD(21) TTD(20) VDD33 TTC(18) VSS VDD25 VDD33 TTD(14) VSS RTD(12) TTC(12) RTC(11) RTC(28) TTD(28) TTC(28) RTC(27) RTC(12) RTD(11) TTD(11) RTC(10) RTC(29) TTD(29) RTD(28) VDD33 TTD(30) TTC(30) RTD(29) TTC(29) TE3-MUX PEB 3445 E VDD33 TTC(11) TTD(10) VDD25 RTD(10) TTC(10) RTD(9) RTC(9) VDD25 RTD(30) RTC(30) VSS VSS TTD(9) TTC(9) RTD(8) RTD(31) RTC(31) TTD(31) TTC(31) VSS VSS VSS VSS RTC(8) TTD(8) TTC(8) RTD(7) RTC(32) TTC(32) TTD(32) VDD33 VSS VSS VSS VSS RTC(7) TTD(7) TTC(7) VDD25 RTD(32) RMC TXME VDD25 VSS VSS VSS VSS VDD33 RTC(6) TTD(6) RTD(6) LINT DRT DRR IM VSS VSS VSS VSS TTD(5) RTC(5) RTD(5) TTC(6) DBW LCS LRD LDS VSS VSS RTC(4) RTD(4) TTC(5) LWR LRDWR LBHE LBLE VDD25 LA(1) TTD(3) VDD25 TTC(4) TTD(4) LALE NC19 LA(2) VDD33 VDD33 TTC(3) RTC(3) RTD(3) LA(0) LA(3) LA(4) LA(7) RTC(1) TTD(2) RTC(2) RTD(2) NC18 LA(5) VDD25 VSS RST VDD33 LD(4) VSS NC17 VDD33 NC16 VDD25 VSS SCANEN VDD33 TSBCK VSS TTD(1) TTC(1) TTC(2) LA(6) NC15 NC14 TCK LD(1) NC13 LD(7) LD(9) LD(12) VDD25 TCLKO44 RCLK44 NC12 NC11 VDD25 TOVHDEN ROVHCK RSBCK VDD25 RTD(1) NC10 TDI TMS TRST LD(2) LD(5) VDD25 LD(10) LD(13) LD(15) TCLK44 RD44N NC9 NC8 NC7 TOVHCK TOVHSYN ROVHD ROVHSYN NC6 NC5 TDO VDD25 LD(0) LD(3) LD(6) LD(8) LD(11) LD(14) TD44 TD44P TD44N RD44 RD44P NC4 NC3 NC2 NC1 TOVHD TSBD RSBD VSS Figure 3 Pin Configuration Data Sheet 18 2001-06-29 PEB 3445 E Pin Description 2.2 Pin Definitions and Functions Signal Type Definitions: I O I/O o/d Input is a standard input- only signal. Totem Pole Output is a standard active driver. I/O is a bidirectional, tri-state input/output pin. Open Drain allows multiple devices to share a line as a wire-OR. A pullup is required to sustain the inactive state until another agent drives it, and must be provided by the central resource. No-connect Pin n Such pins are not bonded with the silicon. Although any potential at these pins will not impact the device it is recommended to leave them unconnected. No-connect pins might be used for additional functionality in later versions of the device. Leaving them unconnected will guarantee hardware compatibility to later device versions. Reserved Reserved pins are for vendor specific use only and should be connected as recommended to guarantee normal operation. Signal Name Conventions: NCn Note: The signal type definition specifies the functional usage of a pin. This does not reflect necessarily the implementation of a pin, e.g. a pin defined of signal type `Input' may be implemented with a bidirectional pad. Data Sheet 19 2001-06-29 PEB 3445 E Pin Description 2.3 * Local Microprocessor Interface Pin No. Symbol RST IM Input (I) Output (O) I I Reset Intel/Motorola By connecting this pin to either VSS or VDD3 the bus interface can be adapted to either Intel or Motorola environment. IM = VSS selects Intel bus mode. IM = VDD3 selects Motorola bus mode. Data Bus Width DBW = VSS selects 8-bit bus mode. DBW = VDD3 selects 16-bit bus mode. Address bus These input address lines select one of the internal registers for read or write access. Data Bus Bidirectional three-state data lines which interface with the system's data bus. Their configuration is controlled by the level of pin DBW: * 8-bit mode (DBW = 0): LD(7:0) are active. LD(15:8) are in high impedance and have to be connected to VDD3 or VSS. * 16-bit mode (DBW = 1): LD(15:0) are active. In case of byte transfers, the active half of the bus is determined by LA(0) and LBHE/LBLE and the selected bus interface mode (IM). The unused half is in high impedance. For detailed information, refer to Chapter 5.1. Chip Select This active low signal selects the TE3MUX for read/write operations. Function D16 J17 H20 DBW I E17, C20, D19, LA(7:0) E18, E19, F18, G17, E20 B11, A12, B12, LD(15:0) C12, A13, B13, C13, A14, C14, A15, B15, D14, A16, B16, C16, A17 I I/O H19 LCS I Data Sheet 20 2001-06-29 PEB 3445 E Pin Description Pin No. F20 Symbol LALE Input (I) Output (O) I Function Address Latch Enable The address information provided on address lines LA(7:0) is internally latched with the falling edge of LALE. This function allows the TE3-MUX to be directly connected to a multiplexed address/data bus. In this case, pins LA(7:0) must be externally connected to the data bus pins. When the TE3-MUX is operated in demultiplexed bus mode LALE shall be connected to VDD3. Read (Intel Bus Mode) This active low signal selects a read transaction. Data strobe (Motorola Bus Mode) This active low signal indicates that valid data has to be placed on the data bus (read cycle) or that valid data has been placed on the data bus (write cycle). Write Enable (Intel Bus Mode) This active low signal selects a write cycle. Read Write Signal (Motorola Bus Mode) This input signal distinguishes write from read operations. Interrupt Request This line indicates general interrupt requests of the TE3-MUX. The interrupt sources can be masked via registers. H18 LRD or LDS I I G20 LWR or LRDWR I I J20 LINT od Data Sheet 21 2001-06-29 PEB 3445 E Pin Description Pin No. G19 Symbol LBHE Input (I) Output (O) I Function Byte High Enable (Intel Bus Mode) If 16-bit bus interface mode is enabled, this signal indicates a data transfer on the upper byte LD(15:8) of the data bus. In 8-bit bus interface mode this signal has no function and should be tied to VDD3. Refer to Chapter 5.1 for detailed information. Byte Access (Motorola Bus Mode) If 16-bit bus interface mode is enabled, this signal indicates a data transfer on the lower byte LD(7:0) of the data bus. In 8-bit bus interface mode this signal has no function and should be tied to VDD3. Refer to Chapter 5.1 for detailed information. Data Request Receive This signal indicates that the receive FIFO of the path maintenance data link channel contains a byte which has to be read by an external CPU. Receive Message Complete This signal indicates that the DMA controller has to read the port status register PPSR in order to release the receive FIFO. Data Request Transmit This signal indicates a request to store a new byte in the transmit FIFO of the path maintenance data link channel. Transmit Message End This signal in combination with DRT indicates that the byte written to the transmit FIFO is the last byte of a HDLC message. TXME has to asserted together with the data signal LD. or LBLE I J18 DRR O K19 RMC O J19 DRT O K18 TXME I Data Sheet 22 2001-06-29 PEB 3445 E Pin Description 2.4 * Serial Interface Symbol Input (I) Function Output (O) I DS3 Transmit Clock Input This clock provides a reference clock for the DS3 interface. The frequency of this clock is nominally 44.736 MHz. DS3 Transmit Clock Output This output is a buffered version of the selected transmit clock. In normal operation mode TCLKO44 is a buffered version of TCLK44. In looped timed mode TCLKO44 is a buffered version of RCLK44. DS3 Transmit Data This unipolar serial data output represents the DS3 signal. TD44 can be updated on the falling or the rising edge of TCLKO44. DS3 Transmit Positive Pulse In dual-rail mode this pin represents the positive pulse of the B3ZS encoded DS3 signal. TD44P can be updated on the falling edge or rising edge of TCLKO44. DS3 Transmit Negative Pulse In dual-rail mode this pin represents the negative pulse of the B3ZS encoded DS3 signal. TD44N can be updated on the falling or rising edge of TCLKO44. DS3 Receive Clock Input This pin provides the receive clock input . The frequency of this clock is nominally 44.736 MHz. Pin No. DS3 Serial Interface Signals B10 TCLK44 C10 TCLKO44 O A11 TD44 O or TD44P O A10 TD44N O C9 RCLK44 I Data Sheet 23 2001-06-29 PEB 3445 E Pin Description Pin No. A9 Symbol RD44 or RD44P I Input (I) Function Output (O) I DS3 Receive Data This unipolar serial data input represents the DS3 signal. RD44 can be sampled on the falling or rising edge of RCLK44. DS3 Receive Positive Pulse In dual-rail mode this pin represents the positive pulse of the B3ZS encoded DS3 signal. RD44P can be sampled on the falling or rising edge of RCLK44. DS3 Receive Negative Pulse In dual-rail mode this pin represents the negative pulse of the B3ZS encoded DS3 signal. RD44N can be sampled on the falling or rising edge of RCLK44. Transmit Overhead Bit Clock This signal provides the bit clock for the DS3 overhead bits of the outgoing DS3 frame. TOVHCK is nominally a 526 kHz clock. Transmit Overhead Data The overhead bits to be placed in the outgoing DS3 frame can be provided via TOVHD. Transmit overhead data is sampled on the rising edge of TOVHCK and those bits marked by TOVHDEN are inserted in the overhead bit positions of the outgoing DS3 frame. Transmit Overhead Data Enable The asserted TOVHDEN signal marks the bits to be inserted in the DS3 frame. TOVHDEN is sampled together with TOVHD on the rising edge of TOVHD. B9 RD44N I DS3 Overhead Interface B5 TOVHCK O A4 TOVHD I C5 TOVHDEN I Data Sheet 24 2001-06-29 PEB 3445 E Pin Description Pin No. B4 Symbol TOVHSYN Input (I) Function Output (O) I/O Transmit Overhead Synchronization TOVHSYN provides the means to align TOVHD to the first M-frame of the DS3 signal or to align the first M-frame to TOVHSYN. * If operated in output mode TOVHSYN is asserted when the X-bit of the 1st subframe of the DS3 multiframe has to be inserted via TOVHD. TOVHSYN is updated on the falling edge of TOVHCK. * If operated in input mode TOVHSYN must be asserted when the X-bit of the 1st M-frame of the DS3 signal is output on TD44. TOVHSYN is sampled on the rising edge of TCLKO44. Transmit Stuff Bit Clock This signal provides the bit clock for DS3 transmit stuff bit data. Transmit Stuff Bit Data Data provided via TSBD is optionally inserted in the stuffed bit positions of the DS3 signal. TSBD is sampled on the rising edge of TSBCK. This function is available in M13 asynchronous format only. Receive Overhead Bit Clock This signal provides the bit clock for the received DS3 overhead bits. ROVHCK is nominally a 526 kHz clock. Receive Overhead Data ROVHD contains the extracted overhead bits of the DS3 frame. It is updated on the falling edge of ROVHCK. D5 TSBCK O A3 TSBD I C4 ROVHCK O B3 ROVHD O Data Sheet 25 2001-06-29 PEB 3445 E Pin Description Pin No. B2 Symbol ROVHSYN Input (I) Function Output (O) O Receive Overhead Synchronization ROVHSYN is asserted while the X-bit of the 1st subframe of the DS3 signal is provided via ROVHD. It is updated on the falling edge of ROVHCK. Receive Stuff Bit Clock This signal provides the bit clock for DS3 receive stuff bit data. Receive Stuff Bit Data ROVHD provides data which was inserted in the stuffed bit positions of the DS3 signal. RSBD is updated on the falling edge of RSBCK. This function is available in M13 asynchronous format only. DS1/E1 Receive Clock This interface provides the receive clock for each of the low speed interfaces. Dependent on the tributary (DS1/E1) this clock has a nominal frequency of 1.544 MHz or 2.048 MHz. Due to the destuffing and demultiplexing process the receive clock contains gaps. C3 RSBCK O A2 RSBD O DS1/E1 Interface Signals, DS3 System Interface Signals L20, M19, N18, RTC(32:1) R20, T20, T17, W20, W18, V16, U14, Y15, Y13, Y12, Y11, W9, W8, V7, Y5, Y3, Y2, T4, U1, T1, P1, M4, L4, K3, J3, H3, F2, E2, E4 or E4 RTC(1) O O DS3 Receive Clock When the TE3-MUX is operated in unchannelized mode (DS3 framer mode) this interface provides the DS3 receive payload clock. It is derived from the receive clock RCLK44 and has clock gaps on the DS3 bit positions containing the overhead bits. Data Sheet 26 2001-06-29 PEB 3445 E Pin Description Pin No. Symbol Input (I) Function Output (O) O DS1/E1 Receive Data The data stream of the DS1/E1 tributary is directly feeded to this output. RTD(x) is updated on the rising or falling edge of RTC(x). K20, M20, N19, RTD(32:1) P18, R18, V20, V19, Y19, W17, V15, V14, W13, W12, W11, Y9, Y8, W7, V6, Y4, W4, U3, T3, P4, P2, N1, M1, K1, J2, H2, F1, E1, C1 or C1 RTD(1) O DS3 Receive Data When the TE3-MUX is operated in unchannelized mode (DS3 framer mode) the payload of the incoming DS3 signal is output on RTD(1). RTD(1) is updated on the falling edge of RTC(1). Data Sheet 27 2001-06-29 PEB 3445 E Pin Description Pin No. Symbol Input (I) Function Output (O) I DS1/E1 Transmit Clock Transmit data is sampled on the rising edge of TTC(x) and inserted into the assigned DS1/E1 tributary of the DS3 signal. Dependent on the tributary type TTC(x) has a clock frequency of 1.544 MHz or 2.048 MHz. L19, M17, P19 , TTC(32:1) P17, T18, U19, V18, U16, W16, W15, Y14, V12, V11, V10, U9, Y7, W6, V5, V4, W1, U2, R3, P3, N2, M2, L2, J1, H1, G2, F3, or D1, D2 D2 TTC(1) O DS3 Transmit Clock When the TE3-MUX is operated in unchannelized mode (DS3 framer mode) this interface provides the DS3 transmit payload clock. It is derived from the transmit clock TCLKO44 and has clock gaps on the DS3 bit positions containing the overhead bits. DS1/E1 Transmit Data TTD(x) provides the DS1/E1 data stream to be inserted in the assigned DS1/E1 tributary of the DS3 signal. TTD(x) can be sampled on the rising or falling edge of TTC(x). L18, M18, P20, TTD(32:1) R19, T19, U18, W19, V17, Y17, Y16, W14, U12, U11, Y10, V9, V8, Y6, W5, U5, W3, V1, T2, R2, N3, M3, L3, K2, J4, G1, G4, E3, D3 or D3 TTD(1) I I DS3 Transmit Data When the TE3-MUX is operated in unchannelized mode (DS3 framer mode) the payload of the outgoing DS3 signal needs to be provided via TTD(1). TTD(1) is sampled on the rising edge of TTC(1) Data Sheet 28 2001-06-29 PEB 3445 E Pin Description 2.5 * Test interface Symbol TCK Input (I) Function Output (O) I JTAG Test Clock This pin is connected with an internal pullup resistor. JTAG Test Mode Select This pin is connected with an internal pullup resistor. JTAG Test Data Input This pin is connected with an internal pullup resistor. JTAG Test Data Output JTAG Test Reset This pin is connected with an internal pullup resistor. Full Scan Path Test Enable When connected to VDD3 the TE3-MUX works in a vendor specific test mode. It is recommended to connect this pin to VSS. Pin No. C17 B18 TMS I B19 TDI I A19 B17 TDO TRST O I D7 SCANEN I Data Sheet 29 2001-06-29 PEB 3445 E Pin Description 2.6 * Power Supply, Reserved Pins and No-connect Pins Pin No. Symbol Input (I) Function Output (O) I Ground 0V All pins must have the same level. A1, D4, D8, VSS D13, D17, H4, H17, N4, N17, U4, U8, U13, U17, J9, J10, J11, J12, K9, K10, K11, K12, L9, L10, L11, L12, M9, M10, M11, M12 A18, B14, C2, C6, C11, D9, D18, G3, G18, K17, L1, N20, R1, U7, U20, V13, V2, W10, Y18 D6, D11, D15, F4, F17, K4, L17, R4, R17, U6, U10, U15 VDD25 I Supply Voltage 2.5V 0.25V All pins must have the same level. VDD3 I Supply Voltage 3.3V 0.3V All pins must have the same level. A5, A6, A7, A8, NC1..23 A20, B1, B6, B7, B8, B20, C7, C8, C15, C18, C19, D10, D12, D20, F19, V3, W2, Y1, Y20 No-connect Pins 1..23 It is recommended not to connect these pins. Data Sheet 30 2001-06-29 * 3 3.1 Figure 4 Remote Loop 7 1 1 4 32 7 Local/Remote Loop RC44 7 Local Loop Data Sheet TSBCK TSBD TOVHSYN TOVHDEN TOVHD TOVHCK Block Diagram General Overview Block Diagram Reset Scanlogic RST SCANEN 7 1 7 1 7 Transmit Overhead Access TC44 M23 Mux 32 1 4 TTC(1) M12 M12 Mux Mux 4 TC44O Tributary Interface TTC(32:1) TTD(32:1) TD44P Unipolar/ Bipolar Encoding DS3 Transmit Framer DS2 Transmit Framer TD44N 4 Local Loop Remote Loop 31 M23 Demux 1 4 RD44P RD44N Unipolar/ Bipolar Decoding DS3 Receive Framer DS2 DS2 Transmit Transmit Framer Framer M12 M12 Demux Demux Tributary Interface RTC(32:1) RTD(32:1) Receive Overhead Access Signalling Controller (FEAC/Path Maintenance Data Link) Microprocessor Interface 8/16-bit Intel/Motorola JTAG RMC DRR LINT IM DBW LALE TXME DRT TRST TCK TMS TDO TDI LA(7:0) LD(15:0) RSBCK RSBD LBHE/LBLE LRD/LDS LWR/LRDWR LCS ROVHSYN ROVHD ROVHCK VDD3 VDD25 VSS PEB 3445 E General Overview 2001-06-29 PEB 3445 E General Overview 3.2 Block Description 32 port line selector/tributary mapper This structure allows the user to connect any DS1/E1 signal to a specified tributary of any M12 module. Therefore it maps 32 DS1/E1 signals into 28 DS1 time slots or 21 E1 time slots of the DS3 signal. The four remaining spare ports can be used for microcontroller based protection, e.g. they can be operated in stand-by mode. They can also be used to interface an external test unit to test any DS1/E1. M12 multiplexer/demultiplexer and DS2 framer There are seven independent M12 multiplexer/demultiplexer modules in the chip. Each module can operate in either ANSI T1.107, ANSI T1.107a or ITU-T G.747 mode. In other words, a module can either map 4 DS1/J1 to one DS2 or 3 E1 to one DS2. When mapping DS1 signals into DS2 signals the M12 multiplexer performs inversion of the second and fourth DS1 signal. The DS2 framer performs frame and multi-frame alignment in receive direction and vice versa inserts the framing bits according to ANSI T1.107, ANSI T1.107a or ITU-T G.747. It detects loopback requests or enables insertion of loopback requests under microprocessor control. M23 multiplexer/demultiplexer and DS3 framer In channelized operating mode the M23 multiplexer/demultiplexer maps/demaps seven DS2 signals (generated by the M12 multiplexer/demultiplexer and DS2 framer) into/from M13 asynchronous format or C-bit parity format. In unchannelized mode one logical input stream is mapped into the information bits of the DS3 stream according to ANSI T1.107, ANSI T1.107a. The DS3 framer performs frame and multiframe alignment in receive direction and inserts the frame and multiframe alignment bits. Access to the DS3 overhead bits is provided by an additional overhead interface or via internal registers. An integrated signalling controller supports the Far End Alarm and Control Channel and the C-bit Parity Path Maintenance Data Link in DMA or interrupt mode. Performance monitoring provides counting of framing bit errors, parity errors, CP-bit errors, far end block errors, excessive zeros and line code violations. The framer detects loopback requests and allows insertion of loopbacks under microprocessor control. BERT/PRBS generator/detector The device has an integrated bit error rate tester. It is a programmable pseudo random bit sequence generator/monitor capable of supporting any smart jack loopback code from 2 to 32 bits in length and with a programmable feedback tap. The monitor can detect the incoming pattern and transmit the same pattern towards the far end of any low speed/ high speed port. Data Sheet 32 2001-06-29 PEB 3445 E General Overview The test unit also has single/multi bit error insertion for testing and diagnostics and supports framed DS3, framed/unframed DS2 and framed/unframed DS1/E1 error insertion. Data Sheet 33 2001-06-29 PEB 3445 E Functional Description 4 4.1 4.1.1 Functional Description Remote and Local Loops Local Loops Local loops are provided on DS3 and DS1 level on a per port/tributary basis. In the local loop the outgoing bit stream of a port/tributary is mirrored to the receive data path. This allows to provide data via the low speed tributaries which is processed by the TE3-MUX in transmit direction, mirrored to the respective receiver and send back to the originating source. In order to ensure that the local port loop works even without incoming receive clock, each line looped uses the corresponding transmit clock. * RCLK44 RD44P RD44N DS3 Receive Framer M23 Demux DS2 Receive Framer M12 Demux DS1/E1 Interface TCLKO44 TD44P TD44N TCLK44 DS3 Transmit Framer M23 Multiplexer DS2 Transmit Framer M12 Multiplexer DS1/E1 Interface RCLK44 RD44P RD44N DS3 Receive Framer M23 Demux DS2 Receive Framer M12 Demux DS1/E1 Interface TCLKO44 TD44P TD44N TCLK44 DS3 Transmit Framer M23 Multiplexer DS2 Transmit Framer M12 Multiplexer DS1/E1 Interface Figure 5 Local Loops 4.1.2 Remote Loops The TE3-MUX supports remote loops in different stages of the M13 data path. In DS3 line loopback mode the incoming DS3 signal is mirrored and placed on the DS3 signal output. While operating in DS3 line loopback mode, the incoming receive clock RCLK44 is used to update outgoing transmit data. In DS2 line loopback mode one or more Data Sheet 34 2001-06-29 PEB 3445 E Functional Description selectable DS2 signals are looped after the M23 stage the of the TE3-MUX. Finally the DS1/E1 line loopback mode mirrors one or more incoming lines. Tributary data provided via the low speed serial interface is replaced by the mirrored data stream. * RCLK44 RD44P RD44N DS3 Receive Framer M23 Demux DS2 Receive Framer M12 Demux DS1/E1 Interface TCLKO44 TD44P TD44N TCLK44 DS3 Transmit Framer M23 Multiplexer DS2 Transmit Framer M12 Multiplexer DS1/E1 Interface RCLK44 RD44P RD44N DS3 Receive Framer M23 Demux DS2 Receive Framer M12 Demux DS1/E1 Interface TCLKO44 TD44P TD44N TCLK44 DS3 Transmit Framer M23 Multiplexer DS2 Transmit Framer M12 Multiplexer DS1/E1 Interface RCLK44 RD44P RD44N DS3 Receive Framer M23 Demux DS2 Receive Framer M12 Demux DS1/E1 Interface TCLKO44 TD44P TD44N TCLK44 DS3 Transmit Framer M23 Multiplexer DS2 Transmit Framer M12 Multiplexer DS1/E1 Interface Figure 6 Remote Loops Data Sheet 35 2001-06-29 PEB 3445 E Functional Description 4.2 B3ZS Code In the B3ZS line code each block of three consecutive zeros is replaced by either of two replacements codes which are B0V and 00V, where B represents a pulse which applies to the bipolar rule (`+1' or `-1') and V represents a bipolar violation (two consecutive `+1' or `-1' bits). The replacement code is chosen in a way that there is an odd number of valid B pulses between consecutive V pulses to avoid the introduction of a DC component into the analog signal. The receive line decoder decodes the incoming B3ZS dual rail data signal and changes the replacement patterns to the original three-zeros pattern. Pattern sequences violating these rules are reported as bipolar violation errors. Data Sheet 36 2001-06-29 PEB 3445 E Functional Description 4.3 Tributary Mapper The tributary mapper connects any of the 28 low speed tributaries to any of the 32 DS1/ E1 low speed interfaces. A DS3 tributary consists of seven DS2 tributaries. Each DS2 tributaries consists of four DS1 tributaries when operated in DS1 format or three E1 tributaries when operated in ITU-T G.747 format. When a DS2 tributary is operated in ITU-T G.747 format the first three tributaries of a M12 multiplexer are accessible only. The fourth tributary of that M12 multiplexer is not used. Mapping of the tributaries to the serial interfaces can be done independently in receive and transmit direction. After reset the tributary mapper maps the tributaries 1..28 to the port interfaces 1..28 and the spare lines 29..32 to the port interfaces 29..32. * M23 multiplexer stage M12 multiplexer stage 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Switching stage 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Interface # DS3 interface Tributaries marked with shade are not accessible if tributary is operated in ITU-T G.747 mode Tributary # Figure 7 Tributary Mapper Data Sheet 37 2001-06-29 PEB 3445 E Functional Description Transmit Path Figure 8 shows the DS1/E1 transmit part of the TE3-MUX. Each M12 multiplexer is assigned one input switch which maps 4 out of 32 input signals to the four inputs of the M12 multiplexer. The multiplexer as well as the switch to be programmed are selected via D2TSEL.GN. Then the four outputs of the switch are configured using register D2TTM0..3. Additionally each line can be switched into remote loop mode or one selected line can be fed via the integrated bit error rate tester. * 0 0 1 2 3 M12 1 Mux #0 2 3 #0 32 + TTC(1) TTD(1) To M23 Stage 0 0 1 2 3 M12 1 Mux #6 2 3 #6 32 Spare links 0 1 2 3 #7 32 + TTC(32) TTD(32) To Receive Path From Receive Path OR Test Unit Figure 8 Receive Path Tributary Mapper (Transmit Direction) In receive direction a group of four consecutive output ports is assigned to one output switch (see Figure 9). This output switch maps any of the 28 M12 demultiplexer outputs or any of the four internal spare links to its four outputs. The output multiplexer to be programmed is selected via D2RSEL.GN. Then the four outputs of the switch are programmed via D2RTM0..3. Data Sheet 38 2001-06-29 PEB 3445 E Functional Description * From Transmit Path To Transmit Path 0 + 0 M12 1 Demux #0 2 From M23 Stage 3 RTC(1) RTD(1) 32 1 #0 2 3 0 M12 1 Demux #6 2 3 + 0 Spare links 32 1 #7 2 3 RTC(32) RTD(32) Figure 9 Tributary Mapper (Receive Direction) Data Sheet 39 2001-06-29 PEB 3445 E Functional Description 4.4 M12 Multiplexer/Demultiplexer and DS2 framer The M12 multiplexer and the DS2 framer can be operated in two modes: * M12 multiplex format according to ANSI T1.107 * ITU-T G.747 format 4.4.1 M12 multiplex format The framing structure of the M12 signal is shown in Table 1. A DS2 multiframe consists of four subframes. Each subframe combines 6 blocks with 49 bits each. The first bit of each block contains an overhead (OH) bit and 48 information bits. The 48 information bits are formed by bit-by-bit interleaving of the four DS1 signals or a total of 12 bits from each DS1 signal. The first bit is assigned to the 1st tributary DS1 signal, the second bit is assigned to the 2nd tributary DS1 signal and so on. Table 1 M12 multiplex format Subframe 1 1 DS2Multiframe 2 3 4 Block 1 through 6 of a subframe 2 3 4 5 6 [48] [48] [48] [48] M0 [48] C11 [48] F0 M1 [48] C21 [48] F0 M1 [48] C31 [48] F0 X [48] C41 [48] F0 [48] C12 [48] C13 [48] F1 [48] C22 [48] C23 [48] F1 [48] C32 [48] C33 [48] F1 [48] C42 [48] C43 [48] F1 M0, M1 M0 and M1 form the multiframe alignment signal. Each DS2 multiframe consists of three M-bits and they are located in bit 0 of subframe one through three. The multiframe alignment signal is '011'. X This bit is the fourth bit of the multiframe alignment signal and can be set to either '0' or '1'. It is accessible via an internal register. F0, F1 F0 and F1 form the frame alignment pattern. Each DS2 multiframe consists of eight F-bits, two per subframe in block 3 and 6. F0 and F1 form the pattern '01'. This pattern is repeated in every subframe. C11..C43 The C-bits control the bit stuffing procedure of the multiplexed DS1 signals. [48] These bits represent a data block, which consists of 48 bits. [48] consists of four time slots of 12 bit and each time slot is assigned to one of four participating DS1 signals. Data Sheet 40 2001-06-29 PEB 3445 E Functional Description 4.4.1.1 Synchronization Procedure The integrated DS2 framer searches for the frame alignment pattern '01' and the multiframe alignment pattern in each of the seven DS2 frames which are contained in a DS3 signal. Frame alignment is declared, when the DS2 framer has found the basic frame alignment pattern (F-bit) and the multiframe alignment pattern (M-bit). Loss of frame is declared, when 2 out of 4 or 3 out of 5 incorrect F-bits are found or when one or more incorrect M-bits are found in 3 out of 4 subframes. 4.4.1.2 Multiplexer/Demultiplexer Demultiplexer The demultiplexer extracts four DS1 signals out of each DS2 signal. If two out of three bits of Ci1, Ci2, Ci3 are set to '1' the first information bit in the ith subframe and the 6th block which is assigned to the ith DS1 signal is discarded. The demultiplexer performs inversion of the 2nd and 4th tributary DS1 signal. Multiplexer The multiplexer combines four DS1 signals to form a DS2 signal. Stuffing bits are inserted and the Ci1-, Ci2-, Ci3-bits, which are assigned to the ith DS1 signal, are set to '1' in case that not enough data is available. The 2nd and 4th DS1 signal are automatically inverted in transmit direction. 4.4.1.3 Detection Loopback Control Loopback requests encoded in the C-bits of the DS2 signal are flagged when they are repeated for at least five DS2 multiframes. Loops must be initiated by an external microprocessor. Generation A loopback request, which is transmitted in lieu of the C-bits, can be placed in each DS2 signal. Data Sheet 41 2001-06-29 PEB 3445 E Functional Description 4.4.1.4 Detection Alarm Indication Signal AIS is declared, when the AIS condition (the received DS2 data stream contains an all `1' signal with less then 3/9 zeros within 3156 bits while the DS2 framer is out of frame) is present within a time interval that is determined by register D2RAP. Generation The alarm indication signal is an all '1' unframed signal and will be transmitted if enabled. Data Sheet 42 2001-06-29 PEB 3445 E Functional Description 4.4.2 ITU-T G.747 format The multiplexing frame structure is shown in Table 2. Table 2 ITU-T G.747 format Set I II Bits from tributaries Alarm indication to the remote multiplex equipment Parity Bit Reserved ITU-T G.747 Frame Bits from tributaries III IV V Justification control bits Cj1 Bits from tributaries Justification control bits Cj2 Bits from tributaries Justification control bits Cj3 Bits from tributaries available for justification Bits from tributaries Content Frame Alignment Signal 111010000 Bit 1 to 9 10 to 168 1 2 3 4 to 168 1 to 3 4 to 168 1 to 3 4 to 168 1 to 3 4 to 6 7 to 168 4.4.2.1 Synchronization Procedure The integrated framer searches for the frame alignment pattern '111010000' in each of the seven DS2 frames which are contained in a DS3 signal. Frame alignment is declared, when the framer has found three consecutive correct frame alignment signals. If the frame alignment signal has been received incorrectly in one of the following frames after the receiver found the first correct frame alignment signal a new frame search is started. Loss of frame is declared, when four consecutive frame alignment signals have been received incorrectly. 4.4.2.2 Multiplexer/Demultiplexer Demultiplexer The demultiplexer extracts three E1 signals from each 6.312 MHz signal. If two out of three bits of Cj1, Cj2, Cj3 are set to '1' the available justification bit of the jth E1 signal is discarded. Data Sheet 43 2001-06-29 PEB 3445 E Functional Description Multiplexer The multiplexer combines three E1 signals to form a DS2 signal. Stuffing bits are inserted and the Cj1-, Cj2-, Cij-bits, which are assigned to the jth E1 signal, are set to '1' in case that not enough data is available. 4.4.2.3 Detection Parity Bit The receiver optionally calculates the parity of all tributary bits and compares this value with the received parity bit. Differences are counted in the parity error counter. Generation The parity bit is automatically calculated according to ITU-T G.747 or programmable to a fixed value under microprocessor control. 4.4.2.4 Detection Remote Alarm Indication Remote alarm is reported when bit 1 of "set II" (see Table 2 "ITU-T G.747 format" on Page 43) changes and when the change persists for at least three multiframes. Generation Remote alarm is transmitted in bit 2 of "set II" and can be inserted under microprocessor control. 4.4.2.5 Detection Alarm Indication Signal AIS is declared, when the AIS condition (the received DS2 data stream contains an all `1' signal with less then 5/9 zeros within two consecutive multiframes while the DS2 framer is out of frame) is present within a time interval that is determined by register D2RAP. Generation The alarm indication signal is an all '1' unframed signal and will be transmitted if enabled. Data Sheet 44 2001-06-29 PEB 3445 E Functional Description 4.5 M23 multiplexer and DS3 framer The DS3 path of the TE3-MUX can be operated in three modes: * M23 multiplex format * C-bit parity format with modified M23 multiplex operation * Full payload rate format 4.5.1 M23 multiplex format The framing structure of the M23 multiplex signal is shown in Table 3. Each DS3 multiframe consists of 7 subframes and each subframe of eight blocks. One block consists of 85 bits, where the first bit is the overhead (OH) bit and the remaining 84 bits contain the information bits. The 84 information bits are formed by bit-by-bit interleaving of the seven DS2 signals or a total of 12 bits from each DS2 signal. The first bit is assigned to the 1st tributary DS2 signal, the second bit is assigned to the 2nd tributary DS2 signal and so on. Table 3 Subframe 1 2 DS3Multiframe 3 4 5 6 7 M23 multiplex format Block 1 through 8 of a subframe 1 2 3 4 5 6 7 8 X [84] F1 [84] C11 [84] F0 [84] C12 [84] F0 [84] C13 [84] F1 [84] X [84] F1 [84] C21 [84] F0 [84] C22 [84] F0 [84] C23 [84] F1 [84] P [84] F1 [84] C31 [84] F0 [84] C32 [84] F0 [84] C33 [84] F1 [84] P [84] F1 [84] C41 [84] F0 [84] C42 [84] F0 [84] C43 [84] F1 [84] M0 [84] F1 [84] C51 [84] F0 [84] C52 [84] F0 [84] C53 [84] F1 [84] M1 [84] F1 [84] C61 [84] F0 [84] C62 [84] F0 [84] C63 [84] F1 [84] M0 [84] F1 [84] C71 [84] F0 [84] C72 [84] F0 [84] C73 [84] F1 [84] F0, F1 F0 and F1 form the frame alignment pattern. Each DS3 frame consists of 28 F-bits, four per subframe in block 2, 4, 6 and 8. F0 and F1 form the pattern '1001'. This pattern is repeated in every subframe. M0, M1 M0 and M1 form the multiframe alignment signal. The M-bit is contained in the OH-bit of the first block in subframe 5,6 and 7. The multiframe alignment signal is '010'. C11..C73 The C-bits control the bit stuffing procedure of the multiplexed DS2 signals. P The P-bits contain parity information and are calculated as even parity on all information bits of the previous DS3 frame. Both P-bits are identical. Data Sheet 45 2001-06-29 PEB 3445 E Functional Description X The X-bits are used for transmission of asynchronous in-service messages. Both X-bits must be identical and may not change more than once every second. [84] These bits represent a data block, which consists of 84 bits. [84] consists of seven time slots with 12 bits each and they are assigned to one of the seven participating DS2 signals. 4.5.1.1 Synchronization Procedure The integrated DS3 framer searches for the frame alignment pattern '1001' and when found for the multiframe alignment pattern in each of the seven DS3 subframes. When the multiframe alignment pattern is found in three consecutive DS3 frames while frame alignment is still valid frame alignment is declared. The P-bits and the X-bits are ignored during synchronization. Loss of frame is declared, when 3 out of 8 or 3 out of 16 incorrect F-bits are found or when one or more incorrect M-bits are found in 3 out of 4 subframes. 4.5.1.2 Multiplexer/Demultiplexer Demultiplexer The demultiplexer extracts seven DS2 signals from the incoming DS3 signal. If two or three bits out of Ci1, Ci2, Ci3 are set to '1' the first bit following the F1 bit in the ith subframe which is assigned to the ith DS2 signal is discarded. Multiplexer The multiplexer combines seven DS2 signals to form a DS3 signal. If not sufficient data is available for a DS2 signal, it automatically inserts a stuffing bit and sets the bits Ci1, Ci2, Ci3 assigned to the ith DS2 signal to '1'. 4.5.1.3 X-bit The TE3-MUX provides access to the X-bit via an internal register. Data written to the Xbit register is copied to an internal shadow register which is then locked for one second after each write access. Data Sheet 46 2001-06-29 PEB 3445 E Functional Description 4.5.1.4 Detection Alarm Indication Signal, Idle Signal Alarm indication signal or Idle signal is declared, when the selected signal format was received with less than 8/15 bit errors (selectable via bit D3RAP.AIS) for at least one multiframe. The alarm indication signal can be selected as: * Unframed all '1's * Framed '1010' sequence, starting with a binary '1' after each OH-bit. C-bits are set to `0'. X-bit can be checked as `1' or X-bit check can be disabled. The idle signal is a * Framed '1100' sequence, starting with a binary '11' after each OH-bit. C-bits are set to `0' in M-subframe 3. X-bit can be checked as `1' or X-bit check can be disabled. Generation The alarm indication signal or idle signal will be generated according to the selected signal format. X-bit needs to be set separately to `1'. 4.5.1.5 Detection Loss of Signal Loss of signal is declared, when the incoming data stream contains more than 175 consecutive '0's. Recovery Loss of signal is removed, when two or more ones are detected in the incoming data stream. 4.5.1.6 * * * * * * Performance Monitor The following conditions are counted: Line code violations Excessive zeroes P-bit errors, CP-bit errors Framing bit errors Multiframe bit errors Far end block errors Data Sheet 47 2001-06-29 PEB 3445 E Functional Description 4.5.2 C-bit parity format The framing structure of the C-bit parity format is shown in Table 3. The assignment of the information bits [84] is identical to the M23 multiplex format, but the function of the C-bits is redefined for path maintenance and data link channels. Table 4 Subframe 1 2 DS3Multiframe 3 4 5 6 7 C-bit parity format Block 1 through 8 of a subframe 1 2 3 4 5 6 7 8 X [84] F1 [84] AIC [84] F0 [84] Nr [84] F0 [84] FEAC [84] F1 [84] X [84] F1 [84] DL [84] F0 [84] DL [84] F0 [84] DL [84] F1 [84] P [84] F1 [84] CP [84] F0 [84] CP [84] F0 [84] CP [84] F1 [84] P [84] F1 [84] FEBE [84] F0 [84] FEBE [84] F0 [84] FEBE [84] F1 [84] M0 [84] F1 [84] DLt [84] F0 [84] DLt [84] F0 [84] DLt [84] F1 [84] M1 [84] F1 [84] DL [84] F0 [84] DL [84] F0 [84] DL [84] F1 [84] M0 [84] F1 [84] DL [84] F0 [84] DL [84] F0 [84] DL [84] F1 [84] F0, F1 F0 and F1 form the frame alignment pattern. Each DS3 frame consists of 28 F-bits, four per subframe in block 2, 4, 6 and 8. F0 and F1 form the pattern '1001'. This pattern is repeated in every subframe. M0, M1 M0 and M1 form the multiframe alignment signal. The M-bit is contained in the OH-bit of the first block in subframe 5,6 and 7. The multiframe alignment signal is '010'. Nr Reserved. Set to '1' in transmit direction. AIC Application Identification Channel. DLt The terminal-to-terminal path maintenance data link uses the HDLC protocol. Access to the DLt bits is possible via the integrated signalling controller. DL Reserved. Access to the DL-bits is possible via the spare bit registers. FEAC The alarm or status information of a far end terminal is sent back over the far end and control channel. This bit also contains DS3 or DS1 line loopback requests. Messages are sent in bit oriented mode. The far end alarm and control channel can be accessed via the internal signalling controller. Data Sheet 48 2001-06-29 PEB 3445 E Functional Description FEBE The far end block error bits indicate a CP-bit parity error or a framing error. They are used to monitor the performance of a DS3 signal. Upon detection of either error in the incoming data stream the FEBE-bits are set automatically to '000' in the outgoing direction. Received far end block errors are counted. CP The CP-bits are used to carry path parity information and are set to the same value as the P-bits. In receive direction the CP-bits are checked against the calculated parity and differences are counted. P The P-bits contain parity information and are automatically calculated as even parity on all information bits of the previous DS3 frame. X The X-bits are used for transmission of asynchronous in-service messages. Both X-bits must be identical and may not change more than once every second. Access to the X-bits is possible via a register. [84] These bits represent a data block, which consists of 84 bits. [84] consists of seven time slots with 12 bits each and they are assigned to one of the seven participating DS2 signals. 4.5.2.1 Synchronization Procedure The integrated DS3 framer searches for the frame alignment pattern '1001' and when found for the multiframe alignment pattern in each of the seven DS3 subframes. Frame alignment is declared when the multiframe alignment pattern is found in three consecutive DS3 frames. The P-bits and the X-bits are ignored during synchronization. Loss of frame is declared, when 3 out of 8 or 3 out of 16 incorrect F-bits are found or when one or more incorrect M-bits are found in 3 out of 4 subframes. 4.5.2.2 Multiplexer/Demultiplexer Demultiplexer The demultiplexer extracts seven DS2 signals from the incoming DS3 signal. Since the DS3 signal is always stuffed the stuffing bit assigned to each DS2 signal is discarded. Multiplexer The multiplexer combines seven DS2 signals to form a DS3 signal and automatically inserts a stuffing bit for each DS2 signal. 4.5.2.3 X-bit The TE3-MUX provides access to the X-bits via internal registers. Data Sheet 49 2001-06-29 PEB 3445 E Functional Description 4.5.2.4 Far End Alarm and Control Channel The Far End Alarm and Control Channel is handled via an internal BOM controller (see Chapter 4.6, Signalling Controller). The following byte format is assumed (the left most bit is received first): 111111110xxxxxx0B The far end alarm and control channel uses the FFH byte for synchronization. Message words start and end with a `0'. 4.5.2.5 Detection Loopback Control Loopback requests are encoded in the messages of the far end alarm and control channel. The microprocessor has access to the messages as described in Chapter 4.5.2.4. Generation A loopback request can be initiated via the far end alarm and control channel. 4.5.2.6 Detection Alarm Indication Signal, Idle Signal Alarm indication signal or Idle signal is declared, when the selected signal format was received with less than 8/15 bit errors (selectable via bit D3RAP.AIS) for at least one multiframe. The alarm indication signal can be selected as: * Unframed all '1's * Framed '1010' sequence, starting with a binary '1' after each OH-bit. C-bits are set to `0'. X-bit can be checked as `1' or X-bit check can be disabled. The idle signal is a * Framed '1100' sequence, starting with a binary '11' after each OH-bit. C-bits are set to `0' in M-subframe 3. X-bit can be checked as `1' or X-bit check can be disabled. Generation The alarm indication signal or idle signal will be generated according to the selected signal format. X-bit needs to be set separately to `1'. Data Sheet 50 2001-06-29 PEB 3445 E Functional Description 4.5.2.7 Detection Loss of Signal Loss of signal is declared, when the incoming data stream contains more than 175 consecutive '0's. Recovery Loss of signal is removed, when two or more ones are detected in the incoming data stream. 4.5.2.8 * * * * * * Performance Monitor The following conditions are counted: Line code violations Excessive zeroes P-bit errors, CP-bit errors Framing bit errors Multiframe bit errors Far end block errors Data Sheet 51 2001-06-29 PEB 3445 E Functional Description 4.5.3 Full Payload Rate Format In full payload rate format the DS3 multiframe structure can be selected according to M13 multiplex structure or C-bit parity structure. In either case the data blocks [84] carry one continuous data stream which is provided via the tributary interface one. Multiplexing/Demultiplexing of the data block [84] does NOT apply. Data Sheet 52 2001-06-29 PEB 3445 E Functional Description 4.6 Signalling Controller The signalling controller provides access to the Far End Alarm and Control Channel and to the C-bit Parity Path Maintenance Data Link Channel. Note: The C-bit parity path maintenance data link channel and the far end alarm and control channel support the same register structure. Registers assigned to the Cbit parity path maintenance data link channel start with a 'P', registers assigned to the Far End Alarm and Control Channel start with a 'F'. 4.6.1 C-bit Parity Path Maintenance Data Link Channel The TE3-MUX performs the FLAG generation, CRC generation, zero bit-stuffing and programmable idle code generation. Buffering of transmit/receive data is done in 2x32 byte deep FIFOs. The TE3-MUX additionally supports DMA support signals for operation of the C-bit parity path maintenance data link channel. Shared Flags The closing flag of a previously transmitted frame simultaneously becomes the opening flag of the following frame if there is one to be transmitted. The shared flag feature is enabled by setting PXCR.SF. CRC check As an option in HDLC mode the internal handling of received and transmitted CRC checksum can be influenced via control bits PRCFG.CRCDIS and PXCFG.DISCRC. * Receive Direction The received CRC checksum is always assumed to be in the last two bytes of a frame, immediately preceding a closing flag. If PRCFG.CRCDIS is set, the received CRC checksum will be written to the receive FIFO where it precedes the frame status byte. The received CRC checksum is additionally checked for correctness. * Transmit Direction If PXCFG.DISCRC is set, the CRC checksum is not generated internally. The checksum has to be provided via the transmit FIFO (PXFF.XFIFO) as the last two bytes. The transmitted frame will only be closed automatically with a (closing) flag. 4.6.2 Far End Alarm And Control Channel (BOM) The BOM controller supports the Far End Alarm and Control Channel according to ANSI T1.404. Data Sheet 53 2001-06-29 PEB 3445 E Functional Description Data Transmission Transmission of BOM data is done by using a transparent mode of the signalling controller. After having written 1 to 32 bytes to the transmit FIFO, the command 'Start Transmission, Enable Automatic Repetition' via the handshake register FHND forces the TE3-MUX to repeatedly transmit the data stored in the transmit FIFO to the remote end. The cyclic transmission continues until a reset command (FHND.XRES) is issued or until the command `Stop Transmission, Disable Automatic Repetition' is written to the handshake register FHND. Afterwards an all `1' pattern is transmitted. The transmitter does not insert FFH itself. Data stored in the transmit FIFO has to include the FFH byte as well and has to follow the following byte format: 111111110xxxxxx0B Data Reception BOM Regular Mode The following byte format is assumed (the left most bit is received first): 111111110xxxxxx0B The signalling controller uses the first two FFH bytes for synchronization, the next byte is stored in the receive FIFO (first bit received: LSB) if it starts and ends with a `0', that is the receiver automatically removes the FFH synchronization byte. Bytes starting or ending with a `1' are not stored. If the message word 7EH (similar to HDLC flag) is received or when more than four times FFH is received byte sampling is stopped and a 'Receive Message End' interrupt vector is generated. Byte sampling starts again when the synchronization byte FFH is received two times. After detecting 32 bits of `1's, byte sampling is stopped, the receive status byte marking the end of a BOM frame is stored in the receive FIFO and a 'BOM Idle' interrupt is generated. The same interrupt is generated when not eight consecutive ones where received in 32 bits. Data Reception BOM Filter Mode In BOM filter mode the received BOM data is validated and then filtered. If same valid BOM pattern is received for 7 out of 10 patterns, then BOM data is written to the receive FIFO along with the status byte indicating that filtered BOM data was received. Filtered BOM mode will be exited if one of the following conditions occurs: * 4 valid BOM patterns are consecutively received but none of these equals the BOM data received earlier. * 4 times idle pattern is received. 4.6.3 Signalling controller FIFO operation Access to the FIFO's of the signalling controllers is handled via registers. The corresponding FIFO's for receive and transmit direction of the C-bit parity Path Data Sheet 54 2001-06-29 PEB 3445 E Functional Description Maintenance data link channel are named PRFF and PXFF respectively. The FIFOs of the Far End Alarm and Control Channel are named FRFF and FXFF. FIFO status and commands are exchanged using the port status registers PPSR (FPSR) and the handshake register PHND (FHND). The C-bit parity Path Maintenance Data Link Channel supports an external DMA controller via the signals DRR, RME or DRT and TXME. Additional interrupts inform the system software about protocol status and FIFO status. 4.6.3.1 Interrupt Driven Microprocessor Operation Receive Direction In receive direction there are different interrupt indications associated with the reception of data: * A 'Receive Pool Full' (RPF) interrupt indicates that a data block can be read from the receive FIFO and the received message is not yet complete. It is generated, when the amount of data bytes has reached the programmed threshold. * A 'Receive Message End' (RME) or 'Receive Message Idle' interrupt indicates that the reception of one message is completed. After this interrupt system software has to read the corresponding port status register in order to get the number of bytes stored in the receive FIFO. This number includes the status byte which is written into the receive FIFO as the last byte after the received frame. The status byte includes information about the CRC result, valid frame indication, abort sequence or data overflow. The format of the status byte is shown in the table below: 7 6 5 0 4 STAT(4:0) 0 SMODE(1:0) SMODE STAT Receiver Status Mode Receive FIFO Status This bit field reports the status of the data stored in the receive FIFO. The content of the status byte is dependent on the channel. C-bit Parity Path Maintenance Data Link 00000B 00001B 00010B Valid HDLC Frame Receive Data Overflow Receive Abort Far End Alarm and Control Channel BOM Filtered data declared BOM Data Available Flag 7EH Received Data Sheet 55 2001-06-29 PEB 3445 E Functional Description C-bit Parity Path Maintenance Data Link 00011B 00100B 00101B Not Octet CRC Error Channel Off Far End Alarm and Control Channel BOM Filtered Data Undeclared BOM Idle n/a Note: For a description of the status information refer to Page 165 and Page 177. After the received data has been read from the FIFO, the receive FIFO has to be released by the CPU with the command 'Receive Message Complete' (FHND.RMC, PHND.RMC). The CPU has to process a 'Receive Pool Full' interrupt and issue the 'Receive Message Complete' command before the second page of the FIFO becomes full. Otherwise a 'Receive Data Overflow' condition will occur. This time is dependent on the threshold programmed (smaller threshold results in shorter time). * Receive frame (79 bytes) FDL channel 32 bytes 32 bytes 15 bytes Local Bus Interface RD 32 bytes RPF RMC RPF RD 32 bytes RD RD RD RBC 15 bytes status RMC RMC RME Figure 10 Interrupt Driven Reception Sequence Example (32-byte Receive Threshold) Transmit Direction In the transmit direction after checking the transmit FIFO status by polling the transmit FIFO write enable bit (FPSR.XFW, PPSR.XFW) or after a 'Transmit Pool Ready' interrupt, up to 32 bytes may be written to the transmit FIFO (bit field FXFF.XFIFO, PXFF.XFIFO) by the CPU. Transmission of a frame can be started by issuing a 'Start Transmission' command (see register FHND on Page 167 for Far End Alarm and Control Channel and register PHND on Page 179 for C-bit parity Path Maintenance Data Data Sheet 56 2001-06-29 PEB 3445 E Functional Description Link). If the transmit command does not include a 'Transmit Message End' indication (FHND.XME, PHND.XME), the signalling controller will repeatedly request for the next data block by means of a XPR interrupt as soon as the transmit FIFO becomes free. This process will be repeated until the local CPU writes the last bytes to the transmit FIFO. End of transmission is by issuing the command 'Stop Transmission'. In case of C-bit Parity Path Maintenance Data Link channel CRC and closing flag sequence is appended after the last byte was sent. C-bit parity path maintenance data link channel only: Consecutive frames may share a flag (enabled via bit PXCR.SF) or may be transmitted as back-to-back frames, if service of transmit FIFO is quick enough. In case that no more data is available in the transmit FIFO prior to the arrival of PHND.XME, the transmission of the frame is terminated with an abort sequence and the CPU is notified via a 'Transmit Data Underrun' interrupt (XDU). The frame may also be aborted per software by setting the XAB bit in the handshake register PHND. In case of messages longer than 32 bytes the transmit FIFO has to be filled up in blocks of 32 bytes. The last block of the message can be smaller than 32 bytes. If the transmit FIFO is not filled up in time a transmit abort (C-bit parity Path Maintenance Data Link) is inserted or gaps between BOM messages (Far End Alarm and Control Channel) may occur. * Transmit frame (79 bytes) FDL channel 32 bytes 32 bytes 15 bytes Local Bus Interface WR 32 bytes XTF XPR WR 32 bytes XTF XPR WR 15 bytes XTF+XME XPR ALLS Figure 11 Interrupt Driven Transmit Sequence Example Note: Data bus is 16 bit wide. In the given example writing 32 bytes requires 16 write accesses. Writing 15 bytes requires 8 accesses. Data Sheet 57 2001-06-29 PEB 3445 E Functional Description 4.6.3.2 DMA Supported Data Transmission The C-bit parity Path Maintenance Data Link Channel supports additionally DMA signals to optimize data transfers to and from the internal FIFOs. Request signals for transmit and receive direction indicate free respectively available channel data. The RME (Receive Message End) signal and the TXME (Transmit Message Complete) signal indicates the end of a message. Receive Direction Data reception can be initiated by enabling the HDLC controller and setting the DMA functionality in register PRCFG. As soon as there is a data byte in the receiver the TE3MUX autonomously requests a data transfer by activating the DRR line. This indicates to the DMA controller to read a data byte out of the receive FIFO PRFF. This sequence continuous until the last byte is transferred via the DMA controller. The last byte in the receive FIFO is always the status byte which contains the frame status information, e.g. 'Receive Abort' or `CRC error'. When the last byte of a message was read out of the receive FIFO the signal RME is asserted to indicate that the port status register PPSR needs to be read in order to free the internal buffer. * C-bit Parity Path Maintenance Data Link Receive frame (8 bytes) D0 D1 D2 D3 D4 D5 CRC CRC Flag Local Bus Interface RD D0 (PRFF) DRR RD D5 (PRFF) DRR RD Status (PRFF) Read PPSR XME Enable DMA DRR Figure 12 DMA Supported Receive Sequence Transmit Direction Prior to data transmission the HDLC controller has to be enabled and the DMA support must be activated via the register PXCFG. As long as there is free space in the transmit FIFO the signalling controller requests data by asserting the DRT line which indicates that the external DMA controller can write data to the transmit FIFO. While writing the last byte of a message the external DMA must assert the signal TXME, that is the signal Data Sheet 58 2001-06-29 PEB 3445 E Functional Description must be asserted while the data byte is on the microprocessor bus. Then the next data transfer is the first byte of a new message. The TE3-MUX automatically appends the CRC and the flags between messages. * Transmit Message (8 bytes) C-bit Parity Path Maintenance Data Link D0 D1 D2 D3 D4 D5 CRC CRC Flag Local Bus Interface WR D0 (PXFF) Enable DRT DMA WR D5 (PXFF) Set XME WR Data (PXFF) DRT 2nd message DRT Transmit Message (8 bytes) Figure 13 DMA supported Transmit Sequence Data Sheet 59 2001-06-29 PEB 3445 E Functional Description 4.7 Test Unit The test unit of the TE3-MUX incorporates a test pattern generator and a test pattern synchronizer which can be attached to different test points as shown in Figure 14. Controlled by a small set of registers it can generate and synchronize to polynomial pseudorandom test patterns or repetitive fixed length test patterns. Test patterns can be generated in the following modes: * * * * * Framed DS3 Unframed DS2 Framed DS2 Unframed DS1/E1 Framed DS1/E1 Note: When the test unit is operated in framed DS1 mode, the bit error rate must be below 1/100. * DS2 Framer DS2 Framer M12 DS3 Framer M23 (De)multiplexer DS2 Framer M12 0 6 Test Port Select 0 6 Test Port Select 0 27 Test Port Select Test Mode Select To DS1/E1 Framer Test Unit Figure 14 Test Unit Access Points In pseudorandom test mode the receiver tries to achieve synchronization to a test pattern which satisfies the programmed receiver polynomial. In fixed pattern mode it synchronizes to a repetitive pattern with a programmable length. An all '1' pattern or an all '0' pattern, which satisfies this condition, is flagged. Measurement intervals as well as receiver synchronization can be controlled by the user. When a test is finished an interrupt is generated and the bit count and the bit error count are readable. Data Sheet 60 2001-06-29 PEB 3445 E Functional Description * + Feedback in Pseudorandon pattern mode only 0 1 X-1 X N-2 N-1 + N X Pattern length Feedback Tap Bit error insertion Figure 15 Pattern Generator Bit Error Insertion The test unit provides the optional capability to insert bit errors in the range of 10-7 (1 error in 10.000.000 bits) up to 10-1 bit errors (1 error in 10 bits). External Bit Error Test Four of the 32 low speed tributary interfaces can be used for protection switching or to connect an external bit error rate tester to one of the 28 DS1/21E1 tributaries. Data Sheet 61 2001-06-29 PEB 3445 E Functional Description 4.8 Interrupt Interface Special events in the TE3-MUX are indicated by means of a single interrupt output with programmable characteristics (open drain, push-pull, active low/high), which requests the CPU to read status information or to transfer to/from the TE3-MUX. Since only one interrupt output is provided the cause of an interrupt must be determined by the external CPU by reading the interrupt status register D3RINTV which indicates the interrupt reason and the interrupt source. Status changes of the test unit, the DS2 framer or the DS3 framer require a second read of register D3RINTC while loopback code changes of the DS2 receiver require a read of register D3RINTL. The interrupt pin is deactivated when register D3RINTV was read and no further interrupts are pending. As long as further interrupts are pending the interrupt pin remains asserted and the process as described above needs to be repeated until all pending interrupts are resolved. Data Sheet 62 2001-06-29 PEB 3445 E Interface Description 5 5.1 Interface Description Local Microprocessor Interface The Local Microprocessor Interface is a demultiplexed/multiplexed switchable Intel or Motorola style interface with an 8- or 16-bit bus interface. 5.1.1 Intel Mode The Intel mode supports a 16- or 8-bit bus interface with demultiplexed or multiplexed bus operation. For multiplexed bus operation LA(7:0) must be connected to LD(7:0). The TE3-MUX uses the port pins LA(7:0) for the 8 bit address and the port pins LD(15:0) for 16/8 bit data or LD(7:0) in 8-bit interface mode. A read/write access is initiated by placing an address on the address bus and then asserting LCS. The external processor then activates the respective command signal (LRD, LWR). Data is driven onto the data bus either by the TE3-MUX (for read cycles) or by the external processor (for write cycles). After a period of time, which is determined by the access time to the internal registers valid data is placed on the bus. In multiplexed bus operation a falling edge of LALE indicates a valid address on LA(7:0) and the corresponding byte enable on LBHE. If operated in demultiplexed operated LALE must be connected to VDD3. Note: LCS need not to be deasserted between two subsequent cycles to the same device. Read cycles Input data can be latched and the command signal can be deactivated now. This causes the TE3-MUX to remove its data from the data bus which is then tri-stated again. Write cycles The command signal can be deactivated now. If a subsequent bus cycle is required, the external processor can place the respective address on the address bus. Table 5 LBHE 0 0 1 1 Data Bus Access 16-bit Intel Mode LA(0) Register Access 0 1 0 1 Word access (16 bit) Byte access (8 bit), odd address Byte access (8 bit), even address No data transfer Data Pins Used LD(15:0) LD(15:8) LD(7:0) - Data Sheet 63 2001-06-29 PEB 3445 E Interface Description * Read Cycle (16 Bit) LA(7:0) Address Write Cycle (8 bit) Address LBHE LCS LRD LWR LD(15:0) Data Data Figure 16 * Intel Bus Mode (Demultiplexed Bus Operation) Read Cycle (16 Bit) LA(7:0) LD(15:0) LALE Addr. Data Addr. Write Cycle (8 bit) Data LBHE LCS LRD LWR Figure 17 Intel Bus Mode (Multiplexed Bus Operation) Data Sheet 64 2001-06-29 PEB 3445 E Interface Description 5.1.2 Motorola Mode The Motorola bus mode supports a 16- or 8-bit bus interface with demultiplexed or multiplexed bus operation. For multiplexed bus operation LA(7:0) must be connected to LD(7:0). The TE3-MUX uses the port pins LA(7:0) for the 8 bit address and the port pins LD(15:0) for 16/8 bit data or LD(7:0) in 8-bit interface mode. A read/write access is initiated by placing an address on the address bus and asserting LCS together with the command signal LRDWR (see "Motorola Bus Mode (Demultiplexed Bus Operation)" on Page 66). The data cycle begins when the signal LDS is asserted. Data is driven onto the data bus either by the TE3-MUX (for read cycles) or by the external processor (for write cycles). After a period of time, which is determined by the access time to the internal registers valid data is placed on the bus. In multiplexed bus operation a falling edge of LALE indicates a valid address on LA(7:0)and the corresponding byte enable signal on LBLE. If operated in demultiplexed bus mode LALE must be connected to VDD3. Note: LCS need not to be deasserted between two subsequent cycles to the same device. Read cycles Input data can be latched and the data strobe signal can be deactivated now. This causes the TE3-MUX to remove its data from the data bus which is then tri-stated again. Write cycles The data strobe signal can be deactivated now. If a subsequent bus cycle is required, the external processor can place the respective address on the address bus. Table 6 Data Bus Access 16-bit Motorola Mode Register Access Word access (16 bit) Byte access (8 bit), even address Byte access (8 bit), odd address no data transfer Data Pins Used LD(15:0) LD(15:8) LD(7:0) - LBLE LA(0) 0 0 1 1 0 1 0 1 Data Sheet 65 2001-06-29 PEB 3445 E Interface Description * Read Cycle (8 bit) LA(7:0) Address Write Cycle (16 bit) Address LBLE LCS LDS LRDWR LD(15:0) Data Data Figure 18 * Motorola Bus Mode (Demultiplexed Bus Operation) Read Cycle (8 bit) LA(7:0) LD(15:0) LALE Addr. Data Addr. Write Cycle (16 bit) Data Address LBLE LCS LDS LRDWR Figure 19 Motorola Bus Mode (Multiplexed Bus Operation) Data Sheet 66 2001-06-29 PEB 3445 E Interface Description 5.2 5.2.1 Serial Interface Timing DS3 Interface The DS3 interface of the TE3-MUX consists of one receive port and one transmit port. The receive port provides a clock input (RCLK44) and one (RD44) or two data inputs (RD44P, RD44N) for unipolar or dual-rail input signals. Receive data can be sampled on the rising or falling edge of the receive clock. In transmit direction the port interface consists of two clock signals, the transmit clock input TCLK44 and a clock output signal TCLKO44. The data signals consists of one (TD44) or two data outputs (TD44P, TD44N) for unipolar or dual-rail output signals. The transmit port can be clocked by the receive clock RCLK44 or by the transmit clock TCLK44. The selected clock is provided as an output on TCLKO44. Transmit data is updated on the rising or falling edge of TCLKO44. The TE3-MUX provides two additional serial interfaces, one for DS3 overhead bit access and one for DS3 stuff bit access (M13 asynchronous format only). The overhead access is provided via an overhead clock signal (ROVHCK, TOVHCK), an overhead data signal (ROVHD, TOVHD) and an synchronization signal (ROVHSYN, TOVHSYN) which marks the X overhead bit of the first subframe of a DS3 signal. In transmit direction the overhead enable signal (TOVHDEN) marks those bits which shall be inserted in the overhead bits of the DS3 signal. Overhead signals are updated on the falling edge or sampled on the rising edge of the corresponding overhead clock. See Figure 20 and Figure 21 for details. * 7th subframe 1st subframe RCLK44 RD44 F1 84 data bits X 84 data bits F1 84 data bits C11 ROVHCK ROVHD F1 X F1 ROVHSYN Figure 20 Receive Overhead Access Data Sheet 67 2001-06-29 PEB 3445 E Interface Description * 1. Transmit Overhead Bit Access (TOVHSYN in output mode) 7th subframe 1st subframe TCLKO44 TD44 C73 84 data bits F1 84 data bits X 84 data bits F1 TOVHCK TOVHD TOVHSYN (Output mode) TOVHDEN F1 X F1 2. Transmit Overhead Bit Access (TOVHSYN in input mode) 7th subframe 1st subframe TCLKO44 TD44 TOVHSYN (Input mode) TOVHCK C73 84 data bits F1 84 data bits X 84 data bits F1 TOVHD F1 X F1 TOVHDEN Figure 21 Transmit Overhead Access The stuff bit access is provided via a receive and transmit stuff bit clock (RSBCK, TSBCK) and the two stuff bit signals RSBD and TSBD. Stuff bits are updated on the falling edge and sampled on the rising edge of the corresponding stuff bit clock. Data Sheet 68 2001-06-29 PEB 3445 E Interface Description 5.2.2 DS1/E1 Interface/DS3 System Interface Dependent on the selected operational mode the TE3-MUX operates in channelized mode, where the M13 multiplexer is enabled, or in unchannelized mode where the M13 multiplexer is disabled. In unchannelized mode the first tributary interface is used to transfer DS3 payload data. 5.2.2.1 DS1/E1 Interface In receive direction (DS3 --> DS1/E1) each port consists of a clock output RTC(x) and the corresponding data output RTD(x). The receive clock is nominally a 1.544 MHz (DS1) respectively a 2.048 MHz (E1) clock. Due to the demultiplexing and destuffing process this clock contains clock gaps. Each port can be mapped independently to any of the 28 tributaries of the T3 signal. In transmit direction (DS1/E1--> DS3) each port consists of a clock input TTC(x) and the corresponding data input TTD(x). This clock is nominally a 1.544 MHz (DS1 mode) respectively a 2.048 MHz (E1) clock. 5.2.2.2 DS3 System Interface In unchannelized mode the first DS1/E1 interface is used to transfer DS3 payload data. The DS3 payload clocks are derived from the DS3 receive respectively the DS3 transmit clock. In receive direction the overhead bits are extracted and the receive clock is gapped on those positions which contain the overhead bits. In transmit direction clock #1 (TTC(1)) is switched to output direction and transmit data needs to be provided via TTD(1). TTC(1) is gapped on those positions where the overhead bits need to be inserted by the TE3-MUX. Data Sheet 69 2001-06-29 PEB 3445 E Interface Description 5.3 JTAG Interface A test access port (TAP) is implemented in the TE3-MUX. The essential part of the TAP is a finite state machine (16 states) controlling the different operational modes of the boundary scan. Both, TAP controller and boundary scan, meet the requirements given by the JTAG standard: IEEE 1149.1. Figure 22 gives an overview about the TAP controller. * Test Access Port (TAP) TCK CLOCK Pins Clock Generation CLOCK 1 2 Identification Scan (32 bit) . . . TRST Reset TMS Test Control TAP Controller Control Bus - Finite State Machine - Instruction Register (4 bit) - Test Signal Generator Boundary Scan (n bit) n TDI Data in ID Data out SS Data out . . . TDO Enable Data out Figure 22 Block Diagram of Test Access Port and Boundary Scan Unit If no boundary scan operation is planned TRST has to be connected to VSS. TMS and TDI do not need to be connected since pull- up transistors ensure high input levels in this case. Nevertheless it would be a good practice to put the unused inputs to defined levels. In this case, if the JTAG is not used: TMS = TCK = `1' is recommended. Test handling (boundary scan operation) is performed via the pins TCK (Test Clock), TMS (Test Mode Select), TDI (Test Data Input) and TDO (Test Data Output) when the TAP controller is not in its reset state, i. e. TRST is connected to VDD3 or TRST input is open in which case internal pull sets TRST to VDD3. Test data at TDI are loaded with a clock signal connected to TCK. `1' or `0' on TMS causes a transition from one controller state to another; constant `1' on TMS leads to normal operation of the chip. An input pin (I) uses one boundary scan cell (data in), an output pin (O) uses two cells (data out, enable) and an I/O-pin (I/O) uses three cells (data in, data out, enable). Note that most functional output and input pins of the TE3-MUX are tested as I/O pins in boundary scan, hence using three cells. The boundary scan unit of the TE3-MUX Data Sheet 70 2001-06-29 PEB 3445 E Interface Description contains a total of n = 484 scan cells. The desired test mode is selected by serially loading a 4-bit instruction code into the instruction register via TDI (LSB first). EXTEST is used to examine the interconnection of the devices on the board. In this test mode at first all input pins capture the current level on the corresponding external interconnection line, whereas all output pins are held at constant values (`0' or `1'). Then the contents of the boundary scan is shifted to TDO. At the same time the next scan vector is loaded from TDI. Subsequently all output pins are updated according to the new boundary scan contents and all input pins again capture the current external level afterwards, and so on. INTEST supports internal testing of the chip, i. e. the output pins capture the current level on the corresponding internal line whereas all input pins are held on constant values (`0' or `1'). The resulting boundary scan vector is shifted to TDO. The next test vector is serially loaded via TDI. Then all input pins are updated for the following test cycle. SAMPLE/PRELOAD is a test mode which provides a snapshot of pin levels during normal operation. IDCODE: A 32-bit identification register is serially read out via TDO. It contains the version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits). The LSB is fixed to `1'. The ID code field is set to Version Part Number Manufacturer : 1H : 0078H : 083H (including LSB, which is fixed to '1') Note: Since in test logic reset state the code `0011' is automatically loaded into the instruction register, the ID code can easily be read out in shift DR state. BYPASS: A bit entering TDI is shifted to TDO after one TCK clock cycle. CLAMP allows the state of signals driven from component pins to be determined from the boundary-scan register while the bypass register is selected as the serial path between TDI and TDO. Signals driven from the TE3-MUX will not change while the CLAMP instruction is selected. HIGHZ places all of the system outputs in an inactive drive state. Data Sheet 71 2001-06-29 PEB 3445 E Reset and Initialization procedure 6 Reset and Initialization procedure Since the term "initialization" can have different meanings, the following definition applies: Chip Initialization Generating defined values in all on-chip registers, RAMs (if required), flip-flops etc. Mode Initialization Software procedure, that prepares the device to its required operation, i.e. mainly writing on-chip registers to prepare the device for operation in the respective system environment. Operational programming Software procedures that setup, maintain and shut down operational modes, i.e. initialize logical channel or maintain framing operations on selected ports. 6.1 Chip Initialization Reset phase The hardware reset RST has to be applied to the device. Chip input TRST must be activated prior to or while asserting RST and should be held asserted as long as the boundary scan operation is not required. During reset: * All I/Os and all outputs are tri-state. * All registers, state machines, flip-flops etc. are set asynchronously to their reset values and all internal modules are set to their initial state. * All interrupts are masked. After hardware reset (RST deasserted) the transmit clock TCLK44 is assumed to be running. Tributary clocks must be low/high or running. The local bus interface goes into its operational state. 6.2 Mode Initialization After reset the TE3-MUX is configured in C-bit parity mode. System software has to setup the device for the required function. Data Sheet 72 2001-06-29 PEB 3445 E Register Description 7 Register Description The register description of the TE3-MUX is divided into two parts, an overview of all internal registers and in the second part a detailed description of all internal registers. 7.1 Register Overview Note: Register locations not contained in the following register tables are "reserved". In general all write accesses to reserved registers are discarded and read access to reserved registers result in 0000H (16-bit bus mode) or 00H (8-bit bus mode). Nevertheless, to allow future extensions, system software shall access documented registers only, since writes to reserved registers may result in unexpected behavior. The read value of reserved registers shall be handled as don't care. Unused and reserved bits are marked with a gray box. The same rules as given for register accesses apply to reserved bits, except that system software shall write the documented default value in reserved bit locations. Note: The lower 8 bits (bits 7..0) of a register correspond to even address, the upper 8 bits (bits 15..8) correspond to an odd address. Table 7 Register Register Overview Access Address Reset value Comment Page DS3 Clock Configuration and Status Register D3CLKCS TUCLKC D3TCFG D3TCOM D3TLPB D3TLPC D3TAIS D3TFINS D3TTUC D3TSDL R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00H 01H 02H 04H 05H 06H 07H 08H 09H 0AH 00H 00H 0000H 70H 00H 00H 00H 00H 00H 01FFH DS3 Clock Configuration and Status Test Unit Clock Configuration Transmit Configuration Transmit Command Remote DS2 Loopback Transmit Loopback Code Insertion Transmit AIS Insertion Transmit Fault Insertion Control Transmit Test Unit Control Transmit Spare Data Link 78 80 81 83 85 86 87 88 89 90 DS3 Transmit Control Registers Data Sheet 73 2001-06-29 PEB 3445 E Register Description Register Access Address Reset value 0000H 00H 00H 0FFFH 00H 00H 0001H 00H 01FFH 0000H 0000H 0000H 0000H 0000H 0000H 00H 0000H 00H 00H 00H 00H 00H 00H 00H 00H 00H 74 2001-06-29 Comment Page DS3 Receive Control/Status Registers D3RCFG D3RCOM D3RAP D3RIMSK D3RESIM D3RTUC D3RSTAT D3RLPCS D3RSDL D3RCVE D3REXZ D3RFEC D3RPEC D3RCPEC D3RFEBEC D3RINTV D3RINTC D3RINTL D2TSEL D2TCFG D2TCOM D2TLPC D2TTM0 D2TTM1 D2TTM2 D2TTM3 R/W R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W 10H 12H 13H 14H 16H 17H 18H 1AH 1CH 1EH 2EH 20H 22H 24H 26H 28H 2AH 2CH 30H 31H 32H 33H 34H 35H 36H 37H Receive Configuration Receive Command Alarm Timer Parameters Receive Interrupt Mask Receive Error Simulation Receive Test Unit Control Receive Status Receive Loopback Code Status Receive Spare Data Link Receive B3ZS Code Violation Error Counter Receive Excessive Zero Counter Receive Framing Error Counter Receive Parity Error Counter Receive Path Parity Error Counter Receive FEBE Error Counter Interrupt Vector Interrupt Status Interrupt Loopback Code Status DS2 Transmit Group Select Transmit Configuration Transmit Command Remote DS1/E1 Loopback Loopback Code Insertion 91 94 96 97 98 99 100 103 104 105 105 106 106 107 107 108 111 112 113 114 115 116 DS2 Transmit Control Registers Tributary Map Registers 117 Data Sheet PEB 3445 E Register Description Register Access Address Reset value 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 0000H 0000H Local DS1/E1 Loopback AIS Insertion Register Receive Status Receive Loopback Code Status Alarm Timer Parameters Receive Framing Bit Error Counter Receive Parity Bit Error Counter (G.747) Transmit Configuration Transmit Command Transmit Error Insertion Rate Transmit Fixed Pattern 125 126 128 129 131 131 Tributary Map Registers 124 Comment Page DS2 Receive Control Registers D2RSEL D2RCFG D2RCOM D2RIMSK D2RTM0 D2RTM1 D2RTM2 D2RTM3 D2RLAIS D2RSTAT D2RLPCS D2RAP D2RFEC D2RPEC R/W R/W R/W R/W R/W R/W R/W R/W R R R R/W R/W R/W 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4EH DS2 Receive Group Select Receive Configuration Receive Command Receive Interrupt Mask 118 119 121 123 Test Unit Transmit Registers TUTCFG TUTCOM TUTEIR TUTFP0 TUTFP1 TURCFG TURCOM TURERMI TURIMSK TURSTAT R/W W R/W R/W R/W R/W W R/W R/W R 50H 52H 53H 54H 56H 58H 5AH 5BH 5CH 5EH 0000H 00H 00H 0000H 0000H 0000H 00H 00H 1F1FH 0001H 132 133 135 136 Test Unit Receive Registers Receive Configuration Receive Command Receive Error Measurement Interval Receive Interrupt Mask Receive Status 137 139 141 142 143 Data Sheet 75 2001-06-29 PEB 3445 E Register Description Register TURBC0 TURBC1 TUREC0 TUREC1 TURFP0 TURFP1 TUTFCFG TUTFCOM TURFCFG TURFCOM TURFSTAT TURFFEC TURFCEC TURFEBC Access Address R R R R R R R/W R/W R/W R/W R R R R 60H 62H 64H 66H 68H 6AH 70H 71H 74H 75H 76H 78H 7AH 7CH Reset value 0000H 0000H 0000H 0000H 0000H 0000H 00H 00H 00H 00H 00H 0000H 0000H 0000H Comment Receive Bit Counter Receive Error Counter Receive Fixed Pattern Page 145 147 149 Test Unit Framer Registers Transmit Framer Configuration Transmit Framer Command Receive Framer Configuration Receive Framer Command Receive Framer Status Register Receive Framing Error Counter Receive Framer CRC Error Counter Receive Framer Errored Block Counter Receive Configuration Register Receive FIFO Transmit Configuration Register Transmit FIFO Port Status Register Handshake Register Interrupt Mask Register Receive Configuration Register Receive FIFO Transmit Configuration Register Transmit FIFO Port Status Register 150 152 153 155 156 157 158 159 Far End Alarm and Control Channel (BOM) FRCFG FRFF FXCFG FXFF FPSR FHND FMSK PRCFG PRFF PXCFG PXFF PPSR Data Sheet R/W R R/W W R W R/W R/W R R/W W R 80H 82H 84H 86H 88H 8AH 8CH 90H 92H 94H 96H 98H 0000H 0000H 00H 0000H 2000H 0000H 00H 0000H 0000H 0000H 0000H 2000H 76 160 162 163 164 165 167 170 171 173 174 176 177 C-Bit Path Maintenance Channel (HDLC) 2001-06-29 PEB 3445 E Register Description Register PHND PMSK Access Address W R/W 9AH 9CH Reset value 0000H 00H Comment Handshake Register Interrupt Mask Register Page 179 181 Data Sheet 77 2001-06-29 PEB 3445 E Register Description 7.2 7.2.1 Detailed Register Description DS3 Control and Status Registers D3CLKCS DS3 Clock Configuration and Status Register Access Address Reset Value : read/write : 00H : 00H 5 4 3 2 1 0 7 0 6 RCA TCA RRX RTX T2RL R2TL TXLT RCA Receive Clock Activity This bit monitors the receive clock activity (RCLK44). 0 1 No receive DS3 clock since last read of this register. At least one receive DS3 clock since last read of this register. TCA Transmit Clock Activity This bit monitors the transmit clock activity (TCLK44). 0 1 No transmit DS3 clock since last read of this register. At least one transmit DS3 clock since last read of this register. RRX Reset receiver This bit resets the receiver. 0 1 Normal operation. Reset DS3 receiver. This bit is self clearing. RTX Reset transmitter This bit resets the transmitter. 0 1 Normal operation. Reset DS3 transmitter. This bit is self clearing. Data Sheet 78 2001-06-29 PEB 3445 E Register Description T2RL Transmit to Receive Loop (Local DS3 Loopback) This bit enables the local DS3 loop where the outgoing DS3 bit stream is mirrored to the DS3 input. 0 1 R2TL Disable local loop. Enable local loop. Receive to Transmit Loop (Remote DS3 Loopback) This bit enables the remote DS3 line loop where the complete incoming DS3 bit stream is mirrored to the transmitter. 0 1 Disable remote loop. Enable remote loop. TXLT Transmit Loop Timing Mode This bit enables DS3 looped timing where the transmitter uses the receivers DS3 input clock. 0 1 Disable looped timing. Enabled looped timing. Data Sheet 79 2001-06-29 PEB 3445 E Register Description TUCLKC Test Unit Clock Configuration Register Access Address Reset Value : read/write : 01H : 00H 1 0 0 0 0 0 0 7 0 RTUR TUL RTUR Reset Test Unit Receiver This bit resets the test unit receiver. 0 1 Normal operation. Reset Receiver (automatically removed). This bit is self clearing. TUL Test Unit Transmit to Receive Loop This bit switches a local loop from the test unit transmitter to the test unit receiver. While operating in loop mode the test unit is operated with TCLK44. 0 1 Normal operation. Test unit transmitter output connected to test unit receiver input. Data Sheet 80 2001-06-29 PEB 3445 E Register Description D3TCFG DS3 Transmit Configuration Register Access Address Reset Value : read/write : 02H : 0000H 10 0 0 0 0 9 8 7 6 ITD 5 4 3 2 1 FPL 0 CBP 15 0 ITRCK ITRD FAM ITCK UTD AISC LPC(1:0) ITRCK Invert DS1/E1 Interface Clock This bit sets the clock edge for data sampling on the low speed interfaces. 0 1 Sample data on the falling edge of TTC(x). Sample data on the rising edge of TTC(x). ITRD Invert DS1/E1 Data This bit enables inversion of sampled data. 0 1 No inversion of data sampled on TTD(x). Invert data sampled on TTD(x). FAM TOVHSYN Mode This bit switches between input mode and output mode of the signal pin TOVHSYN. If TOVHSYN is operated in input mode it marks the position of the X-bit. Therefor the outgoing DS3 frame is aligned to TOVHSYN. If TOVHSYN is switched to output mode TOVHSYN is asserted when the X-bit needs to be inserted via the transmit overhead interface. 0 1 TOVHSYN switched to input. TOVHSYN switched to output. ITCK Invert DS3 Transmit Clock This bit sets the clock edge on which transmit data TD44P/TD44N is updated with respect to the transmit clock TCLKO44. 0 1 Update transmit data on the rising edge of the transmit clock. Update transmit data on the falling edge of transmit clock. Data Sheet 81 2001-06-29 PEB 3445 E Register Description ITD Invert DS3 Transmit Data This bit enables inversion of DS3 transmit data. 0 1 UTD Transmit data is logic high (not inverted). Transmit data is logic low (inverted). Unipolar data mode This bit sets the port mode to dual-rail mode or unipolar mode. 0 1 B3ZS (dual rail data). Unipolar mode (single rail data). AISC AIS Code Type This bit field sets the AIS code. 0 1 Set AIS to '1010... ' between overhead bits, C-bits all `0's. The Xbits needs to be set via D3TCOM.TXBIT. Set AIS to unframed all `1's (non-standard). LPC Loopback Code. This bit field selects the C-bit which will be inverted when loopback requests are transmitted. 00 01 10 Invert 1st C-bit. Invert 2nd C-bit. Invert 3rd C-bit. FPL Full Payload Mode This bit enables the M23 multiplex operation or the full payload rate format. 0 1 Enable M23 multiplex operation. Payload is formed by interleaving 7 asynchronous DS2 tributaries. Enable full payload rate format. The payload is one single, high speed data stream without stuffing. CBP C-bit parity mode This bit enables M13 asynchronous mode or C-bit parity mode. 0 1 M13 asynchronous mode. C-bit parity mode. Data Sheet 82 2001-06-29 PEB 3445 E Register Description D3TCOM DS3 Transmit Command Register Access Address Reset Value : read/write : 04H : 70H 5 4 3 2 1 0 0 7 0 6 TAIC TNrB TXBIT SIDLESAISA SAIS TAIC Transmitted AIC-bit This bit sets the value to be transmitted in the DS3 overhead bit of block 3, subframe 1. This function is available in C-pit parity format only. 0 1 AIC-bit = `0'. AIC-bit = `1'. TNrB Transmitted Nr-bit This bit sets the value to be transmitted in the DS3 overhead bit of block 5, subframe 1. This function is available in C-pit parity format only. 0 1 Nr-bit = `0'. Nr-bit = `1'. TXBIT Transmitted X-bits This bit sets the value to be transmitted in the DS3 overhead bit of block 1, subframes 1 and 2. TXBIT is synchronized to the DS3 multiframe. Both X-bits in a multiframe are guaranteed identical. Software should limit changes to maximum of 1 per second. Note: Setting TXBIT to `0' results in transmission of remote alarm indication even when SIDLE, SAISA or SAIS are set. 0 1 X-bit = `0'. X-bit = `1'. Data Sheet 83 2001-06-29 PEB 3445 E Register Description SIDLE Send DS3 Idle Code This bit enables transmission of the DS3 idle code ('1100' between overhead bits, C-bits all `0's). The X-bits must be set to `1' independently by setting TXBIT to `1'. 0 1 SAISA Normal operation. Send DS3 idle code. Send AIS in DS3 output and on DS3 loop This bit enables transmission of AIS on the DS3 output. If the DS3 is additionally switched to local DS3 loopback mode the DS3 signal including AIS is mirrored to the receiver. The AIS code transmitted depends on D3TCFG.AISC. The X-bits must be set to `1' independently by setting TXBIT to `1'. 0 1 Normal operation. Enable transmission of AIS. SAIS Send AIS at DS3 output This bit enables transmission of AIS on the DS3 output. If the DS3 signal is switched into local DS3 loopback mode the DS3 signal without AIS code is mirrored to the DS3 receiver. The AIS code transmitted depends on D3TCFG.AISC. The X-bits must be set to `1' independently by setting TXBIT to `1'. 0 1 Normal operation. Enable transmission of AIS. Data Sheet 84 2001-06-29 PEB 3445 E Register Description D3TLPB DS3 Transmit Remote DS2 Loopback Register Access Address Reset Value : read/write : 05H : 00H 0 LPB(6:0) 7 0 6 LPB Remote DS2 Loopback Setting LPB(x) enables the remote DS2 loopback of tributary x. In this mode the demultiplexed DS2 tributary is internally looped and multiplexed into the outgoing DS3 signal. 0 1 Normal operation. Enable remote DS2 loopback of tributary x. Data Sheet 85 2001-06-29 PEB 3445 E Register Description D3TLPC DS3 Transmit Loopback Code Insertion Register Access Address Reset Value : read/write : 06H : 00H 0 LPC(6:0) 7 0 6 LPC Send Loopback Setting LPC(x) enables transmission of the loopback code in tributary x of the DS3 signal. The loopback code inserted depends on D3TCFG.LPC. 0 1 Normal operation. Enable transmission of loopback code in tributary x. Data Sheet 86 2001-06-29 PEB 3445 E Register Description D3TAIS DS3 Transmit AIS Insertion Register Access Address Reset Value : read/write : 07H : 00H 0 AIS(6:0) 7 AISE 6 AISE AIS AIS Error Insertion Toggling this bit inserts one `0' in all DS3 tributaries which transmit AIS. Send DS2 Alarm Indication Signal Setting AIS(x) enables insertion of the DS2 alarm indication signal in the outgoing tributary x of the DS3 signal. AIS is an all '1' signal. 0 1 Normal operation. Enable transmission of AIS in tributary x. Data Sheet 87 2001-06-29 PEB 3445 E Register Description D3TFINS DS3 Transmit Fault Insertion Control Register Access Address Reset Value : read/write : 08H : 00H 3 0 0 0 FINSC(3:0) 0 7 0 FINSC Fault Insertion Code. Fault insertion is service affecting and is intended for testing only. Codes are not self clearing, i.e. errors are continuously generated as indicated until bit cleared. A single FEBE, P, CP, or code violation is guaranteed to be inserted if the respective code is written and then immediately cleared. 0 1 2 3 4 5 6 7 8 9 Normal operation (no fault insertion). Insert FEBE event every multiframe (106 sec). Insert P-bit errors every 2nd multiframe (212 sec). Insert CP-bit errors every 2nd multiframe (212 sec). Insert 4 F-bit errors/multiframe (satisfies 3 out of 15 threshold trigger). Insert 5 F-bit errors/multiframe (satisfies 3 out of 7 threshold trigger). Insert 3 M-bit errors/multiframe (caution: receiver can frame on emulator). Force DS3 output to all `0's. Insert B3ZS violation/multiframe (violation of alternate polarity rule). Insert 3 zero string/multiframe (B3ZS code word suppressed). Data Sheet 88 2001-06-29 PEB 3445 E Register Description D3TTUC DS3 Transmit Test Unit Control Register Access Address Reset Value : read/write : 09H : 00H 4 TUDS2(2:0) 3 2 1 TUIM 0 7 EN 6 TUDS1(1:0) EN Enable Test Unit Insertion Setting this bit enables insertion of the test unit data. 0 1 Normal operation. Enable insertion of test unit data. TUDS2 Test Unit DS2 Group This bit field selects the DS2 group the test unit is attached to. Only valid if TUIM is 10B, 01B or 00B. 0..6 Selects DS2 group 0..6. TUDS1 Test Unit DS1 Tributary This bit field selects the DS1 tributary the test unit is attached to. Only valid if TUIM is 00B. The DS2 group is selected via TUDS2. 0..3 DS1/E1 tributary TUIM Bit Error Rate Test Unit (TU) Insertion Mode This bit field selects the interface the test unit is attached to. 00B 01B 10B 11B Insert test stream into DS1/E1 tributary. Insert test stream into DS2 tributary (unframed, bypass M12). Insert test stream into DS2 payload (framed). Insert test stream into DS3 payload (framed). Data Sheet 89 2001-06-29 PEB 3445 E Register Description D3TSDL DS3 Transmit Spare Data Link Register Access Address Reset Value : read/write : 0AH : 01FFH 8 0 0 0 0 0 0 7 6 5 4 3 2 1 0 15 0 DL77 DL75 DL73 DL67 DL65 DL63 DL27 DL25 DL23 Multiframe buffer for spare DL bits transmitted in blocks 3, 5, and 7 of subframes 2, 6, and 7. If enabled, the M13 will generate an interrupt every multiframe to request a refresh of this register. The software must write these registers within 106 sec to avoid an underrun. DL(S)(B) Overhead bit for block B of subframe S These bits store the DL bits to be transmitted in blocks 3, 5, and 7 of subframes 2, 6, and 7. If enabled, the M13 will generate an interrupt every multiframe to request a refresh of this register. Data Sheet 90 2001-06-29 PEB 3445 E Register Description D3RCFG DS3 Receive Configuration Register Access Address Reset Value : read/write : 10H : 0000H 13 12 OD 11 IL 10 9 8 0 6 5 4 3 2 1 0 URD 15 14 CVM ITRCK ITRD STTM ECM FEBM AISX MFM MDIS FFM IRCK IRD Note: M13 mode, Full payload mode, loopback code, and AIS mode are controlled by bits CBP, FPL, LPC, and AISC in register DS3 transmit configuration register D3TCFG. CVM B3ZS Code Word ("00V" or "10V" Acceptance Condition) This bit selects the B3ZS violations alternate polarity to maintain line balance. 0 1 ITRCK Convert all B3ZS codeword patterns to "000" regardless of polarity. Convert codeword only if alternate violation polarity rule is satisfied. Invert Tributary Clock This bit sets the clock edge for data update on the low speed tributaries. 0 1 Update data on the rising edge of RTC(x). Update data on the falling edge of RTC(x). ITRD Invert Tributary Data This bit enables inversion of tributary data. 0 1 No inversion of data provided via RTD(x). Invert data provided via RTD(x). OD Interrupt Open Drain This bit selects the operating mode of the interrupt pin. 0 1 Open Drain. Push-Pull. Data Sheet 91 2001-06-29 PEB 3445 E Register Description IL Interrupt Active Level This bit selects the active level of the interrupt pin. 0 1 STTM Active Low. Active High. Select Transmit Tributary Monitoring for receive test unit This bit selects the DS1/E1 tributary observed by the test unit receiver. The test unit can be connected to the upstream DS1/E1 tributary (DS1/ E1 tributary going towards the DS3 interface) or to the downstream DS1/ E1 tributary (DS1/E1 tributary coming from the DS3 interface). 0 1 Monitor downstream DS1/E1 tributary. Monitor upstream DS1/E1 tributary. ECM Error Counter Mode DS3 errors are counted in background and copied to foreground (error counter registers) when condition selected via ECM is met. 0 1 Counter values are copied to foreground when copy command is executed. See also register DS3COM. The counter values are copied to the foreground register in one second intervals. At the same time the background registers are reset to zero. This operation is synchronous with the periodic one second interrupt which alerts software to read the register. FEBM Far End Block Error (FEBE) Mode This bit selects the event which leads to FEBE indication. It is available in C-bit parity mode only. 0 1 Receive multiframe parity error. Receive multiframe parity error or framing error. AISX AIS X-bit Check Disable This bit disables checking of the X-bit for AIS and idle detection. 0 1 Check X-bit. Disable check of X-bit. Data Sheet 92 2001-06-29 PEB 3445 E Register Description MFM Multiframe Framing Mode This bit selects the M-bit error condition which triggers the DS3 framer to start a new frame search. To enable reframing in case of M-bit errors MDIS must be set to `0'. 0 1 MDIS Start new F-frame search if M-bit errors are detected in two out of four consecutive M-frames. Start new F-frame search if M-bit errors are detected in three out of four consecutive M-frames. Multiframe Reframe Disable This bit disables reframing due to M-bit errors. 0 1 Enable reframe due to M-bit errors. Disable reframe due to M-bit errors. FFM F Framing Mode This bit selects the F-bit error condition which triggers the DS3 framer to start a new frame search. 0 1 A new frame search is started when 3 out of 8 contiguous F-bits are in error. A new frame search is started when 3 out of 16 contiguous F-bits are in error. IRCK Invert Receive Clock This bit sets the clock edge for data sampling. 0 1 Sample data on rising edge of receive clock. Sample data on falling edge of receive clock. IRD Invert Receive Data This bit enables inversion of receive data. 0 1 Receive data is logic high (not inverted). Receive data is logic low (inverted). URD Unipolar Receive Data This bit sets the port mode to dual-rail mode or unipolar mode. 0 1 B3ZS (dual rail data input). Unipolar mode (single rail data input). Data Sheet 93 2001-06-29 PEB 3445 E Register Description D3RCOM DS3 Receive Command Register Access Address Reset Value : read/write : 12H : 00H 4 0 0 3 2 1 0 7 0 C3NC C3C CNCA CCA FRS C3NC Copy DS3 Error Counters Values of DS3 background registers are copied to foreground. Background registers are NOT cleared. Command is self clearing and completes before next register access is possible i.e. software can write command and then immediately read the counters without starting a delay timer. Note: Usage of this function in not recommend in 'One Second' error counter mode (D3RCFG.ECM = `1'). 0 1 No operation. Copy background counters to foreground. C3C Copy and Clear DS3 Error Counters Values of DS3 background registers are copied to foreground. Background registers are cleared. Command is self clearing and completes before next register access is possible i.e. software can write command and then immediately read the counters without starting a delay timer. 0 1 No operation. Copy background counters to foreground. Clear background counters. Note: Usage of this function in not recommend in 'One Second' error counter mode (D3RCFG.ECM = `1'). CNCA Copy Error Counters Only valid for counters which are not operating in `One Second' error counter mode. Values of DS2 and DS3 background registers are copied to foreground. Background registers are NOT cleared. Command is self Data Sheet 94 2001-06-29 PEB 3445 E Register Description clearing and completes before next register access is possible i.e. software can write command and then immediately read the counters without starting a delay timer. 0 1 CCA No operation. Copy background counters to foreground. Copy and Clear DS2/DS3 Error Counters Only valid for counters which are not operating in `One Second' error counter mode. Values of DS2 and DS3 background registers are copied to foreground. Background registers are cleared. Command is self clearing and completes before next register access is possible i.e. software can write command and then immediately read the counters without starting a delay timer. 0 1 No operation. Copy background counters to foreground. Clear background counters. FRS Force Resynchronization This bit enables a new frame search on the DS3 input. The command is self clearing after frame search has begun. 0 1 Normal operation. Force new frame search. Data Sheet 95 2001-06-29 PEB 3445 E Register Description D3RAP DS3 Receive Alarm Timer Parameters Register Access Address Reset Value : read/write : 13H : 00H 5 0 CV(5:0) 0 7 AIS AIS AIS criteria This bits sets the error rate for AIS detection. Declaration of AIS depends on value defined in bit field CV. 0 1 AIS is recognized when the alarm indication signal is received with less than 8 errors per multiframe. AIS is recognized when the alarm indication signal is received with less than 15 errors per multiframe. CV Counter Value This bit specifies the number of frames when the TE3-MUX declares AIS, RED or Idle. 0..63 Counter Value. Data Sheet 96 2001-06-29 PEB 3445 E Register Description D3RIMSK DS3 Receive Interrupt Mask Register Access Address Reset Value : read/write : 14H : 0FFFH 11 0 0 0 10 9 8 7 Nr 6 AIC 5 4 3 2 1 0 15 0 RSDL TSDL LPCS 1SEC XBIT IDLES AISS REDS LOSS FAS This register provides the interrupt mask for DS3 status interrupts and DS3 loopback code interrupts. See register D3RSTAT and D3RLPCS for interrupt conditions. The following definition applies: 1 0 RSDL TSDL LPCS 1SEC Nr AIC XBIT IDLES AISS REDS LOSS FAS The corresponding interrupt will not be generated by the device. The corresponding interrupt will be generated. Mask 'Receive Spare Data Link Transfer Buffer Full' Mask 'Transmit Spare Data Link Transfer Buffer Empty' Mask 'Loopback Code Status' (flagged in D3RLPCS) Mask '1 Second Interrupt' Mask 'Nr-bit Image' (C-bit parity mode only) Mask 'AIC-bit Image' (C-bit parity mode) Mask 'X-bit Image' Mask 'DS3 Idle Signal State' Mask 'DS3 Alarm Indication Signal State' Mask 'DS3 Red Alarm State' Mask 'DS3 Input Signal State' Mask 'DS3 Frame Alignment State' Data Sheet 97 2001-06-29 PEB 3445 E Register Description D3RESIM DS3 Receive Error Simulation Register Access Address Reset Value : read/write : 16H : 00H 4 0 0 FTMR 0 2 ESIMC(2:0) 0 7 0 FTMR Fast Timer This bit enables alarm timer test function (manufacturing test only). 0 1 Normal Operation. Test Operation. DS3 RED/AIS/Idle timer period reduced by 56. DS2 READ/AIS timer period reduced by 24. Second interrupt period reduced to 140 sec ESIMC Error Simulation Code This bit enables error simulation. During error simulation the device generates error interrupts and error status messages. Nevertheless the service is not affected. 0 1 2 3 4 5 6 7 Normal operation (no error simulation). Simulate one F-bit error/multiframe (106 sec). Simulate M-bit error in every other multiframe. Simulate FEBE event/multiframe (106 sec). Simulate P/CP event/multiframe (106 sec). Simulate Loss of DS3 input (all zeros). Simulate B3ZS code violations. Simulate Loss of Receive Clock. Data Sheet 98 2001-06-29 PEB 3445 E Register Description D3RTUC DS3 Receive Test Unit Control Register Access Address Reset Value : read/write : 17H : 00H 4 TUDS2(2:0) 3 2 1 0 7 EN 6 TUDS1(1:0) TURM(1:0) EN Enable Test Unit Receive Clock This bit enables the receive clock of the test unit. The clock speed is dependent on the selected test mode. 0 1 Receive clock disabled. Receive clock enabled. TUDS2 Test Unit DS2 Group This bit field selects the DS2 group the test unit is attached to. Only valid if TURM is 10B, 01B, or 00B. 0..6 Selects DS2 group 0..6. TUDS1 Test Unit DS1/E1 Tributary This bit field selects the DS1/E1 tributary the test unit is attached to. Only valid if TURM is 00B. The DS2 group is selected via TUDS2. 0..3 DS1/E1 tributary TURM Test Unit Receive Mode This bit field selects the interface the test unit is attached to. 00B 01B 10B 11B DS1/E1 tributary DS2 tributary (unframed, bypass M12) DS2 payload (framed) DS3 payload (framed) Data Sheet 99 2001-06-29 PEB 3445 E Register Description D3RSTAT DS3 Receive Status Register Access Address Reset Value : read : 18H : 0001H 13 0 12 11 10 9 8 7 6 5 4 3 2 1 0 15 0 14 0 RSDL TSDL LPCD 1SEC Nr / AIC AICC XBIT IDLES AISS REDS LOSS COFA FAS Each bit in the DS3 framer receive status register declares a specific condition dependent on the selected modes. The following convention applies to the individual bits: 0 1 The named status is not or no longer existing. The named status is currently effective. Except for COFA every bit can be used to generate an interrupt. Interrupts can be masked in register D3RIMSK. RSDL Receive Spare Data Link Buffer Full This bit indicates that the spare data link receive buffer (register D3RSDL) is full. TSDL Transmit Spare Data Link Buffer Empty This bit indicates that the spare data link transmit buffer (register D3TSDL) is empty. LPCD 1SEC Loopback Code Detected This bit indicates changes in register D3RLPCS. 1 Second Flag This bit toggles every second synchronously with the one second interrupt. It can be used by software to synchronize 1 second events when the 'One second interrupt' is masked. Data Sheet 100 2001-06-29 PEB 3445 E Register Description Nr/AICC Nr-bit Image (C-bit parity format only) This bit contains an image of the DS3 frame overhead bit in block 5 of subframe 1. It is updated only if its state persists for 3 multiframes and DS3 frame is aligned. AIC-bit Changed (M13 asynchronous format) This bit indicates a change of the AIC-bit (first C-bit of the first subframe) since the last read of this register. AIC AIC-bit Image (DS3 frame overhead bit in block 3 of subframe 1) This bit contains an image of the DS3 frame overhead bit in block 3 of subframe 1. It is updated only if its state persists for 3 multiframes and DS3 frame is aligned. XBIT X-bit Image (DS3 frame overhead bit in block 1 of subframes 1 and 2) This bit contains an image of the DS3 frame overhead bit in block 1 of subframes 1 and 2. It is updated only if both overhead have the same value, when its state persists for 3 multiframes and when the DS3 frame is aligned. IDLES DS3 Idle Signal State This bit indicates that the idle pattern (framed ...1100... with C-bits='0' in subframe 3 and X-bits='1') was persistent as per alarm timing parameters defined in register D3RAP. Idle is considered active in a multiframe when fewer than 15 errors are detected. At 10-3 error rates, 5 errors per multiframe are typical. The exact time necessary to change the flag could be greater if the FAS flag is not constant. The frame alignment state is integrated by incrementing or decrementing a counter at the end of each multiframe when the FAS flag is set or cleared respectively. AISS DS3 Alarm Indication Signal State This bit indicates the AIS alarm state. AIS can be a framed '..1010..' pattern with C-bits='0' and X-bits='1' or an unframed all `1' pattern. This is determined by D3TCFG.AISC. AIS is considered active in a multiframe when fewer than 15 errors are detected and is declared when it was persistent as per alarm timing parameters defined in register D3RAP. At 10-3 error rates, 5 errors per multiframe are typical. The exact time necessary to change the flag could be greater if the FAS flag is not constant. The frame alignment state is integrated by incrementing or decrementing a counter at the end of each multiframe when the FAS flag is set or cleared respectively. Data Sheet 101 2001-06-29 PEB 3445 E Register Description REDS DS3 Red Alarm State (Loss of Frame Alignment) This bit indicates that red alarm was persistent as per alarm timing parameter defined in register D3RAP. The red alarm flag nominally changes when loss of frame alignment condition persists for either 32 or 128 multiframes. The exact time necessary to change the flag could be greater if the FAS flag is not constant. The frame alignment state is integrated by incrementing or decrementing a counter at the end of each multiframe when the FAS flag set or cleared respectively. LOSS DS3 Input Signal State This bit indicates that the received DS3 bit stream contained at least 175 consecutive `0's. It is deasserted when 59 `1' bits are detected in 175 clocks (1/3 density). Following removal of LOS, a 10 msec guard timer is started. If a new LOS occurs, the release condition is extended so that the 1/3 density condition must persist for at least 10 msec. This prevents chatter and excessive interrupts. COFA Change of Frame Alignment This bit indicates a change of frame alignment event. It is set when the DS3 framer found a new frame alignment and when the new frame position differs from the expected frame position. FAS DS3 Frame Alignment State This bit indicates that the DS3 framer is not aligned. Data Sheet 102 2001-06-29 PEB 3445 E Register Description D3RLPCS DS3 Receive Loopback Code Status Register Access Address Reset Value : read : 1AH : 00H 5 4 3 LPCD(6:0) 2 1 0 7 0 6 LPCD Loopback Detected LPCD(x) indicates that a loopback request was received. A loopback request for tributary x is indicated by inverting one of the 3 C-bits of the xth subframe. The C-bit is determined by D3TCFG.LPC. A command state change must persist for 5 contiguous multiframes before it will be reported. This function is available in M13 asynchronous mode only. 0 1 No loopback code being received Loopback code being received Data Sheet 103 2001-06-29 PEB 3445 E Register Description D3RSDL DS3 Receive Spare Data Link Register Access Address Reset Value : read : 1CH : 01FFH 8 0 0 0 0 0 0 7 6 5 4 3 2 1 0 15 0 DL77 DL75 DL73 DL67 DL65 DL63 DL27 DL25 DL23 DL(S)(B) Overhead Bit for Block B of Subframe S These bits buffer the spare DL bits received in blocks 3, 5, and 7 of subframes 2, 6, and 7. If enabled, the M13 will generate an interrupt every multiframe to synchronize reading of this register. The register must be read within 106 sec to avoid an overrun. Data Sheet 104 2001-06-29 PEB 3445 E Register Description D3RCVE DS3 Receive B3ZS Code Violation Error Counter Access Address Reset Value : read/write : 1EH : 0000H 0 CVE(15:0) 15 CVE(15:0) B3ZS Code Violation Errors Error counter mode (Clear on Read or Errored Second) depends on register D3RCFG.ECM. Register D3RCVE counts line code violations. The error counter will not be incremented during asynchronous state. D3REXZ DS3 Receive Excessive Zeroes Counter Access Address Reset Value : read/write : 2EH : 0000H 0 EXZ(15:0) 15 EXZ(15:0) Excessive Zeroes Error counter mode (Clear on Read or Errored Second) depends on register D3RCFG.ECM. Violations are 3 zero strings. The error counter will not be incremented during asynchronous state. Data Sheet 105 2001-06-29 PEB 3445 E Register Description D3RFEC DS3 Receive Framing Bit Error Counter Access Address Reset Value : read/write : 20H : 0000H 0 FEC(15:0) 15 FEC(15:0) Framing Bit Error Counter Error counter mode (Clear on Read or Errored Second) depends on register D3RCFG.ECM. Count of F-bit and M-bit errors. Errors are not counted in out of frame state. D3RPEC DS3 Receive Parity Error Counter Access Address Reset Value : read/write : 22H : 0000H 0 PE(15:0) 15 PE(15:0) Parity Bit Error Counter Error counter mode (Clear on Read or Errored Second) depends on register D3RCFG.ECM. Count of parity errors (P-bits in DS3 overhead bits). The P-bit is duplicated in the DS3 frame structure but only single error maximum is counted per multiframe. Errors are not counted in out of frame state. Data Sheet 106 2001-06-29 PEB 3445 E Register Description D3RCPEC DS3 Receive Path Parity Error Counter Access Address Reset Value : read/write : 24H : 0000H 0 CPE(15:0) 15 CPE(15:0) Path Parity Error Counter Error counter mode (Clear on Read or Errored Second) depends on register D3RCFG.ECM. Count of path parity errors (CP bits in DS3 C-bit parity overhead bits). CP-bits are triplicated in the DS3 frame structure but only single error maximum is counted per multiframe. Errors are not counted in out of frame state. D3RFEBEC DS3 Receive FEBE Error Counter Access Address Reset Value : read/write : 26H : 0000H 0 FEBE(15:0) 15 FEBE(15:0) FEBE Error Events Error counter mode (Clear on Read or Errored Second) depends on register D3RCFG.ECM. This register counts the occurrence of a received `not all `1's'. FEBE-bits are triplicated in the DS3 frame structure but only one single error maximum is counted per multiframe. Errors are not counted in out of frame state. Data Sheet 107 2001-06-29 PEB 3445 E Register Description D3RINTV Interrupt Vector Register Access Address Reset Value : read : 28H : 00H 5 4 3 2 1 0 7 6 TYPE 00 01 10 0 0 LBR 0 STATUS SR RDL TDL GN(2:0) TU 1S RMI ALLS XDU XPR RPF RME 0 11 Four vectors are defined and differentiated by the type field (bits 6 and 7). The interrupt status information contained in the status field (bits 5 down to 0) is dependent on the type information. TYPE Interrupt Type Information This bit field defines the content of the following interrupt status field. 00 This code defines loopback code changes or status changes of the DS2 or DS3 framer. Subsequently the changes can be read in register D3RINTC or D3RINTL. This code defines general status informations. This code defines interrupts of the Far End Alarm and Control Channel. This code defines interrupts of the C-bit parity Path Maintenance Data Link Channel. 01 10 11 STATUS Status Information The status information is dependent on the value of the type bit field. The following section defines the meaning of the status bits: LBR Loopback Code Status Change This bit indicates a change of received DS3 or DS2 loopback code status. The loopback code status is shown in register D3RINTL. The related port is indicated in bit field GN. Data Sheet 108 2001-06-29 PEB 3445 E Register Description SR Status Register Change This bit indicates a change in DS3 or DS2 status. The status is shown is register D3RINTC. The related port is indicated in bit field GN. GN Group Number This bit field indicates the port where a status change or loopback code change occurred. 0..6 7 RDL Status change of DS2 framer 0..6. Status change of DS3 framer. Receive Spare Data Link Buffer Full This bit indicates that new DL bits have been received in register D3RSDL. If enabled it is generated with every multiframe to synchronize reading of register D3RSDL. TDL Transmit Spare Data Link Buffer Empty This bit indicates that new DL bits shall be written to register D3TSDL. If enabled it is generated with every multiframe to synchronize writing of register D3RSDL. TU Test Unit Status Change This bit indicates a status change of the test unit. Subsequently the status can be read in register D3RINTC. 1S ALLS 1 Second The `One Second' interrupt is generated every second. All Sent The 'All Sent' interrupt is generated, when the last bit of a frame to be transmitted is completely sent out and XFF.XFIFO is empty. XDU Transmit Data Underrun The 'Transmit Data Underrun' interrupt is generated, when the transmit FIFO of the corresponding channel runs out of data during transmission of a frame. The protocol controller terminates the affected frame. XPR Transmit Pool Ready The 'Transmit Pool Ready' interrupt is generated, when a new data block of up to 32 bytes can be written to transmit FIFO. 'Transmit Pool Ready' is the fastest way to access the transmit FIFO. It has to be used for transmission of long frames, back-to-back frames or frames with shared flag. RPF Receive Pool Full This bit is set, when the receive threshold is reached and data has to be read from the receive FIFO. The frame is not yet completely received. Data Sheet 109 2001-06-29 PEB 3445 E Register Description RME Receive Message End This bit is set, when one complete message of length less than 32 bytes or the last part of a frame is stored in the receive FIFO. The number of bytes in RFF.RFIFO can be determined reading the port status register F/PPSR. RMI Receive Message Idle/Incorrect This bit is set, when four flags (FFH) or no eight consecutive `1's are detected within 32 bits. Data Sheet 110 2001-06-29 PEB 3445 E Register Description D3RINTC Interrupt Status Register Access Address Reset Value : read : 2AH : 0000H This register must be read after register D3RINTV and dependent on the content of register D3RINTV it contains a copy of register D3RSTAT, D2RSTAT or TURSTAT. Data Sheet 111 2001-06-29 PEB 3445 E Register Description D3RINTL Interrupt Loopback Code Status Register Access Address Reset Value : read : 2CH : 0000H This register must be read after register D3RINTV and dependent on the content of register D3RINTV this register contains a copy of register D3RLPCS or D2RLPCS. Data Sheet 112 2001-06-29 PEB 3445 E Register Description 7.2.2 DS2 Control and Status Registers D2TSEL DS2 Transmit Group Select Register Access Address Reset Value : read/write : 30H : 00H 2 0 0 0 0 GN(2:0) 0 7 0 Note: This register is an indirect access register, which must be programmed before accessing the register DS2 transmit registers. GN Group Number This bit field selects the DS2 group, which can be accessed via the DS2 transmit registers. Please refer to section "Tributary Mapper" on Page 37 for a detailed description of the tributary mapper and to Page 117 for programming examples. 0..6 7 Tributary Group Number. Spare Line Group Data Sheet 113 2001-06-29 PEB 3445 E Register Description D2TCFG DS2 Transmit Configuration Register Access Address Reset Value : read/write : 31H : 00H 2 0 0 0 0 1 0 E1 7 0 LPC(1:0) LPC Loopback Code This bit selects the C-bit which will be inverted when loopback requests are transmitted. 00 01 10 Invert 1st C-bit. Invert 2nd C-bit. Invert 3rd C-bit. E1 G.747 Select This bit selects the operation mode of the low speed multiplexer. 0 1 Select M12 mode (4 DS1 into DS2). Select ITU-T G.747 mode (3 E1 into DS2). Data Sheet 114 2001-06-29 PEB 3445 E Register Description D2TCOM DS2 Transmit Command Register Access Address Reset Value : read/write : 32H : 00H 4 IAIS(3:0) 3 2 1 0 7 FINSC(1:0) SRA RES IAIS Insert DS1/E1 AIS Setting IAIS(x) enables transmission of the alarm indication signal in tributary x of the DS2 signal. AIS is an all `1' signal. 0 1 Normal operation. Insert AIS in low speed tributary x. FINSC Fault Insertion Code This bit enables transmission of faults for testing purposes. 0 1 2 3 No fault insertion. Insert F-bit errors at low rate (2 out of 5 F-bits). Insert F-bit errors at high rate (2 out of 4 F-bits). Insert M-bit framing bit error (DS1 mode) or P-bit error (ITU-T G.747) SRA Set Remote Alarm This bit enables transmission of the DS3 remote alarm. In DS1 modes remote alarm is transmitted in subframe 4, block 1 overhead bit and in ITU-T G.747 remote alarm is transmitted in bit 2 of "set II". 0 1 Normal operation. Enable transmission of remote alarm. RES ITU-T G.747 Reserved Bit This bit sets the value to be transmitted in the reserved bit of ITU-T G.747 format. 0 1 Transmit reserved bit as '0'. Transmit reserved bit as '1'. Data Sheet 115 2001-06-29 PEB 3445 E Register Description D2TLPC DS2 Transmit DS1/E1 Remote Loopback/Loopback Code Insertion Register Access Address Reset Value : read/write : 33H : 00H 4 R2T(3:0) 3 LPC(3:0) 0 7 R2T DS2 Tributary Receive to Transmit Loop (remote loop) Setting bit R2T(x) enables the remote loop for tributary x where the incoming tributary x is mirrored to the DS2 transmitter. 0 1 Disable remote loop. Enable remote loop. LPC Send Loopback Code for Tributary N Setting LPC(x) enables transmission of the loopback code in tributary x. The loopback code inserted is specified in D2TCFG.LPC. 0 1 Disable transmission of loopback code. Enable transmission of loopback code. Data Sheet 116 2001-06-29 PEB 3445 E Register Description D2TTM0, D2TTM1, D2TTM2, D2TTM3 DS2 Transmit Tributary Map Register Access Address Reset Value : read/write : 34H, 35H, 36H, 37H : 00H 4 0 0 TN(4:0) 0 7 0 TN Tributary Number A (transmit) tributary map register specifies the data and clock source for the seven M12 multiplexers and the four internal spare links (please refer to section "Tributary Mapper" on Page 37 for a detailed description of the tributary mapper). The M12 multiplexer to be programmed is selected via D2TSEL.GN. where GN can be in the range of 0..6. To program the four internal spare links GN must be set to 7. Now each of the four inputs of the selected M12 multiplexer (or the four spare links) can be programmed by the four tributary map registers D2TTM0..3 (D2TTM0 programs the first input, .., D2TTM3 programs the fourth input). This process maps any of the incoming 32 inputs to the selected input of the M12 multiplexer. After reset interfaces 1..32 are mapped to tributaries 1..32. Example (please refer to Figure 7 on page 37): The interface 14 (TTC(14), TTD(14)) shall be connected to tributary 7 (the third input of the second M12 multiplexer). 1. Write 01H to D2TSEL.GN. This command selects the second M12 multiplexer (GN counts from 0..7). 2. Write 0DH (= 13D) to D2TTM2.TN. This command assigns interface 14 (TN counts from 0..31) to the third input of the second M12 multiplexer. Data Sheet 117 2001-06-29 PEB 3445 E Register Description D2RSEL DS2 Receive Group Select Register Access Address Reset Value : read/write : 40H : 00H 2 0 0 0 0 GN(2:0) 0 7 0 Note: This register is an indirect access register, which must be programmed before accessing the register DS2 transmit registers. GN Group Number This bit field selects the DS2 group number, which can be accessed via the DS2 receive registers. Please refer to section "Tributary Mapper" on Page 37 for a detailed description of the tributary mapper and to Page 124 for programming examples. 0..7 Group Number. Data Sheet 118 2001-06-29 PEB 3445 E Register Description D2RCFG DS2 Receive Configuration Register Access Address Reset Value : read/write : 41H : 00H 3 0 0 0 2 1 0 7 0 ECM AAIS MFM FFM Note: ITU-T G.747 mapping and loop back codes are controlled by bits E1 and LPC in the DS3 transmit configuration register D2TCFG. DS1/E1 and loopback codes are controlled by E1 and LPC fields of the D2TCFG register. ECM Error Counter Mode DS2 errors are counted in background and copied to foreground (error counter registers) when condition selected via ECM is met. 0 1 Counter values are copied to foreground when copy command is executed. See also register DS3COM. The counter values are copied to the foreground register in one second intervals. At the same time the background registers are reset to zero. This operation is synchronous with the periodic one second interrupt which alerts software to read the register. AAIS Automatic AIS Insertion This bit enables automatic insertion of AIS in downstream direction if DS2 framer OR DS3 framer is out of frame. 0 1 Disable automatic insertion of AIS. Enable automatic insertion of AIS. MFM Multiframe Framing Mode This bit selects the M-bit error condition which triggers the DS2 framer to start a new frame search. It is valid in DS1 mode only. 0 1 F-frame search started if 3 contiguous multiframes have M-bit errors. Inhibit new F-frame search due to M-bit errors. Data Sheet 119 2001-06-29 PEB 3445 E Register Description FFM F-Framing Mode This bit selects the F-bit error condition which triggers the DS2 framer to start a new frame search. 0 1 A new frame search is started when 2 out of 4 contiguous F-bits are in error. A new frame search is started when 2 out of 5 contiguous F-bits are in error. Data Sheet 120 2001-06-29 PEB 3445 E Register Description D2RCOM DS2 Receive Command Register Access Address Reset Value : read/write : 42H : 00H 4 ESIMC(2:0) 0 0 1 0 7 0 6 C2NC C2C ESIMC Error Simulation Code This bit field enables error simulation. During error simulation the device generates error interrupts and error status messages. Nevertheless the service is not affected. 0 1 2 Normal operation (no error simulation) Simulate 2 receive F-bit errors/multiframe (186 sec) Simulate 2 receive M-bit errors/multiframe (186 sec) (DS-1 mode) Receive parity error/multiframe (133 sec) (ITU-T G.747 mode) Simulate remote alarm Simulate loss of frame (RED alarm timer) Note:This simulation is service affecting if automatic AIS insertion is enabled. 5 6 Simulate AIS (AIS alarm timer) Simulate receive loop command 3 4 C2NC Copy DS2 Error Counters Only valid when D2RCFG.ECM is set to `0'. Values of DS2 background registers are copied to foreground. Background registers are NOT cleared. Command is self clearing and completes before next register access is possible i.e. software can write command and then immediately read the counters without starting a delay timer. 0 1 No operation. Copy background counters to foreground. Data Sheet 121 2001-06-29 PEB 3445 E Register Description C2C Copy and Clear DS2 Error Counters Only valid when D2RCFG.ECM is set to `0'. Values of DS2 background registers are copied to foreground. Background registers are cleared. Command is self clearing and completes before next register access is possible i.e. software can write command and then immediately read the counters without starting a delay timer. 0 1 No operation. Copy background counters to foreground. Clear background counters. Data Sheet 122 2001-06-29 PEB 3445 E Register Description D2RIMSK DS2 Receive Interrupt Mask Register Access Address Reset Value : read/write : 43H : 3FH 5 0 4 3 2 1 0 FAS 7 0 LPCD AISS REDS RES RAS This register provides the interrupt mask for DS2 status interrupts and DS2 loopback code interrupts. See register D2RSTAT and D2RLPCS for interrupt conditions. The following definition applies: 1 0 LPCS AIS REDS RES RAS FAS The corresponding interrupt vector will not be generated by the device. The corresponding interrupt vector will be generated. Mask 'Loopback Code Status' (flagged in D2RLPCS) Mask 'AIS Alarm State' Mask 'Red Alarm State' Mask 'Reserved Bit' Mask 'DS2 Remote Alarm State' Mask 'DS2 Frame Alignment State' Data Sheet 123 2001-06-29 PEB 3445 E Register Description D2RTM0, D2RTM1, D2RTM2, D2RTM3 DS2 Receive Tributary Map Register Access Address Reset Value : read/write : 44H, 45H,46H, 47H : 00H 4 0 0 TN(4:0) 0 7 0 TN Tributary Number A (receive) tributary map register specifies the data and clock source for one of the 32 DS1/E1 outputs (please refer to section "Tributary Mapper" on Page 37 for a detailed description of the tributary mapper). The outputs are divided into eight groups where each group represents four consecutive output ports, i.e. 1..4, 5..8, .. , 29..32. The group to be programmed is selected via D2RSEL.GN. Now each of the four outputs of the selected group can be programmed by the four tributary map registers D2RTM0..3. This process maps any of the incoming 28 tributaries of the DS3 signal or any of the four internal spare links to an output. After reset interfaces 1..32 are mapped to tributaries 1..32. Example (please refer to Figure 7 on page 37): The interface 22 (RTC(22), RTD(22)) shall be connected to the tributary 7 (the third output of the second M12 demultiplexer). 1. Write 05H to D2RSEL.GN. This command selects the output group 5 consisting of the output pins 21..24 and in this case the registers D2RTM0..D2RTM3 represent the output pins 21..24. 2. Write 06H to D2RTM1.TN. This command assigns tributary seven (TN counts from 0..31) to output 22. Data Sheet 124 2001-06-29 PEB 3445 E Register Description D2RLAIS DS2 Receive Local DS1/E1 Loopback/AIS Insertion Register Access Address Reset Value : read : 48H : 00H 4 IAIS(3:0) 3 T2R(3:0) 0 7 IAIS Insert AIS Setting bit x of bit field IAIS(x) enables insertion of AIS in tributary x of the demultiplexed DS2 signal in downstream direction. 0 1 No function. Enable insertion of AIS in tributary x of demultiplexed DS2 tributary. T2R Enable loopback Setting bit x of bit field T2R enables loopback from transmit to receive of tributary x (local loop of DS1/E1 tributary). 0 1 No loopback. Enable loopback from transmit to receive. Data Sheet 125 2001-06-29 PEB 3445 E Register Description D2RSTAT DS2 Receive Status Register Access Address Reset Value : read : 49H : 00H 5 0 4 3 2 1 0 7 0 AISS REDS RES RAS COFA FAS Each bit in the DS2 framer receive status register declares a specific condition dependent on the selected modes. The following convention applies to the individual bits: 0 1 The named status is not or no longer existing. The named status is currently effective. Except for COFA every bit can be used to generate an interrupt. Interrupts can be masked in register D2RIMSK. AISS DS2 AIS Alarm State (unframed all `1's pattern) AIS is considered valid in a multiframe when fewer than 5 zeros are detected. At 10-3 error rates, 1 zero per multiframe is typical. A valid DS2 signal without any bit errors has at least 5 zeros. The AIS flag nominally changes when the AIS condition is persistent as per alarm timing parameters defined in register D2RAP. The exact time necessary to change the flag could be greater in extremely high error rates. The AIS state is integrated by incrementing or decrementing a counter at the end of each multiframe depending on the AIS condition being valid or invalid respectively. REDS DS2 Red Alarm State (loss of frame alignment). The red alarm flag nominally changes when loss of frame alignment condition is persistent as per alarm timing parameters defined in register D2RAP. The exact time necessary to change the flag could be greater if the FAS flag is not constant because the frame alignment state is integrated by incrementing or decrementing a counter at the end of each multiframe when the FAS flag set or cleared respectively. Note that the Data Sheet 126 2001-06-29 PEB 3445 E Register Description framer's verification algorithm is designed to prevent a bouncing FAS flag. RES Reserved Bit This bit indicates the status of bit 3 in set II of ITU-T G.747 mode. Is it updated if the DS2 framer is aligned and when its state persists for at least 8 multiframes. RAS DS2 Remote Alarm State This bit indicates that remote alarm is active. Changes are reported when they persist for 3 multiframes. In DS1 mode changes on Mx bit are reported, in ITU-T G.747 mode changes of bit 1 of set II are reported. COFA Change of Frame Alignment This bit indicates a change of frame alignment event. It is set when the DS2 framer found a new frame alignment and when the new frame position differs from the expected frame position. FAS DS2 Frame Alignment State This bit indicates that the DS2 framer is not aligned. Data Sheet 127 2001-06-29 PEB 3445 E Register Description D2RLPCS DS2 Receive Loopback Code Status Register Access Address Reset Value : read : 4AH : 00H 3 0 0 0 LPCD(3:0) 0 7 0 LPCD(N) Loopback Command Detected LPCD(x) indicates that a loopback request was received. A loopback request for tributary x is indicated by inverting one of the 3 C-bits of the xth subframe. The C-bit is determined by D2TCFG.LPC. A command state change must persist for 5 contiguous multiframes before it will be reported. 0 1 No loopback code being received. Loopback code being received. Data Sheet 128 2001-06-29 PEB 3445 E Register Description D2RAP DS2 Receive Alarm Timer Parameters Access Address Reset Value : read/write : 4BH : 00H 5 CV(5:0) 0 7 AIS 6 CM AIS AIS criteria This bits sets the error rate for AIS detection. Declaration of AIS is specified by bits CM and CV. ITU-T G.747: 0 AIS condition is recognized when the alarm indication signal is received with less than 5 errors in each of 2 consecutive multiframes. AIS condition is recognized when the alarm indication signal is received with less than 9 errors in each of 2 consecutive multiframes. AIS condition is recognized when the alarm indication signal is received with less than 3 errors in 3156 bits. AIS condition is recognized when the alarm indication signal is received with less than 9 errors in 3156 bits. 1 M12 format: 0 1 CM Counter Mode This bit selects the alarm timer mode. If counter mode is set to multiframes (`0') the value in CV determines the number of multiframes after which the TE3-MUX declares AIS or RED. When counter mode is set to `1/2 milliseconds' (`1') the value in CV determines the time in CV x 0.5 ms after which AIS or RED is declared. 0 1 Multiframes. 1/2 Milliseconds. Data Sheet 129 2001-06-29 PEB 3445 E Register Description CV Counter Value Dependent on bit CM the counter value specifies the number of frames or the time in multiples of 0.5 milliseconds when AIS or RED is declared, i.e. setting CV to 20 and CM to `1' sets the alarm integration time to 10 milliseconds. 0..63 Counter Value. Data Sheet 130 2001-06-29 PEB 3445 E Register Description D2RFEC DS2 Receive Framing Bit Error Counters Access Address Reset Value : read/write : 4CH : 0000H 0 FE(15:0) 15 FE(15:0) Framing Bit Errors Error counter mode (Clear on Read or Errored Second) depends on register D2RCFG.ECM. For DS1 mode framing bit errors include F-bit and M-bit errors. For G747 mode, individual bits in the Frame Alignment Signal (FAS) are counted. Errors are not counted in out of frame state. D2RPEC DS2 Receive Parity Bit Error Counter Access Address Reset Value : read/write : 4EH : 0000H 0 PE(15:0) 15 PE(15:0) Parity Errors in ITU-T G.747 mode Error counter mode (Clear on Read or Errored Second) depends on register D2RCFG.ECM. Errors are not counted in out of frame state. Data Sheet 131 2001-06-29 PEB 3445 E Register Description 7.2.3 Test Unit Registers TUTCFG Test Unit Transmit Configuration Register Access Address Reset Value : read/write : 50H : 0000H 13 0 INV 12 FBT(4:0) 8 0 6 LEN(4:0) 2 1 ZS 0 MD 15 0 INV Invert output This bit enables inversion of the test unit output. Bit inversion is done after the zero suppression insertion point. 0 1 No inversion Invert pattern generator output FBT Feedback Tap This bit field sets the feedback tap in pseudorandom pattern mode. PRBS shift register input bit 0 is XOR of shift register bits LEN and FBT. LEN ZS Pattern Generator Length This bit field sets the pattern generator length to 1..32. Enable Zero Suppression This bit enables zero suppression where a '1' bit is inserted at the output if the next 14 bits in the shift register are '0'. 0 1 No zero suppression Zero suppression. MD Generator Mode This bit selects the generator mode of the test unit to be either PRBS or fixed pattern mode. 0 1 Pseudorandom Pattern (PRBS) Fixed Pattern Data Sheet 132 2001-06-29 PEB 3445 E Register Description TUTCOM Test Unit Transmit Command Register Access Address Reset Value : write : 52H : 00H 3 0 0 0 2 1 0 7 0 LDER IN1E STOP STRT Note: All commands are self clearing i.e. user does not have to clear command. The maximum command rate is limited by clock rate of unit under test and the associated synchronization process. Write interval should be > 4 transmit clock periods e.g. 2.6 s for DS1 tributary test or 634 ns for T2 tributary test. LDER Load Error Rate Register This bit loads the value of the error rate register TUTEIR to the test unit transmitter. The command can be given while the transmitter is running. 0 1 IN1E No function. Copy value of register TUTEIR to transmit clock region. Insert One Error in Output This bit enables a single error insertion in the next bit after command was written. 0 1 No function Single error insertion. STOP Stop Pattern Generation. This bit stops the test unit transmitter. When stopped output becomes all '1'. 0 1 No function. Stop pattern generation. Data Sheet 133 2001-06-29 PEB 3445 E Register Description STRT Start Transmitter. This bit starts the test unit transmitter with the parameters defined in register TUTCFG. In fixed pattern mode the pattern needs to be programmed via register TUTFP0/1 prior to starting the transmitter. 0 1 No operation. Start test unit. Data Sheet 134 2001-06-29 PEB 3445 E Register Description TUTEIR Test Unit Transmit Error Insertion Rate Register Access Address Reset Value : read/write : 53H : 00H 3 0 0 0 MTST 2 TXER(2:0) 0 7 0 MTST TXER Manufacturing test. Must be written to `0' for normal operation. Transmit Error Insertion Rate. This bit field determines the error insertion rate of the test unit transmitter. 000 001 010 011 100 101 110 111 No errors 10-1 (1 in 10 (1 in 10-3 (1 in 10-4 (1 in 10-5 (1 in 10-6 (1 in -2 10) 100) 1 000) 10 000) 100 000) 1 000 000) 10-7 (1 in 10 000 000) Data Sheet 135 2001-06-29 PEB 3445 E Register Description TUTFP0 Test Unit Transmit Fixed Pattern Low Word Access Address Reset Value : read/write : 54H : 0000H 0 FP(15:0) 15 FP Fixed Pattern Low Word See description below. TUTFP1 Test Unit Transmit Fixed Pattern High Word Access Address Reset Value : read/write : 56H : 0000H 0 FP(31:15) 15 FP Fixed pattern High Word The 32 bit fixed pattern is distributed over two 16 bit registers and contains the pattern which is transmitted repetitively from bit FP(TUTCFG.LEN) down to FP(0) when test unit is operated in fixed pattern generator mode. Data Sheet 136 2001-06-29 PEB 3445 E Register Description TURCFG Test Unit Receive Configuration Register Access Address Reset Value : read/write : 58H : 0000H 13 0 DAS 12 FBT(4:0) 8 0 6 LEN(4:0) 2 1 ZS 0 MD 15 AIM AIM Auxiliary Interrupt Mode This bit field enables the auxiliary interrupt mask AIM of register TURIMSK. In normal operation and if not masked every status event generates an interrupt event. In auxiliary interrupt mode an individual status event generates one interrupt event and further status events of the same class, i.e. 'Bit Error Detected', are masked via an internal mask. This prevents excessive interrupt floods. See register TURIMSK for further details. 0 1 Normal Operation Auxiliary Interrupt Mode DAS Disable Automatic Synchronization This bit disables automatic resynchronization in case of high bit error rates. If automatic resynchronization is enables the receiver automatically tries to resynchronize to the received test pattern. 0 1 Enable automatic resynchronization. Disable automatic resynchronization. FBT Feedback Tap This bit field sets the feedback tap of the test unit synchronizer (receiver) in pseudorandom pattern mode. Next input to PRBS reference shift register (bit 0) is XOR of shift register bits LEN and FBT. LEN Reference shift register length This bit field sets the length of the receiver's test pattern register. Data Sheet 137 2001-06-29 PEB 3445 E Register Description ZS Enable Zero Suppression This bit enables zero suppression at the test unit receiver. A '1' is expected and inserted at the input if the next 14 bits in the shift register are set to '0'. 0 1 MD No zero suppression. Enable zero suppression. Generator Mode This bit sets the generator mode of the test unit to either PRBS or fixed pattern. 0 1 Pseudorandom Pattern (PRBS) Fixed Pattern Data Sheet 138 2001-06-29 PEB 3445 E Register Description TURCOM Test Unit Receive Command Register Access Address Reset Value : write : 5AH : 00H 5 0 4 3 2 1 0 7 0 FRS RDF RDC CAIM STOP STRT Note: All commands are self clearing i.e. user does not have to clear command. The maximum command rate is limited by clock rate of unit under test and the associated synchronization process. Write interval should be > 4 transmit clock periods e.g. 2.6 s for DS1 tributary test or 634 ns for T2 tributary test. FRS Force resynchronization. This bit forces the receiver to resynchronize to the received bit stream. Only applicable if TURCFG.DAS = '1'. 0 1 RDF No function. Force resynchronization of receiver. Copy Receiver's 32 bit Pattern This bit loads the test units internal receiver pattern to register TURFP in fixed pattern mode. In synchronous state TURFP will be loaded with the pattern received. In asynchronous state TURFP with a 32-bit sample of the last received bit stream. 0 1 No function. Update register TURFP with synchronizer pattern. RDC Copy bit counter and error counter This bit loads the test units internal bit counter and error counter to registers TURBC0,1 and TUREC0,1. Afterwards the bit counter and the error counter is cleared. 0 1 No function. Copy counter. Data Sheet 139 2001-06-29 PEB 3445 E Register Description CAIM Clear Auxiliary Interrupt Masks. This bit resets the internal auxiliary mask. See TURCFG.AIM. 0 1 STOP STRT No operation Clear auxiliary interrupts Stop Receiver Setting this bit stopes the test unit receiver. Start Receiver. This bit loads and starts the test unit receiver with the parameters defined in register TURCFG. 0 1 No operation. Load/Start test unit receiver. Data Sheet 140 2001-06-29 PEB 3445 E Register Description TURERMI Test Unit Receive Error Measurement Interval Register Access Address Reset Value : read/write : 5BH : 00H 3 0 0 0 TST 2 RXMI(2:0) 0 7 0 TST Test Mode This bit enables test of the measurement interval timer. 0 1 Normal operation Auto test of measurement interval function. End of Measurement interrupt should be asserted after approximately 4250 receive clock cycles (if enabled). The lower three bits of register FPAT should be "111". RXMI Receive Error Rate Measurement Interval This bit field defines the measurement interval in terms of input bits for measurement of receive bit error rate. At the end of the measurement window, contents of background error counter are automatically copied to foreground error counter and reset for next measurement interval. An interrupt can be generated at the end of each measurement interval. 000B Max measurement interval of 232-1 001B 103 bits 010B 104 bits 011B 105 bits 100B 106 bits 101B 107 bits 110B 108 bits 111B 109 bits Data Sheet 141 2001-06-29 PEB 3445 E Register Description TURIMSK Test Unit Receive Interrupt Mask Register Access Address Reset Value : read/write : 5CH : 1F1FH 12 0 0 AIM(4:0) 8 0 0 0 4 3 2 1 0 15 0 ERXM BED ALL1 LOS SYN This register provides the interrupt mask for test unit interrupts. See register TURSTAT. The following definition applies: 1 0 ERXM BED ALL1 LOS SYN The corresponding interrupt vector will not be generated by the device. The corresponding interrupt vector will be generated. Mask 'End of Receive Error Rate Measurement' Mask 'Bit Error Detected' Mask 'All `1' Pattern Received' Mask 'Loss of Signal' Mask 'Change in Receiver Synchronization State' AIM flags have same layout as the above five mask but are internal masks that are set automatically following the interrupt in the AIM mode. This mask prevents excessive bus load in error conditions. AIM flags are cleared by the TURCOM.CAIM command. They are "read only" flags in this register. Data Sheet 142 2001-06-29 PEB 3445 E Register Description TURSTAT Test Unit Receive Status Register Access Address Reset Value : read : 5EH : 0001H 8 0 0 0 0 0 0 7 6 5 4 3 LBE 2 A1 1 A0 0 OOS 15 0 INVS LA1 LA0 LOOS EMI INV Inverted Pattern This bit indicates that the received PRBS sequence is inverted. 0 1 Not Inverted. Inverted. LA1 Latched 'Input all '1'' This bit indicates that the condition 'Input all '1'' was active since last status register read. LA0 Latched 'Input all '0'' This bit indicates that the condition 'Input all '0'' was active since last status register read. LOOS Latched Out of Synchronization. This bit indicates that the receiver was out of synchronization since last status register read. EMI End of Measurement Interval This bit indicates that the end of the measurement internal was reached since last read of error counter or that command TURCMD.RDC was given. The results of the bit error rate test are available in register TURBC0,1 and TUREC0,1. This flag is cleared when the error counter is read. Counters will not be overwritten while EMI is '1'. LBE Latched Bit Error Detected Flag. This bit indicates that at least '1' one bit error occurred since last read of this register. It is cleared by status register read. A1 Input all `1's This bit indicates that the input contained all '1' during the last 32 bits. It is reset if at least one '0' occurs in 32 bits. Data Sheet 143 2001-06-29 PEB 3445 E Register Description A0 Input all `0's This bit indicates that the input contained all '0' during the last 32 bits. It is reset if at least one '1' occurs in 32 bits. OOS Receiver Out of Synchronization This bit indicates the status of the test unit synchronizer. Data Sheet 144 2001-06-29 PEB 3445 E Register Description TURBC0 Test Unit Receive Bit Counter Low Word Access Address Reset Value : read : 60H : 0000H 0 BC(15:0) 15 BC(31:0) Bit Counter See description below. TURBC1 Test Unit Receive Bit Counter High Word Access Address Reset Value : read : 62H : 0000H 0 BC(31:16) 15 BC(31:0) Bit Counter BC is a 32 bit counter which is split between two 16 bits registers. It counts receive clock slots when the receiver is enabled. Bits are counted in a background register which is not directly readable. The values are transferred to the two 16 bit foreground (readable) registers and cleared in one of the two ways: 1. Assert command TURCOM.RDC. 2. Automatically at end of measurement interval. The background register is transferred to the foreground register and cleared in the same way as the bit error counter (see previous section). Data Sheet 145 2001-06-29 PEB 3445 E Register Description When the error registers are read in response to the "End of Measurement Interval" interrupt vector, reading this register is not necessary because the measurement interval would be known. However the user could assert command TURCOM.RDC to terminate the measurement interval early and transfer the current bit error count and bit count to the foreground registers (polling mode). Data Sheet 146 2001-06-29 PEB 3445 E Register Description TUREC0 Test Unit Receive Error Counter Low Word Access Address Reset Value : read : 64H : 0000H 0 EC(15:0) 15 EC(31:0) Error Counter See description below. TUREC1 Test Unit Receive Error Counter High Word Access Address Reset Value : read : 66H : 0000H 0 EC(31:16) 15 EC(31:0) Error Counter This 32 bit counter counts receive errors detected when receiver is enabled and in synchronized state. When the 'Bit Error Detected' interrupt is enabled, it will be asserted and then automatically masked when this counter is incremented. Errors are counted in a background register (not directly readable) until: 1. The user asserts command TURCOM.RDC. 2. The end of measurement interval is reached and the last result was read. In both cases the value of the background register is copied to TUREC.EC and the measured values are accessible. An 'End of Data Sheet 147 2001-06-29 PEB 3445 E Register Description Receive Error Rate Measurement' interrupt vector is optionally generated. Data Sheet 148 2001-06-29 PEB 3445 E Register Description TURFP0 Test Unit Receive Fixed Pattern Low Word Access Address Reset Value : read : 68H : 0000H 0 FP(15:0) 15 FP(31:0) Fixed pattern See description below. TURFP1 Test Unit Receive Fixed Pattern High Word Access Address Reset Value : read : 6AH : 0000H 0 FP(31:16) 15 FP(31:0) Fixed Pattern This 32 bit field is distributed over two 16 bit registers and is used in the fixed pattern mode (TURCFG.MD='1'). The TURCOM.RDF command will copy the current state of the receiver's 32 bit pattern generator to this register. If the receiver is synchronized, bits FP(TURCFG.LEN:0) contain the fixed pattern being received. Bit 0 is the most recently received. If not synchronized, the register contains a 32 bit sample of input data. Data Sheet 149 2001-06-29 PEB 3445 E Register Description 7.2.4 Test Unit Framer Registers TUTFCFG Test Unit Transmit Framer Configuration Register Access Address Reset Value : read/write : 70H : 00H 4 0 0 3 2 1 T1E1 0 EF 7 0 OM SRAF FM OM Overwrite mode This bit enables test pattern overwrite mode. While in overwrite mode the generated PRBS sequence will be overwritten by the frame bits. When overwrite is disabled the generated PRBS sequence is placed into the payload field of the DS1/E1 signal. 0 1 Disable overwrite mode. Enable overwrite mode. SRAF Select Remote (Yellow) Alarm Format Setting this bit enables the remote alarm format in DS1 mode. This bit has no function in E1 mode. DS1: F12 0 1 Bit 2 = 0 in every channel. FS bit of frame 12. FM Framer Mode This bit selects the frame format of DS1 or E1 mode. DS1 0 1 E1 0 1 Select double frame format. Select multiframe format. Select ESF (F24) format. Select SF (F12) format. Data Sheet 150 2001-06-29 PEB 3445 E Register Description T1E1 Select DS1/E1 mode This bit switches between DS1 and E1 mode. 0 1 EF Select DS1 mode. Select E1 mode. Enable framer This bit enables the framer for framed DS1/E1 error insertion mode. 0 1 Disable framer. (Unframed bit error rate test) Enable framer. (Framed bit error rate test) Data Sheet 151 2001-06-29 PEB 3445 E Register Description TUTFCOM Test Unit Transmit Framer Command Register Access Address Reset Value : read/write : 71H : 00H 3 0 0 0 2 1 FE 0 RA 7 0 EBIT CRC EBIT Set active E-bit (E1 mode) This bit inserts an active E-bit. EBIT is self clearing. 0 1 Normal operation. Set active E-bit. CRC Insert CRC error This bit enables insertion of CRC error. CRC is self clearing. 0 1 Normal operation. Insert CRC error. FE Insert frame error This bit enables insertion of framing errors. FE is self clearing. 0 1 Normal operation. Insert frame error. RA Send remote alarm This bit enables insertion of remote alarm. 0 1 Disable remote alarm. Send remote alarm. Data Sheet 152 2001-06-29 PEB 3445 E Register Description TURFCFG Test Unit Receive Framer Configuration Register Access Address Reset Value : read/write : 74H : 00H 4 0 0 3 2 1 T1E1 0 EF 7 0 OM RRAM FM OM Overwrite mode This bit enables test pattern overwrite. In overwrite mode the test unit discards the generated bits while the F-bit (DS1 mode) respectively time slot 0 (E1 mode) is received. When overwrite mode is disabled the complete test pattern is expected in the payload of the frame. 0 1 Disable overwrite mode. Enable overwrite mode. RRAM Receive Remote Alarm Mode The condition for remote (yellow) alarm detection in DS1-SF mode can be selected via this bit. Remote alarm detection is flagged in register TURFSTAT.RRA. 0 Detection: Bit 2 = `0' in every speech channel per frame. Release: The alarm will be reset when above conditions are no longer detected. 1 Detection: FS-bit of frame 12 is forced to `1'. Release: The alarm will be reset when above conditions are no longer detected. Data Sheet 153 2001-06-29 PEB 3445 E Register Description FM Framer Mode This bit selects the frame format of DS1 or E1 mode. DS1 0 1 E1 0 1 T1E1 Select double frame format. Select multiframe format. Select ESF (F24) format. Select SF (F12) format. Select DS1/E1 mode This bit switches between DS1 and E1 mode. 0 1 Select DS1 mode. Select E1 mode. EF Enable framer This bit enables the framer for framed DS1/E1 error detection mode. 0 1 Disable framer. (Unframed DS1/E1 bit error rate test) Enable framer. (Framed DS1/E1 bit error rate test) Data Sheet 154 2001-06-29 PEB 3445 E Register Description TURFCOM Test Unit Receive Framer Command Register Access Address Reset Value : read/write : 75H : 00H 0 0 0 0 0 0 0 CC 7 0 CC Copy and Clear Framer Error Counters Values of framer background registers are copied to foreground. Background registers are cleared. Command is self clearing and completes before next register access is possible i.e. software can write command and then immediately read the counters without starting a delay timer. 0 1 No operation. Copy background counters to foreground. Clear background counters. Data Sheet 155 2001-06-29 PEB 3445 E Register Description TURFSTAT Test Unit Receive Framer Status Register Access Address Reset Value : read : 76H : 00H 1 0 0 0 0 0 RRA 0 LFA 7 0 RRA Received Remote Alarm (Yellow Alarm) Condition for receive remote alarm is defined by bit TURFCFG.RRAM. The flag is set after detecting remote alarm (yellow alarm). LFA Loss of Frame Alignment This bit reports loss of frame alignment. In DS1 mode loss of frame alignment is reported when 2 out of 4 framing bit errors are detected. Data Sheet 156 2001-06-29 PEB 3445 E Register Description TURFFEC Test Unit Receive Framing Error Counter Access Address Reset Value : read : 78H : 00H 0 FE(15:0) 15 FE Framing Error Counter The counter will not be incremented during asynchronous state. The error counter is cleared on read. DS1: F12 The counter will be incremented when incorrect FT and FS bits are received. DS1: ESF The counter will be incremented when incorrect FAS bits are received. E1 The counter will be incremented when incorrect FAS words are received. Data Sheet 157 2001-06-29 PEB 3445 E Register Description TURFCEC Test Unit Receive Framer CRC Error Counter Access Address Reset Value : read : 7AH : 00H 0 CR(15:0) 15 CR CRC Errors The counter will not be incremented during asynchronous state. The error counter is cleared on read. DS1: F12 No function. DS1: ESF The counter will be incremented when a multiframe has been received with a CRC error. E1: Doubleframe No function. E1: CRC-4 Multiframe In CRC-4 multiframe mode the counter will be incremented when a submultiframe has been received with a CRC error. Data Sheet 158 2001-06-29 PEB 3445 E Register Description TURFEBC Test Unit Receive Framer Errored Block Counter Access Address Reset Value : read : 7CH : 00H 0 EB(15:0) 15 EB E-Bit counter The counter will not be incremented during asynchronous state. The error counter is cleared on read. DS1 No function. E1: Doubleframe No function. E1: CRC-4 Multiframe The counter will be incremented each time the framer receives a CRC-4 multiframe with Si bit in frame 13 or frame 15 set to zero. Data Sheet 159 2001-06-29 PEB 3445 E Register Description 7.2.5 Far End Alarm and Control Channel (BOM) Registers FRCFG FEAC Receive Configuration Register Access Address Reset Value : read/write : 80H : 0000H 7 0 0 0 0 0 0 0 6 0 0 0 2 1 0 15 0 RTF(1:0) BFE BRM RON RTF RFIFO Threshold Level This bit field sets the threshold of the receive FIFO and is applied to both pages of the receive FIFO. A 'Receive Pool Full' interrupt vector will be generated, when the programmed threshold is reached. The threshold value is given as follows: 00B 01B 10B 11B 32 byte threshold 16 byte threshold 4 byte threshold 2 byte threshold BFE Enable BOM Filter Mode This bit selects, that byte oriented messages have to be filtered. The BOM is reported only if 7 out 10 data is received. 0 1 Disable BOM filter mode. Enable BOM filter mode. BRM BOM Receive Mode This bit switches between continuous and 10 byte packet reception of the receive signalling controller. In 10 byte packet mode a receive FIFO full interrupt is generated after 10 bytes. In continuous reception mode a receive message interrupt is generated when the receive FIFO threshold level is reached. 0 1 Enable 10 byte packets. Enable continuous reception. Data Sheet 160 2001-06-29 PEB 3445 E Register Description RON Receiver On/Off This bit switches the receiver of the Far End Alarm and Control channel to operational (on) or inoperational state (off). It is recommended to issue a 'Receive Message Complete' command after the receiver was initialized (FHND.RMC = `1') in order to clear arbitrary receive FIFO contents. 0 1 Switch receiver off. Switch receiver on. Data Sheet 161 2001-06-29 PEB 3445 E Register Description FRFF FEAC Receive FIFO Register Access Address Reset Value : read : 82H : 0000H 7 RFIFO(15:0) 0 0 0 0 0 0 0 0 RFIFO(7:0) 0 15 RFIFO Receive FIFO Data This bit field contains the first 16 bit word of the receive FIFO of the signalling controller. The receive FIFO itself consists of two pages with 32 bytes. One page is always used in background and is not visible to the microprocessor. The microprocessor sees one FIFO of 32 bytes only. Thus a maximum of 16 words is stored inside the receive FIFO at a time. Data stored in the receive FIFO can be read in 8- or 16-bit accesses. Nevertheless if the port status register indicates an odd byte count the higher byte of the last word is not valid. Port status and FIFO operations can be accessed via register FPSR and register FHND. The first bit received is stored in bit 0. Data Sheet 162 2001-06-29 PEB 3445 E Register Description FXCFG FEAC Transmit Configuration Register Access Address Reset Value : read/write : 84H : 00H 0 0 0 0 0 0 0 XON 7 0 XON Transmitter On/Off This bit switches the transmitter of the facility data link to operational (on) or inoperational state (off). 0 1 Switch transmitter off. Switch transmitter on. Data Sheet 163 2001-06-29 PEB 3445 E Register Description FXFF FEAC Transmit FIFO Access Address Reset Value : write : 86H : 0000H 7 XFIFO(15:0) 0 0 0 0 0 0 0 0 XFIFO(7:0) 0 15 XFIFO Transmit FIFO Data This bit field contains the first 16 bit word of the transmit FIFO of the signalling controller. The transmit FIFO itself consists of two pages with 32 bytes. One page is always used in background and is not visible to the microprocessor. The microprocessor sees one FIFO of 32 bytes only. Thus a maximum of 16 words can be stored inside the transmit FIFO at a time. Data stored in the transmit FIFO can be written in 8- or 16-bit accesses. Nevertheless if the user wants to transfer an odd number of bytes the last access to the transmit FIFO register must be a byte access. Port status and FIFO operations can be accessed via register FPSR and register FHND. Data written to the transmit FIFO is sent starting with bit 0 up to bit 15. Note: The FEAC transmitter does not automatically insert 'FF' between message bytes. The 'FF' bytes have to be provided as part of the message to be transmitted. Thus messages stored in the transmit FIFO must have the following structure: 11111111B0XXXXXX0B. Note: If the transmit FIFO is not completely filled (32 bytes stored in the FIFO page) the transmitter may insert gaps between the packet stored in the current FIFO page and the packet stored in the following FIFO page. Thus in order to sent BOM sequences longer than 32 bytes the transmit FIFO has to filled in blocks of 32 bytes except for the last part of the sequence which may not completely occupy a FIFO page. Data Sheet 164 2001-06-29 PEB 3445 E Register Description FPSR FEAC Port Status register Access Address Reset Value : read : 88H : 2000H 13 12 RBC(4:0) 8 5 BRFO 4 STAT(4:0) 0 15 0 14 XRA XFW XRA Transmit Repeat Active This bit indicates that the transmit signalling controller is operating in repeat mode. 0 1 Normal operation Repeat operation XFW Transmit FIFO Write Enable This bit indicates that data can be written to XFF.XFIFO. This bit is for polling use with the same meaning as the 'Transmit Pool Ready' interrupt vector. RBC Receive Byte Count This bit field indicates the amount of data stored in the receive FIFO. Valid after a 'Receive Message End' interrupt vector is generated. Receive byte count will be cleared, when a 'Receive Message Clear' command is executed via register HND. Note: A zero byte count in combination with a `Receive Pool Full' or 'Receive Message End' interrupt vector means that 32 bytes are available in the receive FIFO. However evaluating RBC is not necessary when the 'Receive Pool Full' interrupt was received. BRFO BOM Receive FIFO Overflow 0 1 No overflow RFF overflow The status word will be cleared after a 'Receive Message Clear' command is issued. Data Sheet 165 2001-06-29 PEB 3445 E Register Description STAT Receive FIFO Status This bit field reports the status of the data stored in the receive FIFO. 00000B BOM Filtered Data Declared This status is reported when `BOM Filtered Data' is enabled, and 7 out of 10 BOM data are received (see also register bit FRCFG.BFE). 00001B BOM Data Available BOM data received is continuously written to the receive FIFO. If '10 byte packet mode' is enabled then this status byte is sent after 10 bytes are written into fifo. Otherwise, whenever the receive fifo is full, this status byte is generated. 00010B 00011B BOM 7E This status reported when the HDLC flag 7EH was detected. BOM Filtered Data Undeclared This is sent only if 'BOM FIltered Mode' is enabled. This is sent whenever 3 valid BOM data is received but all these data is not same as the BOM data for which the status 'BOM Filtered Data declared' was sent earlier. Basically, this means that 7 out of 10 condition is no longer valid. This status is useful, when BOM data pattern changes from one valid pattern to another and BOM Filtered data is enabled. 00100B BOM Idle This message is generated when the receiver was not able to detect a BOM message in the last 32 bits, e.g. the idle pattern (all `1') was sent. Data Sheet 166 2001-06-29 PEB 3445 E Register Description FHND FEAC Handshake Register Access Address Reset Value : write : 8AH : 0000H 8 0 0 0 0 0 0 RMC 0 6 0 5 4 0 0 1 0 15 0 XRES XREP XTF XME Note: Receive command (bit 8) and transmit commands (bit 5 down to bit 0) can not be issued at the same time. Doing so will cause the facility data link to omit the transmit commands. RMC Receive Message Complete This bit is a confirmation from CPU that a data block has been read from RFIFO following a 'Receive Pool Full' or 'Receive Message End' interrupt vector and that the occupied page can now be released. Note: If this bit is set, the low byte (transmit commands) of the register HND is ignored. 0 1 XRES No function Release page of receive FIFO. Transmitter Reset This bit resets the signalling controller transmit. However, the contents of the control register will not be reset. 0 1 Normal operation Transmitter reset XREP Transmission Repeat Setting this bit together with bit XTF indicates that the contents stored in XFF.XFIFO shall be repeatedly transmitted by the TE3-MUX. 0 1 No cyclic transmission. Enable cyclic transmission. XTF Transmit transparent frame Setting this bit indicates that the contents written to XFF.XFIFO shall be transmitted in transparent mode. Data Sheet 167 2001-06-29 PEB 3445 E Register Description 0 1 XME No function Transmit data stored in XFF.XFIFO fully transparent, i.e. without bit stuffing and CRC. Transmit Message End Setting this bit indicates that the last data block written to XFF.XFIFO completes the current message. Data Sheet 168 2001-06-29 PEB 3445 E Register Description Table 8 Far End Alarm and Control Transmit Commands XTF 1 1 XME Function 0 1 Reset Port Start Transmission Send FIFO content in BOM channel. Stop Transmssion Stop transmission of FIFO contents. Transmission ends when content of transmit FIFO has been sent completely. Start Transmission, Enable automatic Repetition Send FIFO content BOM channel. Automatically repeat transmission of FIFO content. Stop Transmission, Disable Automatic Repetition Stop transmission after last byte stored in FIFO has been sent. This command is issued when transmission started by command 'Start Transmission, Enable automatic Repetition' shall be stopped. XRES XREP 1 0 0 0 0 0 1 1 0 0 1 1 1 Data Sheet 169 2001-06-29 PEB 3445 E Register Description FMSK FEAC Interrupt Mask Register Access Address Reset Value : read/write : 8CH : 00H 5 0 4 3 2 1 0 7 0 ALLS XDU XPR RPF RME RMI For each facility data link interrupt vector an interrupt vector generation mask is provided. Generation of an interrupt vector itself does not necessarily result in assertion of the interrupt pin. For description of interrupt concept refer to section "Interrupt Interface" on Page 62. The following definition applies: 1 0 The corresponding interrupt vector will not be generated by the device. The corresponding interrupt vector will be generated. Facility Data Link Interrupt Vector Transmit ALLS XDU XPR RPF RME RMI Mask 'All Sent' Mask ''Transmit Data Underrun' Mask 'Transmit Pool Ready' Mask 'Receive Pool Full' Mask 'Receive Message End' Mask 'BOM Idle' Facility Data Link Interrupt Vector Receive Data Sheet 170 2001-06-29 PEB 3445 E Register Description 7.2.6 C-Bit Path Maintenance (HDLC) Registers PRCFG HDLC Receive Configuration Register Access Address Reset Value : read/write : 90H : 0000H 10 0 0 0 0 9 8 7 6 0 4 3 2 1 0 15 0 RMCP DRRP DMA RTF(1:0) INV RIFTF XCRC CRC RON DIS RMCP RMC Polarity This bit sets the polarity of the RMC signal. 0 1 Set polarity to active low. Set polarity to active high. DRRP DRR Polarity This bit sets the polarity of the DRR signal. 0 1 Set polarity to active low. Set polarity to active high. DMA Activate DMA This bit enables the DMA functionality of the C-bit parity Path Maintenance Data Link receiver. While DMA is active new data is indicated by an asserted DRR signal. The end of a message is indicated by an asserted RMC signal. 0 1 Disable DMA. Enable DMA. RTF RFIFO Threshold Level This bit field sets the threshold of the receive FIFO and is applied to both pages of the receive FIFO. A 'Receive Pool Full' interrupt vector will be Data Sheet 171 2001-06-29 PEB 3445 E Register Description generated, when the programmed threshold is reached. The threshold value is given as follows: 00B 01B 10B 11B INV 32 byte threshold 16 byte threshold 4 byte threshold 2 byte threshold Invert data input from Receive Framer This bit enables data inversion between receive framer and receive signalling controller. 0 1 Disable data Inversion. Enable data inversion. RIFTF Report Interframe Time-fill Change This bit selects, that interframe time-fill changes should be reported. 0 1 Disable IFF status messages. Enable IFF status messages. XCRC Transfer CRC to RFIFO This bit defines, that CRC of incoming data packets shall be transferred to the receive FIFO or not. 0 1 No transfer of CRC to RFIFO. Transfer of CRC to RFIFO. CRCDIS CRC Check Disable This bit enables or disables the CRC check of incoming data packets. 0 1 Enable CRC check. Disable CRC check. RON Receiver On/Off This bit switches the receiver of the facility data link channel to operational (on) or inoperational state (off). It is recommended to issue a 'Receive Message Complete' command after the receiver was initialized (PHND.RMC = `1') in order to clear arbitrary receive FIFO contents. 0 1 Switch receiver off. Switch receiver on. Data Sheet 172 2001-06-29 PEB 3445 E Register Description PRFF HDLC Receive FIFO Register Access Address Reset Value : read : 92H : 0000H 7 RFIFO(15:0) 0 0 0 0 0 0 0 0 RFIFO(7:0) 0 15 RFIFO Receive FIFO Data This bit field contains the first 16 bit word of the receive FIFO of the signalling controller. The receive FIFO itself consists of two pages with 32 bytes. One page is always used in background and is not visible to the microprocessor. The microprocessor sees one FIFO of 32 bytes only. Thus a maximum of 16 words is stored inside the receive FIFO at a time. Data stored in the receive FIFO can be read in 8- or 16-bit accesses. Nevertheless if the port status register indicates an odd byte count the higher byte of the last word is not valid. Port status and FIFO operations can be accessed via register PPSR and register PHND. The first bit received is stored in bit 0. Data Sheet 173 2001-06-29 PEB 3445 E Register Description PXCFG HDLC Transmit Configuration Register Access Address Reset Value : read/write : 94H : 0000H 10 0 0 0 0 9 8 7 0 0 0 0 3 INV 2 DIS CRC 1 SF 0 XON 15 0 TXMEP DRTP DMA TXMEP TXME Polarity This bit sets the polarity of the TXME signal. 0 1 Set polarity to active low. Set polarity to active high. DRTP DRT Polarity This bit sets the polarity of the DRT signal. 0 1 Set polarity to active low. Set polarity to active high. DMA Activate DMA This bit enables the DMA functionality of the C-bit parity Path Maintenance Data Link transmitter. While DMA is active a data request is indicated by an asserted DRT signal. The end of a message is indicated by the user with an asserted TXME signal. 0 1 Disable DMA. Enable DMA. INV Invert Data This bit enables data inversion between transmit signalling controller and transmit framer. 0 1 Disable data Inversion. Enable data inversion. Data Sheet 174 2001-06-29 PEB 3445 E Register Description DISCRC Disable CRC This bit enables CRC generation and transmission on transmission of HDLC packets. 0 1 SF Enable CRC generation. Disable CRC generation. Shared Flags This bit enables transmission of protocol data with shared flags. 0 1 Disable shared flags. Enable shared flags. XON Transmitter On/Off This bit switches the transmitter of the facility data link to operational (on) or inoperational state (off). 0 1 Switch transmitter off. Switch transmitter on. Data Sheet 175 2001-06-29 PEB 3445 E Register Description PXFF HDLC Transmit FIFO Register Access Address Reset Value : write : 96H : 0000H 7 XFIFO(15:0) 0 0 0 0 0 0 0 0 XFIFO(7:0) 0 15 XFIFO Transmit FIFO Data This bit field contains the first 16 bit word of the transmit FIFO of the signalling controller. The transmit FIFO itself consists of two pages with 32 bytes. One page is always used in background and is not visible to the microprocessor. The microprocessor sees one FIFO of 32 bytes only. Thus a maximum of 16 words can be stored inside the transmit FIFO at a time. Data stored in the receive FIFO can be written in 8- or 16-bit accesses. Nevertheless if the user wants to transfer an odd number of bytes the last access to the transmit FIFO register must be a byte access. Port status and FIFO operations can be accessed via register PPSR and register PHND. Data written to the transmit FIFO is sent starting with bit 0 up to bit 15. Data Sheet 176 2001-06-29 PEB 3445 E Register Description PPSR HDLC Port Status register Access Address Reset Value : read : 98H : 2000H 13 XFW 12 RBC(4:0) 8 7 6 5 0 4 STAT(4:0) 0 15 0 14 0 XFW Transmit FIFO Write Enable This bit indicates that data can be written to XFF.XFIFO. This bit is for polling use with the same meaning as the 'Transmit Pool Ready' interrupt vector. RBC Receive Byte Count This bit field indicates the amount of data stored in the receive FIFO. Valid after a 'Receive Message End' interrupt vector is generated. Receive byte count will be cleared, when a 'Receive Message Clear' command is executed via register HND. Note: A zero byte count in combination with a `Receive Pool Full' or 'Receive Message End' interrupt vector means that 32 bytes are available in the receive FIFO. However evaluating RBC is not necessary when the 'Receive Pool Full' interrupt was received. Data Sheet 177 2001-06-29 PEB 3445 E Register Description STAT Receive FIFO Status This bit field reports the status of the data stored in the receive FIFO. 00000B Valid HDLC Frame This status is reported whenever a valid frame with valid CRC was received. 00001B Receive Data Overflow This status indicates a receive buffer overflow while the frame was received. 00010B 00011B 00100B 00101B Receive Abort Indicates a frame which was aborted while being received. Not Octet The frame length is not a multiple of eight bits. CRC Error HDLC frame was received with CRC error. Channel Off This status is generated when the receiver was disabled while a frame was being received. It reports the first '7E' flag which was received after the receiver was disabled. Data Sheet 178 2001-06-29 PEB 3445 E Register Description PHND HDLC Handshake Register Access Address Reset Value : write : 9AH : 0000H 8 0 0 0 0 0 0 RMC 0 6 5 4 0 0 2 XHF 1 0 0 XME 15 0 ABORT XRES Note: Receive command (bit 8) and transmit commands (bit 5 down to bit 0) can not be issued at the same time. Doing so will cause the facility data link to omit the transmit commands. RMC Receive Message Complete This bit is a confirmation from CPU that a data block has been read from RFIFO following a 'Receive Pool Full' or 'Receive Message End' interrupt vector and that the occupied page can now be released. Note: If this bit is set, the low byte (transmit commands) of the register HND is ignored. 0 1 ABORT No function Release page of receive FIFO. Abort Frame Setting this bit aborts HDLC frames which are transmitted. 0 1 Normal operation Abort HDLC frame. XRES Transmitter Reset This bit resets the signalling controller transmit. However, the contents of the control register will not be reset. 0 1 Normal operation Transmitter reset Data Sheet 179 2001-06-29 PEB 3445 E Register Description XHF Transmit HDLC frame Setting this bit indicates that the contents written to XFF.XFIFO shall be transmitted as HDLC frame. If data written to XFF.XFIFO completes a HDLC frame, bit XME must be set together with XHF in order to generate CRC and flag. 0 1 XME No function Transmit data stored in XFF.XFIFO in HDLC format. Transmit Message End Setting this bit indicates that the last data block written to XFF.XFIFO completes the current frame. The signalling controller terminates the transmission properly by appending CRC and the closing flag to the data sequence. Table 9 XRES 1 0 XHF 1 Path Maintenance Transmit Commands XME Function 0 Reset Port Start Transmission Send FIFO content. This command has to be issued in case frames are longer than 32 bytes. In case frames length is equal to or smaller than 32 bytes the command `End Transmission' is sufficient. End Transmission Send FIFO content. CRC (if enabled) and flag are sent after the last byte which was stored in the transmit FIFO was sent. 0 1 1 Data Sheet 180 2001-06-29 PEB 3445 E Register Description PMSK Interrupt Mask Register Access Address Reset Value : read/write : 9CH : 00H 5 0 4 3 2 1 0 0 7 0 ALLS XDU XPR RPF RME For each facility data link interrupt vector an interrupt vector generation mask is provided. Generation of an interrupt vector itself does not necessarily result in assertion of the interrupt pin. For description of interrupt concept refer to section "Interrupt Interface" on Page 62. The following definition applies: 1 0 The corresponding interrupt vector will not be generated by the device. The corresponding interrupt vector will be generated. Facility Data Link Interrupt Vector Transmit ALLS XDU XPR RPF RME Mask 'All Sent' Mask ''Transmit Data Underrun' Mask 'Transmit Pool Ready' Mask 'Receive Pool Full' Mask 'Receive Message End' Facility Data Link Interrupt Vector Receive Data Sheet 181 2001-06-29 PEB 3445 E Electrical Characteristics 8 8.1 Electrical Characteristics Important Electrical Requirements Both VDD3 and VDD25 can take on any power-on sequence. Within 50 milliseconds of power-up the voltages must be within their respective absolute voltage limits. At powerdown, within 50 milliseconds of either voltage going outside its operational range, both voltages must be returned below 0.1V. 8.2 Table 10 Parameter Absolute Maximum Ratings Absolute Maximum Ratings Symbol Limit Values min max 85 125 -65 -0.4 125 VDD3+0.4 C C C V -40 Unit Ambient temperature under bias Junction temperature under bias Storage temperature Voltage on any pin with respect to ground TA TJ Tstg VS Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Data Sheet 182 2001-06-29 PEB 3445 E Electrical Characteristics 8.3 DC Characteristics a) Power Supply Pins Table 11 Parameter Core Supply Voltage I/O Supply Voltage Core supply current VDD25 I/O supply current VDD3 operational DC Characteristics Symbol Limit Values min. typ. 2.5 3.3 75 max. 2.75 3.6 100 100 2.375 3.0 Unit Test Condition V V mA A VDD25 VDD3 ICC25 power down ICCPD25 (no clocks) operational power down (no clocks) ICC3 ICCPD3 45 70 200 mA A Inputs at VSS/ VDD3 No output loads. VDD25=VDD3=max Input leakage for each pin: Input leakage low Input leakage high Input leakage low bscan Input leakage high bscan Power Dissipation b) Interface Pins Table 12 IIL IIH IIIL_BS IIIH_BS P -1 5 -200 5 340 A Vin=0V; Vin=3.6V; Vin=0V; Vin=3.6V; mW DC Characteristics TA = -40 to 85C, VDD3 = 3.3 V 0.3 V, VDD25 = 2.5 V + 0.25 V - 0.125 V, VSS = 0 V Parameter L-input voltage H-input voltage L-output voltage H-output voltage Symbol Limit Values min. max. 0.8 VDD3+0.4 0.45 2.4 V V V V -0.4 2.0 Unit Test Condition VIL VIH VOL VOH IQL = 2 mA IQH = -400 A Data Sheet 183 2001-06-29 PEB 3445 E Electrical Characteristics 8.4 AC Characteristics TA = -40 to 85C, VDD3 = 3.3 V 0.3 V, VDD25 = 2.5 V + 0.25 V - 0.125 V, VSS = 0 V Inputs are driven to 2.4 V for a logical `1' and to 0.4 V for a logical `0'. Timing measurements are made at 2.0 V for a logical `1' and at 0.8 V for a logical `0'. The AC testing input/output waveforms are shown below. * 2.4 2.0 test points 0.8 0.45 0.8 2.0 Device Under Test Cload = 50pF Figure 23 Input/Output Waveform for AC Tests Data Sheet 184 2001-06-29 PEB 3445 E Electrical Characteristics 8.4.1 8.4.1.1 * Local Microprocessor Interface Timing Intel Bus Interface Timing P Read Cycle LA 20 21 LBHE 20 21 LCS 28 29 LRD 32 30 31 LD P Write Cycle LA 20 21 LBHE 20 21 LCS 28 29 LWR 33 34 LD Figure 24 Intel Demultiplexed Bus Timing Data Sheet 185 2001-06-29 PEB 3445 E Electrical Characteristics * P R e a d C y c le 24 25 LALE LBH E 22 23 LC S 28 29 LR D 32 22 23 30 31 LA LD P W rite C y c le 24 25 LALE LBH E 22 23 LC S 28 29 LW R 22 23 33 34 LA LD Figure 25 Intel Multiplexed Bus Timing Data Sheet 186 2001-06-29 PEB 3445 E Electrical Characteristics 38 39 LRD x LCS LWR x LCS Figure 26 * Read, Write Control Interval in Demultiplexed Bus Mode 38 39 LRD x LCS LWR x LCS Figure 27 Table 13 No. 20 21 22 23 24 25 28 29 30 31 32 33 34 38 39 Read, Write Control Interval in Multiplexed Bus Mode Intel Bus Interface Timing Limit Values min. max. ns ns ns ns ns ns ns ns 20 5 100 20 5 60 100 ns ns ns ns ns ns ns 10 0 10 5 15 10 10 0 Unit Parameter LA, LBHE to LRD, LWR setup time LA, LBHE to LRD, LWR hold time LA, LBHE to LALE falling setup time LA, LBHE to LALE falling hold time LALE minimum high time LALE falling to LRD, LWR setup time LCS to LRD, LWR setup time LCS to LRD, LWR hold time LRD low to LD active delay LRD high to LD float delay LRD low to LD valid delay LD to LWR setup time LD to LWR hold time Read, Write inactive control interval Read, Write active control interval Data Sheet 187 2001-06-29 PEB 3445 E Electrical Characteristics 8.4.1.2 * Motorola Bus Interface Timing P Read Cycle LA 40 41 LBLE 40 41 LRDWR 48 49 LCS 50 51 LDS 54 52 53 LD P Write Cycle LA 40 41 LBLE 40 41 LRDWR 48 49 LCS 50 51 LDS 55 56 LD Figure 28 Motorola Demultiplexed Bus Timing Data Sheet 188 2001-06-29 PEB 3445 E Electrical Characteristics * P Read Cycle 44 LALE LBLE 42 43 LRDWR 45 48 49 LCS 50 51 LDS 54 42 43 52 53 LA LD P Write Cycle 44 LALE LBLE 42 43 LRDWR 45 48 49 LCS 50 51 LDS 42 43 55 56 LA LD Figure 29 Motorola Multiplexed Bus Timing Data Sheet 189 2001-06-29 PEB 3445 E Electrical Characteristics * 58 59 LCS x LDS Figure 30 Read, Write Control Interval in Demultiplexed Bus Mode LALE 59 58 LCS x LDS Figure 31 Table 14 No. 40 41 42 43 44 45 48 49 50 51 52 53 54 55 56 58 59 Read, Write, ALE Control Interval in Multiplexed Bus Mode Motorola Bus Interface Timing Limit Values min. max. ns ns ns ns ns ns ns ns ns ns 20 5 100 20 5 60 100 ns ns ns ns ns ns ns 10 0 10 5 15 10 10 5 10 0 Unit Parameter LA to LDS setup time LA to LDS hold time LA to LALE falling setup time LA to LALE falling hold time LALE minimum high time LALE falling to LCS setup time LRDWR to LDS setup time LRDWR to LDS hold time LCS to LDS setup time LCS to LDS hold time LDS low to LD active delay LDS high to LD float delay LDS low to LD valid delay LD to LDS setup time LD to LDS hold time Read, Write inactive control interval Read, Write active control interval Data Sheet 190 2001-06-29 PEB 3445 E Electrical Characteristics 8.4.2 8.4.2.1 DMA Interface Signals DMA Receive Timing LRD1 LDS2 60 DRR3 61 62 RMC4 Figure 32 Note: 1 2 3 4 DMA Receive Timing Intel Mode Motorola Mode DRR is asserted asynchronously as soon as there is data in the receive FIFO. RMC is asserted when the last data belonging to a message was read. DMA Receive Timing Limit Values min. 60 61 62 LRD, LDS inactive to DRR inactive delay LRD, LDS inactive to RMC active delay LRD, LDS inactive to RMC inactive delay max. ns ns ns Unit Table 15 No. Parameter Data Sheet 191 2001-06-29 PEB 3445 E Electrical Characteristics 8.4.2.2 DMA Transmit Timing LWR1 LDS2 65 DRT3 66 67 TXME4 Figure 33 Note: 1 2 3 4 DMA Transmit Timing Intel Mode Motorola Mode DRT is asserted asynchronously as soon as there is free space in the transmit FIFO. TXME has to be asserted while the last byte of a message is written to the transmit FIFO. DMA Transmit Timing Limit Values min. 65 66 67 LRD, LDS inactive to DRT inactive delay TXME to LDS setup time TXME to LDS hold time 20 5 max. ns ns ns Unit Table 16 No. Parameter Data Sheet 192 2001-06-29 PEB 3445 E Electrical Characteristics 8.4.3 8.4.3.1 * Serial Interface Timing DS3 Serial Interface Timing 100 101 102 TCLK44 RCLK44 103 104 Figure 34 Table 17 No. 100 101 102 103 104 Clock Input Timing Clock Input Timing Limit Values min. max. MHz ns ns 2 2 ns ns nom. 44.736 7.5 7.5 Unit Parameter Clock period Clock high timing Clock low timing Clock fall time Clock rise time Data Sheet 193 2001-06-29 PEB 3445 E Electrical Characteristics * TCLK44 RCLK44 (Note 1) TCLKO44 110 110 Figure 35 Note: 1. * DS3 Transmit Cycle Timing Actual clock reference depends on selected clock mode: TCLKO44 (Note 2) TCLKO44 (Note 3) 111 TD44, TD44P/N Figure 36 Note: 2. 3. DS3 Transmit Data Timing Timing for transmit data which is updated on the rising edge of TCLKO44. Timing for transmit data which is updated on the falling edge of TCLKO44. DS3 Transmit Cycle Timing Limit Values min. max. 15 5 ns ns 2 0 Unit Table 18 No. 110 111 Parameter RCLK44, TCLK44 to TCLKO44 delay TCLKO44 to TD44, TD44P/TD44N delay Data Sheet 194 2001-06-29 PEB 3445 E Electrical Characteristics * RCLK44 (Note 1) RCLK44 (Note 2) 130 131 RD44, RD44P/N Figure 37 Note: 1. 2. DS3 Receive Cycle Timing Timing for data which is sampled on the rising edge of the receive clock. Timing for data which is sampled on the falling edge of the receive clock. DS3 Receive Cycle Timing Limit Values min. max. ns ns 5 5 Unit Table 19 * No. 130 131 Parameter RD44, RD44P, RD44N to RCLK44 setup time RD44, RD44P, RD44N to RCLK44 hold time Data Sheet 195 2001-06-29 PEB 3445 E Electrical Characteristics 8.4.3.2 * Overhead Bit Timing TOVHCK 150 TOVHSYN (Output Mode)) 153 154 TOVHD 155 156 TOVHDEN Figure 38 * DS3 Transmit Overhead Timing TCLKO44 151 152 TOVHSYN (Input mode) Figure 39 Table 20 No. 150 151 152 153 154 155 156 DS3 Transmit Overhead Synchronization Timing DS3 Transmit Overhead Timing Limit Values min. max. 75 7 7 25 5 25 5 ns ns ns ns ns ns ns Unit Parameter TOVHCK to TOVHSYN delay TOVHSYN to TCLKO44 setup time TOVHSYN to TCLKO44 hold time TOVHD to TOVHCK setup time TOVHD to TOVHCK hold time TOVHDEN to TOVHCK setup time TOVHDEN to TOVHCK hold time Data Sheet 196 2001-06-29 PEB 3445 E Electrical Characteristics * ROVHCK 157 ROVHSYN 158 ROVHD Figure 40 Table 21 No. 157 158 DS3 Receive Overhead Timing DS3 Receive Overhead Timing Limit Values min. max. 75 75 ns ns Unit Parameter ROVHCK to ROVHSYN delay ROVHCK to ROVHD delay Data Sheet 197 2001-06-29 PEB 3445 E Electrical Characteristics 8.4.3.3 * Stuff Bit Timing TSBCK 160 161 TSBD Figure 41 Table 22 No. 160 161 * DS3 Transmit Stuff Bit Timing DS3 Transmit Stuff Timing Limit Values min. max. ns ns 25 5 Unit Parameter TSBD to TSBCK setup time TSBD to TSBCK hold time RSBCK 162 RSBD Figure 42 Table 23 No. 162 DS3 Receive Stuff Bit Timing DS3 Receive Stuff Bit Timing Limit Values min. max. 75 ns Unit Parameter RSBCK to RSBD delay Data Sheet 198 2001-06-29 PEB 3445 E Electrical Characteristics 8.4.3.4 * DS1/E1 Interface Timing 170 171 172 TTC(x) 173 174 Figure 43 Table 24 No. DS1/E1 Transmit Clock Timing DS1/E1 Transmit Clock Timing Limit Values min. typ max. Unit Parameter Interface operated in E1 Mode 170 171 172 173 174 170 171 172 173 174 Clock period Clock high timing Clock low timing Clock fall time Clock rise time Clock period Clock high timing Clock low timing Clock fall time Clock rise time 2.048 MHz 50 ppm 100 100 10 10 1.544 MHz 130 ppm 100 100 10 10 ns ns ns ns ns ns ns ns Interface operated in DS1 Mode Data Sheet 199 2001-06-29 PEB 3445 E Electrical Characteristics * TTC(x) (Note 1) TTC(x) (Note 2) 175 176 TTD(x) Figure 44 Note: 1. 2. DS1/E1 Transmit Data Timing Timing for transmit data sampled on the rising edge of TTC(x). Timing for transmit data sampled on the falling edge of TTC(x). DS1/E1 Transmit Data Timing Limit Values min. max. ns ns 25 75 Unit Table 25 No. 175 176 Parameter TTD(x) to TTC(x) setup time TTD(x) to TTC(x) hold time Data Sheet 200 2001-06-29 PEB 3445 E Electrical Characteristics * 180 181 182 RTC(x) Figure 45 Table 26 No. DS1/E1 Receive Clock Timing DS1/E1 Receive Clock Timing Limit Values min. typ max. 2056 335 1900 1587 495 1275 ns ns ns ns ns ns Unit Parameter Interface operated in E1 Mode 180 181 182 180 181 182 Clock period Clock high timing Clock low timing Clock period Clock high timing Clock low timing 469 156 312 625 310 310 Interface operated in DS1 Mode Data Sheet 201 2001-06-29 PEB 3445 E Electrical Characteristics * RTC(x) (Note 1) RTC(x) (Note 2) 185 RTD(x) Figure 46 Note: 1. 2. DS1/E1 Receive Data Timing Timing for receive data updated on the rising edge of RTC(x). Timing for receive data updated on the falling edge of RTC(x). DS1/E1 Receive Data Timing Limit Values min. max. 75 ns 25 Unit Table 27 No. 185 Parameter RTC(x) to RTD(x) delay Data Sheet 202 2001-06-29 PEB 3445 E Electrical Characteristics 8.4.3.5 * DS3 System Interface Timing 190 191 192 RTC(1) TTC(1) Figure 47 Table 28 No. 190 191 192 DS3 System Clock Timing DS3 System Clock Timing Limit Values min. typ 22.35 7.5 7.5 max. 44.7 ns ns ns Unit Parameter Clock period Clock high timing Clock low timing TTC(1) 195 196 TTD(1) Figure 48 Table 29 No. 195 196 DS3 System Transmit Data Timing DS3 System Transmit Data Timing Limit Values min. max. ns ns 7 5 Unit Parameter TTD(1) to TTC(1) setup time TTD(1) to TTC(1) hold time Data Sheet 203 2001-06-29 PEB 3445 E Electrical Characteristics RTC(1) 198 RTD(1) Figure 49 Table 30 No. 198 DS3 System Receive Data Timing DS3 System Receive Data Timing Limit Values min. max. 7 ns -5 Unit Parameter RTC(1) to RTD(1) delay Data Sheet 204 2001-06-29 PEB 3445 E Electrical Characteristics 8.4.4 * JTAG Interface Timing TRST 200 201 202 TCK 203 204 TMS 205 206 TDI 207 TDO Figure 50 Table 31 No. 200 201 202 203 204 205 206 207 JTAG Interface Timing JTAG Interface Timing Limit Values min. TCK period TCK high time TCK low time TMS setup time TMS hold time TDI setup time TDI hold time TDO valid time 120 60 60 20 20 20 20 50 max. ns ns ns ns ns ns ns ns Unit Parameter Data Sheet 205 2001-06-29 PEB 3445 E Electrical Characteristics 8.4.5 * Reset Timing power-on VDD3 and VDD25 are up and in their respective limits VDD3 VDD25 220 RST Figure 51 Table 32 No. 220 Reset Timing Reset Timing Limit Values min. RST pulse width 1 max. s Unit Parameter Data Sheet 206 2001-06-29 PEB 3445 E Package Outline 9 Package Outline Data Sheet 207 2001-06-29 PEB 3445 E Package Outline Data Sheet 208 2001-06-29 PEB 3445 E Package Outline Data Sheet 209 2001-06-29 PEB 3445 E Package Outline Data Sheet 210 2001-06-29 Total Quality Management Qualitat hat fur uns eine umfassende Bedeutung. Wir wollen allen Ihren Anspruchen in der bestmoglichen Weise gerecht werden. Es geht uns also nicht nur um die Produktqualitat - unsere Anstrengungen gelten gleichermaen der Lieferqualitat und Logistik, dem Service und Support sowie allen sonstigen Beratungs- und Betreuungsleistungen. Dazu gehort eine bestimmte Geisteshaltung unserer Mitarbeiter. Total Quality im Denken und Handeln gegenuber Kollegen, Lieferanten und Ihnen, unserem Kunden. Unsere Leitlinie ist jede Aufgabe mit Null Fehlern" zu losen - in offener Sichtweise auch uber den eigenen Arbeitsplatz hinaus - und uns standig zu verbessern. Unternehmensweit orientieren wir uns dabei auch an top" (Time Optimized Processes), um Ihnen durch groere Schnelligkeit den entscheidenden Wettbewerbsvorsprung zu verschaffen. Geben Sie uns die Chance, hohe Leistung durch umfassende Qualitat zu beweisen. Wir werden Sie uberzeugen. Quality takes on an allencompassing significance at Semiconductor Group. For us it means living up to each and every one of your demands in the best possible way. So we are not only concerned with product quality. We direct our efforts equally at quality of supply and logistics, service and support, as well as all the other ways in which we advise and attend to you. Part of this is the very special attitude of our staff. Total Quality in thought and deed, towards co-workers, suppliers and you, our customer. Our guideline is "do everything with zero defects", in an open manner that is demonstrated beyond your immediate workplace, and to constantly improve. Throughout the corporation we also think in terms of Time Optimized Processes (top), greater speed on our part to give you that decisive competitive edge. Give us the chance to prove the best of performance through the best of quality - you will be convinced. http://www.infineon.com Published by Infineon Technologies AG |
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