 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ICX074AL Diagonal 8mm (Type 1/2) Progressive Scan CCD Image Sensor with Square Pixel for EIA B/W Video Cameras Description The ICX074AL is an interline CCD solid-state image sensor suitable for EIA black-and-white video cameras. Progressive scan allows all pixels signals to be output independently within approximately 1/60 second. This chip features an electronic shutter with variable charge-storage time which makes it possible to realize full-frame still image without mechanical shutter. Individual pixels in a square matrix make this device suitable for image input and processing applications. High sensitivity and low dark current are achieved through the adoption of HAD (Hole-Accumulation Diode) sensors. Features * Progressive scan allows individual readout of the image signals from all pixels. * High vertical resolution (480TV-lines) still picture without mechanical shutter. * Square pixel unit cell * VGA format-compatible * High resolution, high sensitivity, low dark current * Continuous variable-speed shutter * Low smear * Excellent antiblooming characteristics * Reset gate: 5V drive (bias: no adjustment) Device Structure * Image size: * Number of effective pixels: * Total number of pixels: * Interline CCD image sensor * Chip size: * Unit cell size: * Optical black: * Number of dummy bits: * Substrate material: 22 pin DIP (Cer-DIP) Pin 1 2 V 8 2 Pin 12 H 31 Optical black position (Top View) Diagonal 8mm (Type 1/2) 659 (H) x 494 (V) approx. 330K pixels 692 (H) x 504 (V) approx. 350K pixels 8.10mm (H) x 6.33mm (V) 9.9m (H) x 9.9m (V) Horizontal (H) direction: Front 2pixels, rear 31pixels Vertical (V) direction: Front 8pixels, rear 2pixels Horizontal 16 Vertical 5 Silicon Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E94478H99 ICX074AL Block Diagram and Pin Configuration (Top View) VHOLD VOUT1 CGG2 GND V2 V3 HIS 2 11 10 9 8 7 6 5 4 3 Vertical Register Note) Horizontal Register 1 Horizontal Register 2 HIG1 1 VOUT2 CGG1 V1 Note) : Photo sensor 12 13 14 15 16 17 18 19 20 21 22 HHG1 HHG2 Pin Description Pin No. Symbol 1 2 3 4 5 6 7 8 9 10 11 HIG1 HIS V3 V2 V1 VHOLD GND CGG1 VOUT1 CGG2 VOUT2 Test pin 2 Test pin 2 Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register final stage accumulation clock GND Output amplifier 1 gate 1 decoupling capacitor Signal output 1 Output amplifier 2 gate 1 decoupling capacitor Signal output 2 Description Pin No. Symbol 12 13 14 15 16 17 18 19 20 21 22 VDD RG VL SUB H1 H2 HHG1 HHG2 HIG2 POG VOG Description Supply voltage Reset gate clock Protective transistor bias Substrate (overflow drain) Horizontal register transfer clock Horizontal register transfer clock Inter-horizontal register transfer clock Inter-horizontal register transfer clock Test pin 2 Test pin 2 Vertical register final stage transfer clock 1 DC bias is applied within the CCD, so that this pin should be grounded externally through a capacitance of 1F or more. 2 Regarding the test pins: apply the same voltage as the supply voltage to HIS, and ground HIG1, HIG2, and POG. -2- POG VOG VDD SUB H1 H2 RG HIG2 VL ICX074AL Absolute Maximum Ratings Item Substrate voltage SUB - GND Supply voltage VDD, VOUT1, VOUT2, HIS, CGG1, CGG2 - GND VDD, VOUT1, VOUT2, HIS, CGG1, CGG2 - SUB V1, V2, V3, VHOLD, VOG - GND V1, V2, V3, VHOLD, VOG - SUB Ratings -0.3 to +55 -0.3 to +18 -55 to +10 -15 to +20 to +10 to +15 to +17 -17 to +17 -10 to +15 -55 to +10 -65 to +0.3 -0.3 to +27.5 -0.3 to +22.5 -0.3 to +17.5 -30 to +80 -10 to +60 Unit V V V V V V V V V V V V V V C C 1 Remarks Clock input voltage Voltage difference between vertical clock input pins Voltage difference between horizontal clock input pins H1, H2 - VOG H1, H2 - GND H1, H2 - SUB VL - SUB V2, V3, VDD, VOUT1, VOUT2, HIS, HIG1, HIG2, POG - VL RG - GND V1, CGG1, CGG2, H1, H2, HHG1, HHG2, VOG, VHOLD - VL Storage temperature Operating temperature 1 +27V (Max.) when clock width < 10s, clock duty factor < 0.1%. -3- ICX074AL Bias Conditions Item Supply voltage Substrate voltage adjustment range Substrate voltage adjustment precision Protective transistor bias VL Symbol VDD VSUB Min. 14.55 9.0 Indicated voltage -0.1 Indicated voltage 2 Typ. 15.0 Max. 15.45 18.5 Indicated voltage +0.1 Unit Remarks V V V 1 DC Characteristics Item Supply current Input current Input current Symbol IDD IIN1 IIN2 Min. Typ. 10 1 10 Max. Unit mA A A 3 4 Remarks 1 Indications of substrate voltage (VSUB) setting value The setting value of the substrate voltage is indicated on the back of image sensor by a special code. Adjust the substrate voltage (VSUB) to the indicated voltage. VSUB code -- two characters indication Integer portion Decimal portion The integer portion of the code and the actual value correspond to each other as follows. Integer portion of code Value 9 9 A C d E f G h J K 10 11 12 13 14 15 16 17 18 4 -4- ICX074AL Clock Voltage Conditions Item Readout clock voltage VVT VVH02 VVH1, VVH2, VVH3 VVL1, VVL2, VVL3 VV Vertical transfer clock voltage I VVL1 - VVL3 I VVHH VVHL VVLH VVLL Horizontal transfer clock voltage VH VHL VRG Reset gate clock voltage VRGLH - VRGLL VRGH Substrate clock voltage VSUB Vertical final stage accumulation clock voltage transfer clock voltage VVHOLDH, VVOGH VVHOLDL, VVOGL VDD +0.4 21.5 -0.05 -8.0 4.75 -8.0 -0.05 VDD +0.6 22.5 0 -7.5 5.0 -7.5 0 4.75 -0.05 4.5 5.0 0 5.0 Symbol Min. 14.55 -0.05 -0.2 -8.0 6.8 Typ. 15.0 0 0 -7.5 7.5 Max. 15.45 0.05 0.05 -7.0 8.05 0.1 0.5 0.5 0.5 0.5 5.75 0.05 5.5 0.8 VDD +0.8 23.5 0.05 -7.0 5.25 -7.0 0.05 Unit V V V V V V V V V V V V V V V V V V V V V Waveform diagram 1 2 2 2 2 2 2 2 2 2 3 3 4 4 4 5 6 6 7 7 7 Input through 0.01F capacitance Low-level coupling High-level coupling High-level coupling Low-level coupling Low-level coupling VVL = (VVL01 + VVL03)/2 VV = VVHn - VVLn (n = 1 to 3) VVH = VVH02 Remarks VHHG1H, VHHG2H Inter-horizontal register VHHG1L, VHHG2L transfer clock voltage VHHG1M, VHHG2M -5- ICX074AL Clock Equivalent Circuit Constant Item Capacitance between vertical transfer clock and GND Symbol CV1 CV2 CV3 CV12 Capacitance between vertical transfer clocks Capacitance between vertical final stage accumulation clock and GND Capacitance between vertical final stage transfer clock and GND Capacitance between inter-horizontal register transfer clock and GND Capacitance between horizontal transfer clock and GND Capacitance between horizontal transfer clocks Capacitance between reset gate clock and GND Capacitance between substrate clock and GND Vertical transfer clock series resistor Vertical transfer clock ground resistor Horizontal transfer clock series resistor CV23 CV31 CVHOLD CVOG CHHG1 CHHG2 CH1 CH2 CHH CRG CSUB R1, R2, R3 RGND RH1 RH2 Min. Typ. 3300 4700 4700 1000 22 100 19 12 23 19 60 69 40 9 400 10 15 24 30 Max. Unit Remarks pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF V1 R1 CV12 CV1 RGND CV2 R2 V2 RH1 H1 CHH RH2 H2 Cv31 CV3 Cv23 CH1 CH2 R3 V3 Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit -6- ICX074AL Drive Clock Waveform Conditions (1) Readout clock waveform 100% 90% II II M VVT 10% 0% tr twh tf 0V M 2 (2) Vertical transfer clock waveform V1 VVHL VVH1 VVHH VVHL VVH1 VVHH VVH VVLH VVL01 VVL1 VVLL V2 VVH02 VVHH VVHL VVH2 VVL1 VVLL VVLH VVL VVHH VVHL VVH2 VVH VVLH VVL2 VVLL V3 VVHL VVH3 VVL2 VVLL VVLH VVL VVHH VVHL VVH3 VVHH VVH VVLH VVL03 VVLL VVH = VVH02 VVL = (VVL01 + VVL03) /2 VVLH VVL3 VVLL VV1 = VVH1 - VVL01 VV2 = VVH02 - VVL2 VV3 = VVH3 - VVL03 VVL -7- ICX074AL (3) Horizontal transfer clock waveform tr twh tf 90% VH 10% VHL twl (4) Reset gate clock waveform tr twh tf VRGH twl RG waveform Point A VRG VRGL + 0.5V VRGLH VRGL VRGLL H1 waveform 2.5V VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL. VRGL = (VRGLH + VRGLL)/2 Assuming VRGH is the minimum value during the interval twh, then: VRG = VRGH - VRGL (5) Substrate clock waveform 100% 90% M VSUB 10% 0% M 2 tf VSUB tr twh -8- ICX074AL (6) Vertical final stage accumulation clock waveform * Vertical final stage transfer clock waveform VHOLD, VOG tr tf VVHOLDH, VVOGH 90% 10% VVHOLDL, VVOGL (7) Inter-horizontal register transfer clock waveform HHG1, HHG2 tr tf1 VHHG1H, VHHG2H 90% 90% tf2 10% VHHG1M, VHHG2M 90% 10% 10% VHHG1L, VHHG2L -9- ICX074AL Clock Switching Characteristics Item Readout clock Vertical transfer clock Horizontal transfer clock Symbol VT V1, V2, V3 H1 H2 twh twl tr tf, tf1, tf2 Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. 2.3 2.5 0.5 15 24 26 29 31 26 24 31 29 10 17.5 10 0.01 0.01 11 13 64 2 0.5 20 20 20 20 20 20 20 20 15 0.5 350 10 17.5 10 0.01 0.01 2 0.5 15 Unit s ns Remarks During readout 1 2 During imaging ns s ns s ns ns ns ns During parallel- H1 serial conversion H2 RG SUB Reset gate clock Substrate clock 1.6 1.9 During drain charge Vertical final stage VHOLD accumulation/ VOG transfer clock Inter-horizontal register transfer clock HHG1 HHG2 1 When vertical transfer clock driver CXD1268M is used. 2 tf tr - 2ns, and the cross-point voltage (VCR) for the H1 rising side of the H1 and H2 waveforms must be at least 2.5V. two Item Horizontal transfer clock Symbol H1, H2 Min. Typ. Max. 24 29 Unit ns Remarks 3 3 The overlap period for twh and twl of horizontal transfer clocks H1 and H2 is two. - 10 - ICX074AL Image Sensor Characteristics Item Sensitivity Saturation signal Smear Video signal shading Dark signal Dark signal shading Lag Uniformity between output channels Symbol S Vsat Sm SH Vdt Vdt Lag V 500 0.002 0.007 25 2 1 0.5 3 Min. Typ. 350 Max. Unit mV mV % % mV mV % % Measurement method 1 2 3 4 5 6 7 8 (Ta = 25C) Remarks Ta = 60C Zone 0 Ta = 60C Ta = 60C Note) All the characteristic data of this image sensor was yielded when the sensor was operated in the 1/60s interlaced mode. Zone Definition of Video Signal Shading 659 (H) 4 5 4 494 (V) Zone 0 2 Ignored region Effective pixel region Measurement System CCD signal output 1 [A] [C] C.D.S AMP S/H signal output 1 CCD [B] CCD signal output 2 C.D.S AMP S/H [D] signal output 2 Note) Adjust the amplifier gain so that the gain between [A] and [C], and between [B] and [D] equals 1. - 11 - ICX074AL Readout modes The output methods for the two readout modes indicated below are now described. 1/60s interlaced 1/30s non-interlaced Odd field VOUT1 VOUT2 VOUT1 VOUT2 Even field VOUT1 VOUT2 1. 1/60s interlaced In this mode, the signals are output in a 1/60s period using the two output pins (VOUT1, VOUT2). The signals from two adjacent horizontal lines are simultaneously output from the respective output pins. The lines output from the output pins are changed over with each field. The VOUT1 signal after it has passed through the CDS and other external circuits or the signal produced by adding the VOUT1 and VOUT2 signals accommodate interlaced scanning. 2. 1/30s non-interlaced In this mode, the signals are output in a 1/30s period using only one output pin (VOUT1). Unlike the 1/60s interlaced mode described above, the external circuit can be simplified. The imaging characteristics also differ from those of the other modes. - 12 - ICX074AL Image Sensor Characteristics Measurement Method Measurement conditions 1) In the following measurements, the substrate voltage is set to the value indicated on the device, and the device drive conditions are at the typical values of the bias and clock voltage conditions. 2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black (OB) level is used as the reference for the signal output and the value measured at point [A] in the measurement system is used. 3) In the following measurements, this image sensor is operated in 1/60s interlaced mode. Definition of standard imaging conditions 1) Standard imaging condition I: Use a pattern box (luminance 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.00mm) as an IR cut filter and image at F8. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. 2) Standard imaging condition II : Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens with CM500S (t = 1.00mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. 1. Sensitivity Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of 1/250s, measure the signal output (Vs) at the center of the screen and substitute the value into the following formula. S = Vs x 250 60 [mV] 2. Saturation signal Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with average value of signal output, 150mV, measure the minimum value of the signal output. 3. Smear Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to 500 times the intensity with average value of signal output, 150mV. When the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value VSm [mV] of the signal output and substitute the value into the following formula. Sm = 1 VSm 1 x x x 100 [%] (1/10V method conversion value) 10 150 500 4. Video signal shading Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so that the average value of the signal output is 150mV. Then measure the maximum (Vmax [mV]) and minimum (Vmin [mV]) values of the signal output and substitute the values into the following formula. SH = (Vmax - Vmin)/150 x 100 [%] - 13 - ICX074AL 5. Dark signal Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. 6. Dark signal shading After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark signal output and substitute the values into the following formula. Vdt = Vdmax - Vdmin [mV] 7. Lag Adjust the signal output value generated by strobe light to 150mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following formula. Lag = (Vlag/150) x 100 [%] FLD SG Light Strobe light timing Signal output 150mV Output Vlag (lag) 8. Uniformity between output channels Set to standard imaging condition I. Measure the signals at signal output 1 (V1) and at signal output 2 (V2), and substitute the values into the following formula. V = I V2 - V1I V1 x 100 [%] - 14 - Drive Circuit 2SC2785 x 3 15V 56k 0.1 270k 47k 20 1/35V 1/35V 0.1 0.1 39 15k 27k 15k -7.5V 22/16V 5V 13 12 11 22/20V 1/10V 3.9k 1/10V 2SK523 100 CXD1268M 22 /16V 19 18 17 N.C. 16 15 14 XV2 XSG 1 2 N.C. 3 4 5 6 7 N.C. 8 9 10 [A] CCD OUT1 XV1 XV3 10/20V 1 2 3 4 5 6 7 8 9 10 11 100 HIG1 HIS V3 GND CGG1 VOUT1 CGG2 VOUT2 100k V2 V1 VHOLD 1 2 1/35V 22/16V 18 17 16 15 20 19 2SK523 [B] CCD OUT2 3.9k 3 4 5 VOG POG HIG2 XSUB XVHOLD XHHG1-1 XHHG1-2 XHHG2-1 XHHG2-2 XVOG ICX074 (BOTTOM VIEW) H2 H1 HHG2 HHG1 SUB VL RG VDD 14 13 12 11 22/10V 3.3/16V 100 22 21 20 19 18 17 16 1514 13 12 - 15 - 1/20V HC04 HC04 0.01 6 7 CXD1250 8 9 22/10V 10 1M 3.3/20V 0.01 XH2 XH1 ICX074AL RG ICX074AL Spectral Sensitivity Characteristics (includes lens characteristics, excludes light source characteristics) 1.0 0.9 0.8 0.7 Relative Response 0.6 0.5 0.4 0.3 0.2 0.1 0.0 400 500 600 700 Wave Length [nm] 800 900 1000 Sensor Readout Clock Timing Chart 1/60s interlaced mode HD V1 Odd Field V2 V3 42.5 V1 Even Field 2.53 2.53 2.94 V2 V3 Unit : s - 16 - Drive Timing Chart (Vertical Sync) 493 494 2 4 6 8 2 4 6 8 1 3 5 7 1 3 5 7 493 494 1 3 5 7 1 3 5 7 2 4 6 8 2 4 6 8 - 17 - FLD BLK HD VD V3 V2 V1 CCD OUT1 CCD OUT2 SG 525 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1/60s interlaced mode 260 261 262 263 264 265 270 275 280 285 ICX074AL Drive Timing Chart (Horizontal Sync) 1/60s interlaced mode HD BLK CLK V1 V2 V3 VOG - 18 - VHOLD HHG1 HHG2 H1 H2 RG SHP SHD SUB ICX074AL ICX074AL Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Soldering a) Make sure the package temperature does not exceed 80C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, use a thermal controller of the zero cross On/Off type and connect it to ground. 3) Dust and dirt protection Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operation as required, and use them. a) Perform all assembly operations in a clean room (class 1000 or less). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) When a protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. Do not reuse the tape. 4) Installing (attaching) a) Remain within the following limits when applying a static load to the package. Do not apply any load more than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited portions. (This may cause cracks in the package.) Upper ceramic 39N 29N 29N 0.9Nm Lower ceramic Low melting point glass Shearing strength Tensile strength Torsional strength Compressive strength b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portions. Therefore, for installation, use either an elastic load, such as a spring plate, or an adhesive. - 19 - ICX074AL c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area, and indicated values should be transferred to other locations as a precaution. d) The upper and lower ceramic are joined by low melting point glass. Therefore, care should be taken not to perform the following actions as this may cause cracks. * Applying repeated bending stress to the outer leads. * Heating the outer leads for an extended period with a soldering iron. * Rapidly cooling or heating the package. * Applying any load or impact to a limited portion of the low melting point glass using tweezers or other sharp tools. * Prying at the upper or lower ceramic using the low melting point glass as a fulcrum. Note that the same cautions also apply when removing soldered products from boards. e) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyanoacrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference) 5) Others a) Do not expose to strong light (sun rays) for long periods. For continuous using under cruel condition exceeding the normal using condition, consult our company. b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. - 20 - Package Outline Unit: mm 22pin DIP (600mil) 0 to 9 9.0 12 22 12 A 0.7 22 3 C 15.24 B V H 2-R0.7 11.55 3 7.55 0.55 B' 14.6 3 1.27 4.0 0.3 - 21 - 0.7 0.3 0.46 0.3 M 3.4 0.3 1. "A" is the center of the effective image area. 2. The two points "B" of the package are the horizontal reference. The point "B'" of the package is the vertical reference. 3. The bottom "C" of the package is the height reference. 4. The center of the effective image area, relative to "B" and "B'" is (H, V) = (9.0, 7.55) 0.15mm. 5. The rotation angle of the effective image area relative to H and V is 1. 6. The height from the bottom "C" to the effective image area is 1.41 0.15mm. 7. The tilt of the effective image area relative to the bottom "C" is less than 60m. 8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5. 9. The notches on the bottom must not be used for reference of fixing. 0.69 (For the 1st. pin only) 1.27 PACKAGE STRUCTURE PACKAGE MATERIAL Cer-DIP LEAD TREATMENT TIN PLATING LEAD MATERIAL 42 ALLOY ICX074AL PACKAGE WEIGHT 2.6g 0.25 1 18.0 0.4 17.6 11 11 15.1 0.3 1 |
Price & Availability of ICX074AL
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |