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CXB1572Q
Post amplifier for Optical Fiber Communication Receiver
Description The CXB1572Q achieves the 2R optical-fiber communication receiver functions (Reshaping and Regenerating) on a single chip. This IC is also equipped with the signal interruption alarm output function, which is used to discriminate the existence of data input. 32 pin QFP (Plastic)
Features * Auto-offset canceler circuit * Signal interruption alarm output * 2-level switching function of identification maximum voltage amplitude for alarm block * Single 3.3 V power supply Applications * FDDI * SONET/SDH * ESCON * Fiber channel * ATM
: 125 Mb/s : 155.52 Mb/s : 200 Mb/s : 265.625 Mb/s : 155.52 Mb/s
Absolute Maximum Ratings * Supply voltage * * * * Storage temperature Input voltage difference : I VD - VD I SW input voltage Output current (Continuous) (Surge current)
VCC - VEE Tstg Vdif Vi IO
-0.3 to +7.0 -65 to +150 0 to +2.5 VEE to VCC 0 to 50 0 to 100
V C V V mA mA
Recommended Operating Conditions * Supply voltage VCC - VEE * Termination voltage (for data/alarm) VCC - VT1 * Termination voltage (for alarm 2) VT2 * Termination resistance (for data/alarm) RT1 * Termination resistance (for alarm 2) RT2 * Operating temperature Ta Structure Bipolar silicon monolithic IC
3.0 to 3.6 1.8 to 2.2 VEE 46 to 56 460 to 560 -40 to +85
V V V C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
--1--
E96638-TE
CXB1572Q
Block Diagram and Pin Configuration
VCCDA
VCCD
VCCDA
SD
SD
24
23
22
21
Q
Q
18
20
19
NC NC
25 16 26
NC
17
NC
15
VCCD
NC
27 14
CAP3
28
Alarm Block
VEED
Limiting Amplifier Block
peak hold peak hold
13
VCCA
CAP2
29
12
VEEA
V
DOWN UP VCCA
30
R2
R2
11
CAP1 R3K R2K
31
R4 R1
10 9
32
Rp
R1 R3
2 3 4 5 6 7 8
1
VCCP
D
VEEI
SW
D
VCCA
--2--
CAP1
VCCA
CXB1572Q
Pin Description Pin No. Symbol Typical pin voltage (V) DC AC Equivalent circuit Description
1
VCCP
32 5 1 2
Positive power supply for external power supply.
2
VCCA
0V
VccA 986 123.4 123.4 31
3
VEEI
-3.3 V
30 Vcs SW
VEEA 3
Generates the default voltage between UP and DOWN. The voltage (5.3 mV for input conversion) can be generated between UP and DOWN (Pins 30 and 31) as alarm setting level 1 by this pin to Open. The voltage (12 mV for input conversion) can be generated as alarm setting level 2 by connecting this pin to VEEA.
VCCA 60k
4
SW
0V (OPEN) or -3.3 V
40k 4 VREF
Switches the identification maximum voltage amplitude. High voltage when open; the identification maximum voltage amplitude becomes 50 mVp-p. Low voltage when connecting this pin to VEE; the amplitude becomes 20 mVp-p.
VEEA
5
D
6
D
-0.9 V to -1.7 V -0.9 V -1.3 V to -1.7 V -1.3 V 0V
100 5 10k 100p 200 100 1.5k 10k 200 2k VCCA
Limiting amplifier block input. Be sure to make this input with AC coupled. Positive power supply for analog block.
Pins 8 and 11 connect a capacitor which determines the cut-off frequency for feedback block, and 2 k is connected between Pins 8 and 9; 3 k between Pins 10 and 11. A resistor which is to be inserted in parallel with a capacitor can be selected 5 ways by external wiring, and DC feedback gain can be varied due to compensate the input duty cycle distortion.
7
VCCA
11 3k 10 9 8
8
CAP1
-1.8 V
6
9
R2K
1.5k VEEA
10
R3K
11
CAP1
-1.8 V --3--
CXB1572Q
Pin No. Symbol
Typical pin voltage (V) DC AC -3.3 V 0V -3.3 V 0V
Equivalent circuit
Description Negative power supply for analog block. Positive power supply for analog block. Negative power supply for digital block. Positive power supply for digital block. No connected.
12 13 14 15 16
VEEA VCCA VEED VCCD
NC 17
VCCDA
18
Q
-0.9 V to -1.7 V
19
Data signal output. Terminate this pin in 50 at VTT = -2 V.
19
Q
-0.9 V to -1.7 V
18 VEED
20
VCCDA
0V
VCCDA
Positive power supply for output buffer. -0.9 V to -1.7 V
21
SD
21
Alarm signal output. Terminate this pin in 50 at VTT = -2 V.
22
SD
-0.9 V to -1.7 V
22 VEED
23 24 25 26 27
VCCDA VCCD NC
0V 0V
Positive power supply for digital block. Positive power supply for digital block. No connected.
--4--
CXB1572Q
Pin No. Symbol
Typical pin voltage (V) DC AC
Equivalent circuit
Description
29
28 VCCA
28
CAP3 -1.8 V
80 80
200
200
29
CAP2 -1.8 V
5A
5A VEEA
Connects a peak hold circuit capacitor for alarm block. 470 pF should be connected to VCCA each. CAP2 pin Peak hold capacitor connection for alarm level setting block. CAP3 pin Peak hold capacitor connection for limiting amplifier signal.
10p
10p
VccA
30
-1090 mV (for DOWN VEEI = -3.3 V)
986 123.4 123.4 31 30 Vcs
31
UP
-1020 mV (for VEEI = -3.3 V) 0V
SW
Connects a resistor for alarm level setting. Default voltage can be generated without an external resistor. (Please refer to pin description of pin No. 3.)
VEEA 3
32
VCCA
Positive power supply for analog block.
--5--
CXB1572Q
Electrical Characteristics * DC characteristics (VCC = GND, VEE = -3.0 V to -3.6 V, Ta = -40 to +85 C, VCC = VCCD, VCCDA, VCCA VEE = VEED, VEEA) Item Power supply Q/Q SD/SD High output voltage Q/Q SD/SD Low output voltage SD/SD High output voltage 2 SD/SD Low output voltage 2 SW High input voltage SW Low input voltage SW High input current SW Low input current D/D input resistance Internal resistance 1 for alarm level setting Internal resistance 2 for alarm level setting Resistance between VCCA and VCCP Pare ratio of internal resistance 2 for alarm level setting Resistance between CAP1 and R2K Resistance between CAP1 and R3K Symbol IEE VOH VOL VOHb VOLb VIH VIL IIH IIL Rin Ra1 Refer to Fig. 3. -60 1109 739 93 3.3 Ra2A/Ra2B 0.97 1470 2210 1970 2960 1479 986 123 5 1849 1233 154 6.9 1.03 2470 3700
RT1 = 51 , VT1 = VCC-2 V termination, Ta=0 to 85 C
Conditions
Min. -56 -1025 -1810 -1025 -1860 -500 VEE
Typ. -40
Max. -29 -830 -1550 -700 -1500 0 VEE+500 2
Unit mA
RT2 = 510 , VT2 =VEE termination, Ta=0 to 85 C
mV
A
Ra2A, B Refer to Fig. 3. RP Ra2 R3 R4
--6--
CXB1572Q
* AC characteristics (VCC = GND, VEE = -3.0 V to -3.6 V, Ta = -40 to +85 C, VCC = VCCD, VCCDA, VCCA VEE = VEED, VEEA) Item Maximum input voltage amplitude Amplifier gain (except for output buffer) Identification maximum voltage amplitude of alarm level Symbol Vmax GL VminA1 VminA2 P Tas Tdas Tasd Tdasd Vdef1 SW pin: Low, single-ended input SW pin: Open High, single-ended input Alarm level is default value Low High1 High Low2 Low High3 High Low4 UP,DOWN,VEEI pins ;Open,connect SW pin to VEE UP,DOWN,SW pins ;Open,connect VEEI to VEE D to Q RT1 = 50 , VT1 = VCC-2 V termination, VEE=-3.3 V, Ta=0 to 85 C 20 % to 80 % Conditions Single-ended input Min. 1600 52 20 mVpp 50 3 0 2.3 0 2.3 4.3 5.3 6 7 100 100 100 100 6.3 mV 10.5 1.2 0.45 12.0 1.7 0.85 13.5 2.6 1.3 ns 0.45 0.85 1.3 s dB Typ. Max. Unit mVpp dB
Hysteresis width SD response assert time SD response deassert time SD response assert time for alarm level default SD response deassert time for alarm level default Alarm setting level 1 for default
Alarm setting level 2 for default Propagation delay time Q/Q SD/SD rise time
Vdef2 TPD Tr
Q/Q SD/SD fall time
Tf
1 2 3 4
VUP - VDOWN = 100 mV, Vin = 100 mVpp (single ended), SW pin: High Peak hold capacitance of 470 pF; connect VEEI to VEE. VUP - VDOWN = 100 mV, Vin = 1 Vpp (single ended), SW pin: High Peak hold capacitance of 470 pF; connect VEEI to VEE. Vin = 50 mVpp (single ended), SW pin: Low Peak hold capacitance of 470 pF; connect VEEI to VEE. Vin = 1 Vpp (single ended), SW pin: Low Peak hold capacitance of 470 pF; connect VEEI to VEE.
--7--
CXB1572Q
DC Electrical Characteristics Measurement Circuit
VT1
-2V
V
51 51
V
V
51 51
V
24 25
23
22
21
20
19
18
17
16 26 15 27 Alarm Block 28 Limiting Amplifier Block
C3
14
peak hold
29
peak hold
C3
13
12
R2
V
30
R2
11
V
31 32
R1
R4 10 9
V
C2
V
R1
R3
V
V
RP 1 2 3 4 5 6 7 8
V
V A
C1 VS C1
V
VD VEE
A
-5V
--8--
CXB1572Q
AC Electrical Characteristics Measurement Circuit
Oscilloscope 50input
Z0=50 Z0=50
Z0=50
Z0=50
24 25
23
22
21
20
19
18
17
16 26 15 27 Alarm Block 28 Limiting Amplifier Block
470pF
14
peak hold
29
peak hold
470pF
13
12
R2
REX1
V
31 32
V
30
R2
11 R1 R4 10 9 R1 RP 1 2 3 4 5 6 7 8 R3 0.22F
REX2
0.022F
0.022F VEE +3V VCC +2V
--9--
CXB1572Q
Application Circuit
VT1
-2V
51
51
51
51
24 25
23
22
21
20
19
18
17
16 26 15 27 Alarm Block 28 C3 330pF Limiting Amplifier Block
14
13
peak hold
29
peak hold
12
V
30
R2
R2
11 31 32 R1 RP 1 2 3 4 5 6 7 8 R3 R1 R4 10 9 C2 0.22F
C1 0.022F
C1 0.022F
VEE
-5V
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
--10--
CXB1572Q
Notes on Operation 1. Limiting amplifier block The limiting amplifier block is equipped with the auto-offset canceler circuit. When external capacitors C1 and C2 are connected as shown in Fig. 1, the DC bias is set automatically in this block. External capacitor C1 and IC internal resistor R1 determine the low input cut-off frequency f2 as shown in Fig. 2. Similarly, external capacitor C2 and IC internal resistor R2 determine the high cut-off frequency f1 for DC bias feedback. Since peaking characteristics may occur in the low frequency area of the amplifier gain characteristics depending on the f1/f2 combination, set the C1 and C2 so as to avoid the occurrence of peaking characteristics. The target values of R1 and R2 and the typical values of C1 and C2 are as indicated below. When a single-ended input is used, provide AC grounding by connecting Pin 6 to a capacitor which has the same capacitance as capacitor C1. R1 (internal): 1.5 k R2 (internal): 10 k f2: 4.8 kHz f1: 72 Hz C1 (external): 0.022 F C2 (external): 0.22 F 2 k is incorporated between Pins 8 and 9; 3 k between Pins 10 and 11. A resistance value which is to be inserted in parallel with a capacitor C2 can be selected 5 ways (, 5 k, 3 k, 2 k, 2 k//3 k) by external wiring, and DC feedback can be varied.
D C1
5 To IC interior 6 C1 R1 8 R3 9 C2 10 R4 11 R2 R2 R1
Fig. 1
Feedback frequency response
Amplifier frequency response
Gain
f1
f2 Frequency
Fig. 2 --11--
CXB1572Q
2. Alarm block In order to operate the alarm block, give the voltage difference between Pins 30 and 31 to set an alarm level and connect the peak hold capacitor C3 shown in Fig. 3. This IC has two setting methods of alarm level; one is to leave Pins 30 and 31 open to set an alarm level default value (5.3 mV or 12 mV for input conversion). Default value of alarm level is 5.3 mV for input conversion by leaving Pin3 to open,12 mV by connecting Pin3 to VEE. The other is to connect Pin 3 to VEE and set a desired alarm level using the external resistors REX1 and REX2 and REX3 shown in Fig. 3. Connect REX1 between Pins 30 and 31, or connect REX3 between Pin 30 and VCC when less alarm level is desired to be set than its default value; connect REX2 between Pin 31 and VCC potential when more alarm level is desired to be set than its default value. However, the Pin 31 voltage must be higher than that of Pin 30. Refer to Figs. 7 to 9 for this alarm level setting. This IC also features two-level setting of identification maximum voltage amplitude for the alarm function. The amplitude is set to 50 mVp-p when Pin 4 is left open (High level) and it is set to 20 mVp-p when Pin 4 is Low level. Therefore, noise margin can be increased by setting Pin 4 to Low level when small signal is input. The relation of input voltage and peak hold output voltage is shown in Fig. 5. In the relation between the alarm setting level and hysteresis width, the hysteresis width is designed to maintain a constant gain (design target value: 6 dB) as shown in Fig. 4. The C3 capacitance value should be set so as to obtain desired assert time and deassert time settings for the alarm signal. The electrical characteristics for the SD response assert and deassert times are guaranteed only when the waveforms are input as shown in the timing chart of Fig. 6. The typical values of REX1, REX2, REX3 and C3 are as follows: (Approximately 10 pF capacitor is built in Pins 28 and 29 each.) REX1 : 400 (when the alarm level is set to 3 mV for input conversion.Pin3; open,connect Pin4 to VEE) REX2 : 4k (when the alarm level is set to 15 mV for input conversion.connect Pin3 to VEE, Pin4; open) REX3 : 6.2 k (when the alarm level is set to 3 mV for input conversion.Pin3; open,connect Pin4 to VEE) C3 : 470 pF The table below shows the alarm logic. Optical signal input state Signal input Signal interruption SD High level Low level
Ra1, Ra2A and Ra2B values are typical values VCCA Ra1 Ra2A 123.4 986 Ra2B 123.4 Vcs V 4 VEEA Internal IC 31 External IC 30 3 REX2 Vcc REX1 REX3 Vcc Vcc Vcc C3 C3 3 31 30 Peak hold SD SD
SD Low level High level
From Limiting Amplifier
Peak hold
VccA 10p 29 28
VccA 10p
Fig. 3 --12--
CXB1572Q
VDAS Deassert level VAS Assert level High level
Peak hold output voltage
SD output
SWLow
Low level VDAS Small 3dB 3dB Alarm setting input level Hysteresis Input electrical signal amplitude VAS Large
SWOpen High
0
20mVpp
50mVpp
Input voltage (Vp-p)
Fig. 4
Fig. 5
Data input (D)
Hysteresis width
Alarm setting level
Data output (Q)
Alarm output (SD)
Assert time
Deassert time
Fig. 6
5.0 4.5
Alarm setting level (mV)
4.0 3.5 3.0 2.5 2.0 1.5 1.0 102 103 REX1 ()
VEEI=open SW=VEE Ta=27C
104
Fig. 7 --13--
CXB1572Q
35
5.0 4.5
Alarm setting level (mV)
Alarm setting level (mV)
30 25 20 15 10 101
VEEI=VEE SW=open Ta=27C
4.0 3.5 3.0 2.5 2.0 1.5 1.0 103 104 REX3 () 105
VEEI=open SW=VEE Ta=27C
102
103 REX2 ()
104
105
Fig. 8 3. Others
Fig. 9
Pay attention to handling this IC because its electrostatic discharge strength is weak.
--14--
CXB1572Q
Example of Representative Characteristics
Bit error rate vs. Input amplitude level
10-3 10-4
Bit error rate
10-5 10-6 10-7 10-8 10-9 0.2 0.4 0.6 0.8 1 Data input level (mVp-p) 1.2
VEE=-3.3V Ta=27C D=155.52Mb/s Vin=3mVp-p, Single Input pattern : PRBS223-1
Fig. 10
Output RMS Jitter vs. Data input level 70 60 50 40 30 20 10 0 1 10 100 1000
VEE=3.3V Ta=27C D=155.52Mbps Vin=3mVp-p, Single Input pattern : PRBS223-1
Output RMS Jitter (ps)
Data input level (mVp-p)
Fig. 11
Q Output waveform
VEE=3.3V Ta=27C D=155.52Mbps Vin=3mVp-p, Single Input pattern : PRBS223-1
16.4400ns
26.4400ns
36.4400ns Offset Delay = 680.0 mVolts = 26.4400 ns --15--
Ch. 1 = 200.0 mVolts/div Timebase = 2.00 ns/div
CXB1572Q
Package Outline
Unit : mm
32PIN QFP (PLASTIC)
9.0 0.2 + 0.3 7.0 - 0.1 24 17 + 0.35 1.5 - 0.15
0.1
25
16
32
9
+ 0.2 0.1 - 0.1
1 0.8 + 0.15 0.3 - 0.1
8 + 0.1 0.127 - 0.05 0 to 10
0.24
M
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-32P-L01 QFP032-P-0707 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS
EPOXY RESIN SOLDER PLATING 42 ALLOY 0.2g
--16--
0.50
(8.0)

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