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PRELIMINARY PRODUCT SPECIFICATION
1
Z8E001
CMOS OTP MICROCONTROLLER
FEATURES
Part Number Z8E001
* General-Purpose s s s
1
ROM (KB) 1
RAM* (Bytes) 64
Speed (MHz) 10
One Analog Comparator 16-Bit Programmable Watch-Dog Timer (WDT) Software Programmable Timers Configurable as: - Two 8-Bit Standard Timers and One 16-Bit Standard Timer or - One 16-Bit Standard Timer and One 16-Bit Pulse Width Modulator (PWM) Timer
Microcontroller Core Features
s
All Instructions Execute in one 1 s Instruction Cycle with 10 MHz Crystal 1K x 8 On-Chip OTP EPROM Memory 64 x 8 General-Purpose Registers (SRAM) Six Vectored Interrupts with Fixed Priority Operating Speed: DC - 10 MHz Six Addressing Modes: R, IR, X, D, RA, & IM
s s s
s s s s s
Additional Features
On-Chip Oscillator that Accepts XTAL, Ceramic Resonator, LC, or External Clock Programmable Options: - EPROM Protect Power Reduction Modes: - HALT Mode with Peripheral Units Active - STOP Mode with all Functionality Shut Down
Peripheral Features
s s
13 Total Input/Output Pins One 8-Bit I/O Port (Port A) - I/O Bit Programmable - Each Bit Programmable as Push-Pull or OpenDrain One 5-Bit I/O Port (Port B) - I/O Bit Programmable - Includes Special Functionality: Stop-Mode Recovery Input Comparator Inputs Selectable Edge Interrupts Timer Output
CMOS/Technology Features
s s
Low-Power Consumption 3.0V to 5.5V Operating Range @ 0C to +70C 4.5V to 5.5V Operating Range @ -40C to +105C 18-Pin DIP,SOIC, and 20-Pin SSOP Packages.
s
s
DS97Z8X1300
PRELIMINARY
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Z8E001 CMOS OTP Microcontroller
Zilog
GENERAL DESCRIPTION
Zilog's Z8E001 Microcontroller (MCU) is a One-Time Programmable (OTP) member of Zilog's single-chip Z8Plus MCU family that allows easy software development, debug, prototyping, and small production runs not economically desirable with masked ROM versions. For applications demanding powerful I/O capabilities, the Z8E001's dedicated input and output lines are grouped into two ports, and are configurable under software control. Both 8-bit and 16-bit on-chip timers, with a large number of user selectable modes, offload the system of administering real-time tasks such as counting/timing and I/O data communications. Note: All signals with a preceding front slash, "/", are active Low. For example, B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit
VCC
Device
VDD VSS
GND
VCC
GND
XTAL
/RESET
Two 8-bit Timers or One 16-bit PWM Timer ALU One 16-bit Std. Timer FLAG
Machine Timing & Inst. Control
OTP Prg. Memory Interrupt Control Register Pointer One Analog Comparator RAM Register File Program Counter
Port A
Port B
I/O
I/O Figure 1. Functional Block Diagram
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Z8E001 CMOS OTP Microcontroller
D7 - 0
Z8E001 MCU
AD9 - 0 AD9 - 0 ADDRESS MUX
ADDRESS GENERATOR
AD9 -0
EPROM
D7-0
DATA MUX Z8E001 D7-0 PORT
ROM PROT OPTION BIT PGM + TEST MODE LOGIC
A
/PGM ADCLK XTAL1
ADCLR/VPP
Figure 2. EPROM Programming Mode Block Diagram
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Z8E001 CMOS OTP Microcontroller
Zilog
PIN DESCRIPTION
/PGM GND GND GND ADCLR/VPP D7 D6 D5 D4
1
18
DIP 18 - Pin
9
10
ADCLK XTAL1 NC GND VDD D0 D1 D2 D3
Figure 3. 18-Pin DIP/SOIC Pin Identification/EPROM Programming Mode
Table 1. 18-Pin DIP/SOIC Pin Assignments/EPROM Programming Mode EPROM Programming Mode Pin # 1 2-4 5 6-9 10-13 14 15 16 17 18 Symbol /PGM GND ADCLR/VPP D7-D4 D3-D0 VDD GND NC XTAL1 ADCLK Function Prog Mode Ground Clear Clk./Prog Volt. Data 7,6,5,4 Data 3,2,1,0 Power Supply Ground No Connection 1MHz Clock Address Clock Direction Input Input In/Output In/Output
Input Input
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Z8E001 CMOS OTP Microcontroller
PB1 PB2 PB3 PB4 /RST PA7 PA6 PA5 PA4
1
18
DIP 18 - Pin
9
10
PBO XTAL1 XTAL2 VSS VCC PA0 PA1 PA2 PA3
Figure 4. 18-Pin DIP/SOIC Pin Identification
Table 2. 18-Pin DIP/SOIC Pin Assignments Standard Mode Pin # 1-4 5 6-9 10-13 14 15 16 17 18 Symbol PB1-PB4 /RESET PA7-PA4 PA3-PA0 VCC VSS XTAL2 XTAL1 PB0 Function Port B, Pins 1,2,3,4 Reset Port A, Pins 7,6,5,4 Port A, Pins 3,2,1,0 Power Supply Ground Crystal Osc. Clock Crystal Osc. Clock Port B, Pin 0 Output Input In/Output Direction In/Output Input In/Output In/Output
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PIN DESCRIPTION (Continued)
PB1 PB2 PB3 PB4 /RESET NC PA7 PA6 PA5 PA4
1
20
SSOP 20 - Pin
10
11
PBO XTAL1 XTAL2 VSS VCC NC PA0 PA1 PA2 PA3
Figure 5. 20-Pin SSOP Pin Identification
Table 3. 20-Pin SSOP Pin Assignments Standard Mode Pin # 1-4 5 6 7-10 11-14 15 16 17 18 19 20 Symbol PB1-PB4 /RESET NC PA7-PA4 PA3-PA0 NC VCC VSS XTAL2 XTAL1 PB0 Function Port B, Pins 1,2,3,4 Reset No Connection Port A, Pins 7,6,5,4 Port A, Pins 3,2,1,0 No Connection Power Supply Ground Crystal Osc. Clock Crystal Osc. Clock Port B, Pin 0 Output Input In/Output Direction In/Output Input In/Output In/Output
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Z8E001 CMOS OTP Microcontroller
/PGM GND GND GND ADCLR/VPP NC D7 D6 D5 D4
1
20
SSOP 20 - Pin
10
11
ADCLK XTAL1 NC GND NC VDD NC D1 D2 D3
Figure 6. 20-Pin SSOP Pin Identification/EPROM Programming Mode
Table 4. 20-Pin SSOP Pin Assignments/EPROM Programming Mode EPROM Programming Mode Pin # 1 2-4 5 6 7-10 11-14 15 16 17 18 19 20 Symbol /PGM GND ADCLR/VPP NC D7-D4 D3-D0 NC VDD GND NC XTAL1 ADCLK Function Prog Mode Ground Clear Clk./Prog Volt. No Connection Data 7,6,5,4 Data 3,2,1,0 No Connection Power Supply Ground No Connection 1MHz Clock Address Clock Direction Input Input In/Output In/Output
Input Input
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Z8E001 CMOS OTP Microcontroller
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ABSOLUTE MAXIMUM RATINGS
Parameter Ambient Temperature under Bias Storage Temperature Voltage on any Pin with Respect to VSS Voltage on VDD Pin with Respect to VSS Voltage on /RESET Pin with Respect to VSS Total Power Dissipation Maximum Allowable Current out of VSS Maximum Allowable Current into VDD Maximum Allowable Current into an Input Pin Maximum Allowable Current into an Open-Drain Pin Maximum Allowable Output Current Sunk by Any I/O Pin Maximum Allowable Output Current Sourced by Any I/O Pin Maximum Allowable Output Current Sunk by Port A Maximum Allowable Output Current Sourced by Port A Maximum Allowable Output Current Sunk by Port B Maximum Allowable Output Current Sourced by Port B -600 -600 Min -40 -65 -0.6 -0.3 -0.6 Max +105 +150 +7 +7 VDD+1 880 80 80 +600 +600 25 25 40 40 40 40 Units C C V V V mW mA mA A A mA mA mA mA mA mA 3 4 2 Note
1
Notes: 1. This applies to all pins except the /RESET pin and where otherwise noted. 2. There is no input protection diode from pin to VDD. 3. This excludes XTAL pins. 4. Device pin is not at an output Low state.
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. Total power dissipation should not exceed 880 mW for the package. Power dissipation is calculated as follows:
Total Power Dissipation = VDD x [IDD - (sum of IOH)] + sum of [(VDD - VOH) x IOH] + sum of (V0L x I0L)
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Z8E001 CMOS OTP Microcontroller
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to Ground. Positive current flows into the referenced pin (Figure 7).
From Output Under Test
150 pF
Figure 7. Test Load Diagram
CAPACITANCE TA = 25C, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.
Parameter Input capacitance Output capacitance I/O capacitance Min 0 0 0 Max 12 pF 12 pF 12 pF
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Z8E001 CMOS OTP Microcontroller
Zilog
DC ELECTRICAL CHARACTERISTICS
TA = 0C to +70 C Typical [1] Sym VCH Parameter Clock Input High Voltage VCC [3] 3.0V 5.5V VCL Clock Input Low Voltage 3.0V 5.5V VIH VIL VOH VOL1 VOL2 VRH VRL Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Low Voltage Reset Input High Voltage Reset Input Low Voltage 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V VOFFSET Comparator Input Offset Voltage IIL IOL VICR Input Leakage Output Leakage Comparator Input Common Mode Voltage Range Reset Input Current 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 0.5VCC 0.5VCC VSS-0.3 VSS-0.3 Min 0.7VCC 0.7VCC VSS-0.3 VSS-0.3 0.7VCC 0.7VCC VSS-0.3 VSS-0.3 VCC-0.4 VCC-0.4 0.6 0.4 1.2 1.2 VCC VCC 0.2VCC 0.2VCC 25.0 25.0 2.0 2.0 2.0 2.0 Max VCC+0.3 VCC+0.3 0.2VCC 0.2VCC VCC+0.3 VCC+0.3 0.2VCC 0.2VCC @ 25C 1.3 2.5 0.7 1.5 1.3 2.5 0.7 1.5 3.1 4.8 0.2 0.1 0.5 0.5 1.1 2.2 0.9 1.4 10.0 10.0 0.064 0.064 0.114 0.114 Units Conditions V V V V V V V V V V V V V V V V V V mV mV A A A A V V -30 -100 2.0 4.0 1.0 1.0 A A mA mA mA mA @ 10 MHz @ 10 MHz HALT Mode VIN = 0V,VCC @ 10 MHz HALT Mode VIN = 0V,VCC @ 10 MHz 4,5 4,5 4,5 4,5 IOH = -2.0 mA IOH = -2.0 mA IOL = +4.0 mA IOL = +4.0 mA IOL = +6 mA, IOL = +12 mA, Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Notes
-1.0 -1.0 -1.0 -1.0
VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC 7 7
VSS-0.3 VCC -1.0 VSS-0.3 VCC -1.0 -10 -20 -60 -180 2.5 6.0 2.0 2.0
IIR
ICC ICC1
Supply Current Standby Current
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Zilog TA = 0 C to +70 C Sym Parameter ICC2 Standby Current VCC [3] 3.0V 5.5V Min Max 500 500 Typical [1] @ 25C 150 250 Units nA nA Conditions
Z8E001 CMOS OTP Microcontroller
Notes 6 6
STOP Mode VIN = 0V, VCC STOP Mode VIN = 0V,VCC
Notes: 1. Typical values are measured at VCC = 3.3V and VCC = 5.0V. 2. VSS = 0V = GND 3. The VCC voltage specification of 3.0 V guarantees 3.3 V +/- 0.3 V and the VCC voltage specification of 5.5 V guarantees 5.0 V +/- 0.5 V. 4. All outputs unloaded, I/O pins floating, and all inputs are at VCC or VSS level. 5. CL1 = CL2 = 22 pF. 6. Same as note [4] except inputs at VCC. 7. For analog comparator input when analog comparator is enabled.
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DC ELECTRICAL CHARACTERISTICS (Continued)
TA = -40C to +105C Min Max 0.7 VCC VCC+0.3 0.7 VCC VCC+0.3 VSS-0.3 VSS-0.3 0.2 VCC 0.2 VCC
Sym VCH
Parameter Clock Input High Voltage
VCC [3] 4.5V 5.5V
Typical [1] @ 25C 2.5 2.5 1.5 1.5 2.5 2.5 1.5 1.5 4.8 4.8
Units V V V V V V V V V V V V V V V V mV mV A A A A V V
Conditions Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator
Notes
VCL
Clock Input Low Voltage
4.5V 5.5V
VIH VIL VOH VOL1 VOL2 VRH
Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Low Voltage Reset Input High Voltage
4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V
0.7 VCC VCC+0.3 0.7 VCC VCC+0.3 VSS-0.3 VSS-0.3 VCC-0.4 VCC-0.4 0.4 0.4 1.2 1.2 0.5VCC 0.5VCC VCC VCC 25.0 25.0 2.0 2.0 2.0 2.0 VCC -1.5V VCC -1.5V -180 -180 7.0 7.0 2.0 2.0 0.2 VCC 0.2 VCC
IOH = -2.0 mA IOH = -2.0 mA IOL = +4.0 mA IOL = +4.0 mA IOL = +12 mA, IOL = +12 mA,
0.1 0.1 0.5 0.5 1.1 2.2 10.0 10.0 <1.0 <1.0 <1.0 <1.0
VOFFSET Comparator Input Offset Voltage IIL IOL VICR Input Leakage Output Leakage Comparator Input Common Mode Voltage Range Reset Input Current Supply Current Standby Current
-1.0 -1.0 -1.0 -1.0 0 0 -18 -18
VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC 7 7
IIR ICC ICC1
-112 -112 4.0 4.0 1.0 1.0
A A mA mA mA mA
@ 10 MHz @ 10 MHz HALT Mode VIN = 0V, VCC @ 10 MHz HALT Mode VIN = 0V, VCC @ 10 MHz
4,5 4,5 4,5 4,5
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Zilog TA = -40 C to +105 C Min Max 700 700
Z8E001 CMOS OTP Microcontroller
Typical [1] @ 25C 250 250 Units nA nA Conditions STOP Mode VIN = 0V, VCC STOP Mode VIN = 0V, VCC Notes 6 6
Sym ICC2
Parameter Standby Current
VCC[3] 4.5V 5.5V
Notes: 1. Typical values are measured at VCC = 3.3V and VCC = 5.0V. 2. VSS = 0V = GND 3. The VCC voltage specification of 3.0 V guarantees 3.3 V +/- 0.3 V and the VCC voltage specification of 5.5 V guarantees 5.0 V +/- 0.5 V. 4. All outputs unloaded, I/O pins floating, and all inputs are at VCC or VSS level. 5. CL1 = CL2 = 22 pF. 6. Same as note [4] except inputs at VCC. 7. For analog comparator input when analog comparator is enabled.
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Z8E001 CMOS OTP Microcontroller
Zilog
AC ELECTRICAL CHARACTERISTICS
1 CLOCK
3
2
2
3
IRQN
4
5
Figure 8. AC Electrical Timing Diagram
Additional Table
TA= 0 C to +70 C 10 MHz No 1 2 3 4 5 6 7 Symbol TpC TrC,TfC TwC TwIL TwIH Twsm Tost Parameter Input Clock Period Clock Input Rise and Fall Times Input Clock Width Int. Request Input Low Time Int. Request Input High Time STOP Mode Recovery Width Spec. Oscillator Start-Up Time VCC [2] 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V Min 100 100 Max DC DC 15 15 Units ns ns ns ns ns ns ns ns Notes 1 1 1 1 1 1 1 1 1 1
50 50 70 70 5TpC 5TpC 12 12 5TpC 5TpC
ns ns
Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. The VDD voltage specification of 3.0V guarantees 3.3V +/- 0.3V. The VDD voltage specification of 5.5V guarantees 5.0V +/- 0.5V.
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Z8E001 CMOS OTP Microcontroller
TA= -40 C to +105 C 10 MHz No 1 2 3 4 5 6 7 Symbol TpC TrC,TfC TwC TwIL TwIH Twsm Tost Parameter Input Clock Period Clock Input Rise and Fall Times Input Clock Width Int. Request Input Low Time Int. Request Input High Time STOP Mode Recovery Width Spec. Oscillator Start-Up Time VCC [2] 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V Min 100 100 Max DC DC 15 15 Units ns ns ns ns ns ns ns ns Notes 1 1 1 1 1 1 1 1 1 1
50 50 70 70 5TpC 5TpC 12 12 5TpC 5TpC
ns ns
Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. The VDD voltage specification of 3.0V guarantees 3.3V +/- 0.3V. The VDD voltage specification of 5.5V guarantees 5.0V +/- 0.5V.
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Z8E001 CMOS OTP Microcontroller
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Z8PLUS CORE
The Z8E001 is based on the Zilog Z8Plus Core Architecture. This core is capable of addressing up to 64KBytes of program memory and 4KBytes of RAM. Register RAM is accessed as either 8 or 16 bit registers using a combination of 4, 8, and 12 bit addressing modes. The architecture supports up to 15 vectored interrupts from external and internal sources. The processor decodes 44 CISC instructions using six addressing modes. See the Z8Plus User's Manual (UM97Z8X0300) for more information.
RESET
This section describes the Z8E001 reset conditions, reset timing, and register initialization procedures. Reset is generated by the Reset Pin, Watch-Dog Timer (WDT), and Stop-Mode Recovery (SMR). A system reset overrides all other operating conditions and puts the Z8E001 into a known state. To initialize the chip's internal logic, the /RESET input must be held Low for at least 30 XTAL clock cycles. The control registers and ports are reset to their default conditions after a reset from the /RESET pin. The control registers and ports are not reset to their default conditions after wakeup from Stop Mode or WDT timeout. During RESET, the program counter is loaded with 0020H. I/O ports and control registers are configured to their default reset state. Resetting the Z8E001 does not effect the contents of the general-purpose registers.
RESET PIN OPERATION
The Z8E001 hardware /RESET pin initializes the control and peripheral registers, as shown in Table 4. Specific reset values are shown by 1 or 0, while bits whose states are unchanged are indicated by the letter U. /RESET must be held low until the oscillator stabilizes, then for an additional 30 XTAL clock cycles to be sure that the internal reset is complete. The /RESET pin has a Schmitt-Trigger input with a trip point. There is no high side protection diode. The user should place an external diode from /RESET to VCC. A pull-up resistor on the /RESET pin is approximately 500 K-ohms, typical. Program execution starts 10 XTAL clock cycles after /RESET has returned High. The initial instruction fetch is from location 0020H. Figure 7 shows reset timing. After a reset, the first routine executed must be one that initializes the TCTLHI control register to the required system configuration, followed by initialization of the remaining control registers.
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Zilog Table 5. Control and Peripheral Register Reset Values Register (HEX) FF FE FD FC FB FA F9-F0 EF-E0 DF-D8 D7 D6 D5 D4 D3 D2 D1 D0 CF CE CD CC CB CA C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 Register Name Stack Pointer Reserved Register Pointer Flags Interrupt Mask Interrupt Request Reserved Virtual Copy Reserved PortB Spec. Func. PortB Control PortB Output PortB Input PortA Spec. Func. PortA Control PortA Output PortA Input Reserved Reserved T1VAL T0VAL T3VAL T2VAL T3AR T2AR T1ARHI T0ARHI T1ARLO T0ARLO WDTHI WDTLO TCTLHI TCTLLO Bits 43 U U U 0 0 U 0 U 0 0
Z8E001 CMOS OTP Microcontroller
7 0 U U 0 0
6 0 U U 0 0
5 U U U 0 0
2 U 0 U 0 0
1 U 0 * 0 0
0 U 0 * 0 0
Comments Stack pointer is not affected by RESET Register pointer is not affected by RESET Only WDT & SMR flags are affected by RESET All interrupts masked by RESET All interrupt requests cleared by RESET Virtual Copy of the Current Working Register Set
0 0 U U 0 0 U U
0 0 U U 0 0 U U
0 0 U U 0 0 U U
0 0 U U 0 0 U U
0 0 U U 0 0 U U
0 0 U U 0 0 U U
0 0 U U 0 0 U U
0 0 U U 0 0 U U
Deactivates all port special functions after RESET Defines all bits as inputs in PortB after RESET Output register not affected by RESET Current sample of the input pin following RESET Deactivates all port special functions after RESET Defines all bits as inputs in PortA after RESET Output register not affected by RESET Current sample of the input pin following RESET
U U U U U U U U U U 1 1 1 0
U U U U U U U U U U 1 1 1 0
U U U U U U U U U U 1 1 1 0
U U U U U U U U U U 1 1 1 0
U U U U U U U U U U 1 1 1 0
U U U U U U U U U U 1 1 0 0
U U U U U U U U U U 1 1 0 0
U U U U U U U U U U 1 1 0 0
WDT Enabled in HALT Mode, WDT timeout at maximum value, STOP Mode disabled All standard timers are disabled
* The SMR and WDT flags are set indicating the source of the RESET. D1 0 0 1 1 D0 0 1 0 1 Reset Source /RESET Pin SMR Recovery WDT Reset Reserved
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Zilog
First Machine Cycle Clock
/RESET Hold Low For 30 XTAL Periods (Minimum) 10 XTAL CLOCK CYCLES
First Instruction Fetch
Figure 9. Reset Timing
VCC 100 K
VCC 500 K /RESET 1 F Z8E001
1K
Figure 10. Example of External Power-On Reset Circuit
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Z8E001 CMOS OTP Microcontroller
TCTLHI D6,D5,D4 3
WDT Tap Select
WDT TAP SELECT
XTAL
/64
/WDTRST 16-BIT TIMER /WDTRST
WatchDog Timer
SMR (PB0) SMR RECOVERY
Figure 11. Z8E001 Reset Circuitry with WDT and SMR
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Z8E001 WATCH-DOG TIMER (WDT)
The WDT is a retriggerable one-shot 16-bit timer that resets the Z8E001 if it reaches its terminal count. The WDT is driven by the XTAL2 clock pin. In order to provide the longer timeout periods desired in applications, the watchdog timer is only updated every 64th clock cycle. When operating in the RUN or HALT Modes, a WDT timeout reset is functionally equivalent to an interrupt vectoring the PC to 0020H and setting the WDT flag to a one state. Coming out of RESET, the WDT will be fully enabled with its timeout value set at the maximum value, unless otherwise programmed during the first instruction. Subsequent executions of the WDT instruction reinitialize the watchdog timer registers, C2H and C3H, to their initial values as defined by bits D6, D5, and D4 of the TCTLHI register. The WDT cannot be disabled except on the first cycle after RESET, and if the device enters Stop mode. The WDT instruction should be executed often enough to provide some margin before allowing the WDT registers to get near 0. Because the WDT timeout periods are relatively long, a WDT reset will occur in the unlikely event that the WDT times out on exactly the same cycle that the WDT instruction is executed. The WDT and SMR flags are the only flags that are affected by the external RESET pin. /RESET clears both the WDT and SMR flags. A WDT timeout sets the WDT flag. The STOP instruction sets the SMR flag. This behavior enables software to determine whether a pin RESET occurred, or whether a WDT timeout occurred, or whether a return from STOP Mode occurred. Reading the WDT flag does not reset it to zero, the user must clear it via software. Failure to clear the flag may result in undefined behavior.
0C1
TCTLHI D6 D5 D4 D3 D2 D1 D0
D7
RESERVED (MUST BE 0) 0 = STOP MODE ENABLED 1 = STOP MODE DISABLED* D6 D5 D4 WDT TIMEOUT VALUE ---- --- ---- -------------------------------0 00 DISABLED 0 01 65,536 TpC 0 10 131,072 TpC 0 11 262,144 TpC 1 00 524,288 TpC 1 01 1,048,576 TpC 1 10 2,097,152 TpC 1 11 4,194,304 TpC* (XTAL CLOCKS TO TIMEOUT) 1 = WDT ENABLED IN HALT MODE* 0 = WDT DISABLED IN HALT MODE
* Designates Default Value after RESET
Figure 12. Z8E001 TCTLHI Register for Control of WDT
Note: The WDT can only be disabled via software if the first instruction out of RESET performs this function. Logic within the Z8E001 will detect that it is in the process of executing the first instruction after the part leaves RESET.
During the execution of this instruction, the upper five bits of the TCTLHI register can be written. After this first instruction, hardware will not allow the upper five bits of this register to be written.
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Zilog The TCTLHI bits for control of the WDT are described below: WDT Time Select (D6, D5, D4). Bits 6, 5, and 4 determine the time-out period. Figure 11 shows the range of timeout values that can be obtained. The default values of D6, D5, and D4 are all 1, thus setting the WDT to its maximum timeout period when coming out of RESET. Figure 13. Time-Out Period of the WDT Crystal Clocks to Timeout Disabled 65,536 TpC 131,072 TpC 262,144 TpC 524,288 TpC 1,048,576 TpC 2,097,152 TpC 4,194,304 TpC Time-Out Using a 10 MHZ Crystal Disabled 6.55 ms 13.11 ms 26.21 ms 52.43 ms 104.86 ms 209.72 ms 419.43 ms
Z8E001 CMOS OTP Microcontroller WDT During HALT (D7). This bit determines whether or not the WDT is active during HALT Mode. A 1 indicates active during HALT. A 0 prevents the WDT from resetting the part while halted.Coming out of reset, the WDT will be enabled during HALT Mode. STOP MODE (D3). Coming out of RESET, the Z8E001 will have STOP Mode disabled. If an application desires to use STOP Mode, bit D3 must be cleared immediately upon leaving RESET. If bit D3 is set, the STOP instruction will execute as a NOP. If bit D3 is cleared, the STOP instruction will enter Stop Mode. Whenever the Z8E001 wakes up after having been in STOP Mode, the STOP Mode will, once again, be disabled. Bits 2, 1 and 0. These bits are reserved and must be 0.
D6 0 0 0 0 1 1 1 1
D5 0 0 1 1 0 0 1 1
D4 0 1 0 1 0 1 0 1
Notes: TpC = XTAL clock cycle The default on reset is D6 = D5 = D4 = 1.
POWER-DOWN MODES
In addition to the standard RUN mode, the Z8E001 MCU supports two Power-Down modes to minimize device current consumption. The two modes supported are HALT and STOP.
HALT MODE OPERATION
The HALT Mode suspends instruction execution and turns off the internal CPU clock. The on-chip oscillator circuit remains active so the internal clock continues to run and is applied to the timers and interrupt logic. To enter the HALT Mode, the Z8E001 only needs to execute a HALT instruction. It is NOT necessary to execute a NOP instruction immediately before the HALT instruction. The HALT Mode may be exited by servicing an interrupt, either externally or internally generated. Upon completion of the interrupt service routine, the user program continues from the instruction after the HALT instruction. The HALT Mode may also be exited via a /RESET activation or a Watch-Dog Timer (WDT) timeout. In these cases, program execution will restart at the reset restart address 0020H.
7F
HALT
;enter HALT Mode
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STOP MODE OPERATION
The STOP Mode provides the lowest possible device standby current. This instruction turns off the on-chip oscillator and internal system clock. To enter the STOP Mode, the Z8E001 only needs to execute a STOP instruction. It is NOT necessary to execute a NOP instruction immediately before the STOP instruction., The Z8E001 provides a dedicated STOP-Mode Recovery (SMR) circuit. In this case, a low level applied to input pin PB0 will trigger a SMR. To use this mode, pin PB0 (I/O Port B, bit 0) must be configured as an input before the STOP Mode is entered. The low level on PB0 must be held for a minimum pulse width TWSM. Note: Use of the PB0 input for the stop mode recovery does not initialize the control registers. 6F STOP ;enter STOP Mode Note: The STOP Mode current (ICC2) will be minimized when:
s s s
The STOP Mode is exited by any one of the following resets: /RESET pin or a STOP-Mode Recovery source. Upon reset generation, the processor will always restart the application program at address 0020H and the STOP Mode Flag will be set. Reading this flag does not clear it, the user must clear this flag with software. Failure to clear this flag may result in undefined behavior.
VCC is at the low end of the devices operating range. Output current sourcing is minimized. All inputs (digital and analog) are at the low or high rail voltages.
CLOCK
The Z8E001 MCU derives its timing from on-board clock circuitry connected to pins XTAL1 and XTAL2. The clock circuitry consists of an oscillator, a glitch filter, a divide-bytwo shaping circuit, a divide-by-four shaping circuit, and a divide-by-eight shaping circuit. Figure 12 illustrates the clock circuitry. The oscillator's input is XTAL1 and its output is XTAL2. The clock can be driven by a crystal, a ceramic resonator, LC clock, or an external clock source.
XTAL1
Glitch Filter
/2
Machine Clock (5 cycles per instruction) Timer Clock
XTAL2
/4
/8
WDT Clock
Figure 14. Z8E001 Clock Circuit
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Z8E001 CMOS OTP Microcontroller
OSCILLATOR OPERATION
The Z8E001 MCU uses a Pierce oscillator with an internal feedback (Figure 13). The advantages of this circuit are low cost, large output signal, low-power level in the crystal, stability with respect to VCC and temperature, and low impedances (not disturbed by stray effects). One draw back is the need for high gain in the amplifier to compensate for feedback path losses. The oscillator amplifies its own noise at start-up until it settles at the frequency that satisfies the gain/phase requirements A x B = 1, where A = V0/Vi is the gain of the amplifier and B = Vi/V0 is the gain of the feedback element. The total phase shift around the loop is forced to zero (360 degrees). Since VIN must be in phase with itself, the amplifier/inverter provides 180 degree phase shift and the feedback element is forced to provide the other 180 degrees of phase shift. R1 is a resistive component placed from output to input of the amplifier. The purpose of this feedback is to bias the amplifier in its linear region and to provide the start-up transition. Capacitor C2 combined with the amplifier output resistance provides a small phase shift. It will also provide some attenuation of overtones. Capacitor C1 combined with the crystal resistance provides additional phase shift. C1 and C2 can affect the start-up time if they increase dramatically in size. As C1 and C2 increase, the start-up time increases until the oscillator reaches a point where it does not start up any more. It is recommended for fast and reliable oscillator start-up (over the manufacturing process range) that the load capacitors be sized as low as possible without resulting in overtone operation.
Z8E001 A V1 RI V0
VSS
XTAL1
XTAL2
C1
C2
Figure 15. Pierce Oscillator with Internal Feedback Circuit
Layout
Traces connecting crystal, caps, and the Z8E001 oscillator pins should be as short and wide as possible. This reduces parasitic inductance and resistance. The components (caps, crystal, resistors) should be placed as close as possible to the oscillator pins of the Z8E001. The traces from the oscillator pins of the IC and the ground side of the lead caps should be guarded from all other traces (clock, VCC, address/data lines, system ground) to reduce cross talk and noise injection. This is usually accomplished by keeping other traces and system ground trace planes away from the oscillator circuit and by placing a Z8E001 device VSS ground ring around the traces/components. The ground side of the oscillator lead caps should be connected to a single trace to the Z8E001 VSS (GND) pin. It should not be shared with any other system ground trace or components except at the Z8E001 device VSS pin. This is to prevent differential system ground noise injection into the oscillator (Figure 14).
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Indications of an Unreliable Design
There are two major indicators that are used in working designs to determine their reliability over full lot and temperature variations. They are: Start-up Time. If start -up time is excessive, or varies widely from unit to unit, there is probably a gain problem. C1/C2 needs to be reduced; the amplifier gain is not adequate at frequency, or crystal Rs is too large. Output Level. The signal at the amplifier output should swing from ground to VCC. This indicates there is adequate gain in the amplifier. As the oscillator starts up, the signal amplitude grows until clipping occurs, at which point the loop gain is effectively reduced to unity and constant oscillation is achieved. A signal of less than 2.5 volts peak-topeak is an indication that low gain may be a problem. Either C1 or C2 should be made smaller or a low-resistance crystal should be used.
Circuit Board Design Rules
The following circuit board design rules are suggested:
s
To prevent induced noise the crystal and load capacitors should be physically located as close to the Z8E001 as possible. Signal lines should not run parallel to the clock oscillator inputs. In particular, the crystal input circuitry and the internal system clock output should be separated as much as possible. VCC power lines should be separated from the clock oscillator input circuitry. Resistivity between XTAL1 or XTAL2 and the other pins should be greater than 10 Mohms.
s
s
s
XTAL1
17
C1
Z8E001 XTAL2 16 C2 VSS 15 Clock Generator Circuit
Signals A B (Parallel Traces Must Be Avoided) Signal C Z8E001
PB0
X1 X2
VSS
XTAL1 17
Z8E001
XTAL2 16
VCC
Board Design Example (Top View)
Figure 16. Circuit Board Design Rules
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Z8E001 CMOS OTP Microcontroller In most cases, the RD is 0 Ohms and RF is infinite. It is determined and specified by the crystal/ceramic resonator manufacturer. The RD can be increased to decrease the amount of drive from the oscillator output to the crystal. It can also be used as an adjustment to avoid clipping of the oscillator signal to reduce noise. The RF can be used to improve the start-up of the crystal/ceramic resonator. The Z8E001 oscillator already has an internal shunt resistor in parallel to the crystal/ceramic resonator.
Crystals and Resonators
Crystals and ceramic resonators (Figure 15) should have the following characteristics to ensure proper oscillator operation: Crystal Cut Mode Crystal Capacitance Load Capacitance Resistance AT (crystal only) Parallel, Fundamental Mode <7pF 10pF < CL < 220 pF, 15 typical 100 ohms max
XTAL1
Depending on operation frequency, the oscillator may require the addition of capacitors C1 and C2 (shown in Figures 15 and16). The capacitance values are dependent on the manufacturer's crystal specifications. N/C
VSS Z8E001 XTAL1 RF XTAL2 RD
Z8E001 VSS XTAL2
Figure 19. External Clock It is recommended in Figures 14, 15, and 16 to connect the load capacitor ground trace directly to the VSS (GND) pin of the Z8E001. This ensures that no system noise is injected into the Z8E001 clock. This trace should not be shared with any other components except at the VSS pin of the Z8E001. Please note that a parallel resonant crystal or resonator data sheet will specify a load capacitor value that is the series combination of C1 and C2, including all parasitics (PCB and holder).
C1
C2
Figure 17. Crystal/Ceramic Resonator Oscillator
XTAL1 C1 L Z8E001 VSS XTAL2 C2
Figure 18. LC Clock
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LC OSCILLATOR
The Z8E001 oscillator can use a LC network to generate a XTAL clock (Figure 16). The frequency stays stable over VCC and temperature. The oscillation frequency is determined by the equation: 1 Frequency = 2 (LCT) 1/2 Simple series capacitance is calculated using the following equation: 1/ CT If C1 1/CT C1 = 1/C1 + 1/C2 = C2 = 2 C1 = 2CT
where L is the total inductance including parasitics and CT is the total series capacitance including the parasitics.
Sample calculation of capacitance C1 and C2 for 5.83 MHz frequency and inductance value of 27 uH: 5.83 (10^6) = CT = 27.6 pf Thus C1 = 55.2 pf and C2 = 55.2 pf. 1 2 [2.7 (10-6) CT] 1/2
TIMERS
For the Z8E001, 8-bit timers T0 and T1 are available to function as a pair of independent 8-bit standard timers, or they can be cascaded to function as a 16-bit PWM timer. In addition, 8-bit timers T2 and T3 are provided but they can only operate in cascade to function as a 16-bit standard timer.
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Internal Data Bus
8-bit Standard Timer
T1ARHI
T1ARLO
T1VAL
OSC /8
8-bit Down Counter
IRQ2 (T1) ENABLE TCTLLO (D2-D0)
16-bit PWM Timer
16-bit INITIALIZATION REGISTER
16-bit DOWN COUNTER
IRQ0 IRQ2
8-bit Down Counter
ENABLE TCTLL0 (D2-D0) IRQ0 (T0)
8-bit Standard Timer
T0ARHI
T0ARLO
T0VAL
OSC /8
Internal Data Bus ENABLE TCTLLO (D5) 16-bit Standard Timer IRQ5 (T23) OSC /8 16-bit DOWN COUNTER
T3VAL
T3AR
T2AR
T2VAL
Internal Data Bus Figure 20. Timers Block Diagram DS97Z8X1300 PRELIMINARY 27
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Zilog
0C0
TCTLLO D6 D5 D4 D3 D2 D1 D0
D7
D2 D1 D0 ---- ---- --0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11
TIMER STATUS T0 T1 T01 ------------ ------------ --------------DISAB. DISAB. ENAB. DISAB. DISAB. ENAB. ENAB. ENAB. ENAB.(*) ENAB.(*) DISAB. DISAB. ENAB.(*) ENAB.(*) ENAB.(*)
(NOTE: (*) INDICATES AUTO-RELOAD IS ACTIVE.) RESERVED (MUST BE 0) 1 = T23 16-BIT TIMER ENABLED WITH AUTO-RELOAD ACTIVE 0 = T2 AND T3 TIMERS DISABLED RESERVED (MUST BE 0 )
NOTE: TIMER T01 IS A 16-BIT PWM TIMER FORMED BY CASCADING 8-BIT TIMERS T1 (MSB) AND T0 (LSB). TIMER T23 IS A STANDARD 16-BIT TIMER FORMED BY CASCADING 8-BIT TIMERS T3(MSB) AND T2(LSB).
Figure 21. TCTLLO Register
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Zilog Each 8-bit timer is given a pair of registers, which are both readable and writable. One of the registers is defined to contain the auto-initialization value for the timer, while the second register contains the current value for the timer. When a timer is enabled, the timer will decrement whatever value is currently held in its count register, and will then continue decrementing until it reaches 0, at which time an interrupt will be generated and the contents of the auto-initialization register are optionally copied into the count value register. If auto-initialization is not enabled, the timer will stop counting upon reaching 0 and control logic will clear the appropriate control register bit to disable the timer.This is referred to as "single-shot" operation. If auto-initialization is enabled, the timer will continue counting from the initialization value. Software should not attempt to use registers that are defined as having timer functionality. Software is allowed to write to any register at any time, but care should be taken if timer registers be updated while the timer is enabled. If software updates the count value while the timer is in operation, the timer will continue counting based upon the software-updated value. This can produce strange behavior if the software update occurred at exactly the point that the timer was reaching 0 to trigger an interrupt and/or reload. Similarly, if software updates the initialization value register while the timer is active, the next time that the timer reaches 0, it will be initialized using the updated value. Again, strange behavior could result if the initialization value register is being written while the timer is in the process of being initialized. Whether initialization is done with the new or old value is a function of the exact timing of the write operation. In all cases, the Z8E001 will prioritize the software write above that of a decrementer writeback. However, when hardware clears a control register bit for a timer that is configured for single-shot operation; the clearing of the control bit will override a software write. Reading either register can be done at any time, and will have no effect on the functionality of the timer. If a timer pair is defined to operate as a single 16-bit entity, the entire 16-bit value must reach 0 before an interrupt is generated. In this case, a single interrupt will be generated, and the interrupt will correspond to the even 8-bit timer. For example, timers T2 and T3 are cascaded to form a single 16-bit timer, so the interrupt for the combined timer will be defined to be that of timer T2 rather than T3. When a timer pair is specified to act as a single 16-bit timer, the even timer registers in the pair (timer T0 or T2) will be defined to hold the timer's least significant byte; while the odd timer in the pair will hold the timer's most significant byte. In parallel with the posting of the interrupt request, the interrupting timer's count value will be initialized by copying the contents of the auto-initialization value register to the count value register. It should be noted that any time that a timer pair is defined to act as a single 16-bit timer, that
Z8E001 CMOS OTP Microcontroller the auto-reload function will be performed automatically. All 16-bit timers will continue counting while their interrupt requests are active, and will operate in a free-running manner. If interrupts are disabled for a long period of time, it is possible for the timer to decrement to 0 again before its initial interrupt has been responded to. This is a degenerate case, and hardware is not required to detect this condition. When the timer control register is written, all timers that are enabled by the write will begin counting using the value that is held in their count register. An auto-initialization is not performed. All timers can receive an internal clock source only. Each timer that is enabled will be updated every 8th XTAL clock cycle. If T0 and T1 are defined to work independently, then each will work as an 8-bit timer with a single auto-initialization register; T0ARLO for T0, and T1ARLO for T1. Each timer will assert its predefined interrupt when it times out, and will optionally perform the auto-initialization function. If T0 and T1 are cascaded to form a single 16-bit timer, then the single 16-bit timer will be capable of performing as a PulseWidth Modulator (PWM). This timer is referred to as T01 to distinguish it as having special functionality that is not available when T0 and T1 act independently. When T01 is enabled, it can use a pair of 16-bit auto-initialization registers. In this mode, one 16-bit auto-initialization value is composed of the concatenation of T1ARLO and T0ARLO, and the second auto-initialization value is composed of the concatenation of T1ARHI and T0ARHI. When T01 times out, it will alternately initialize its count value using the LO auto-init pair followed by the HI auto-init pair. This functionality corresponds to a PWM where the T1 interrupt will define the end of the HI section of the waveform, and the T0 interrupt will mark the end of the LO portion of the PWM waveform. To use the cascaded timers as a PWM, one must initialize the T0 and T1 count registers to work in conjunction with the port pin. The user should initialize the T0 and T1 count registers to the PWM_HI auto-init value to obtain the desired PWM behavior. The PWM is arbitrarily defined to use the LO autoreload registers first. This implies that it had just timed out after beginning in the HI portion of the PWM waveform. As such, the PWM is defined to assert the T1 interrupt after the first timeout interval. After the auto-initialization has been completed, decrementing occurs for the number of counts defined by the PWM_LO registers. When decrementing again reaches 0, the T0 interrupt is asserted; and auto-init using the PWM_HI registers occurs. Decrementing occurs for the number of counts defined by the PWM_HI registers until reaching 0, at which time the the T1 interrupt is asserted, and the cycle begins again.
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Z8E001 CMOS OTP Microcontroller The internal timers can be used to trigger external events by toggling the PB1 output when generating an interrupt. This functionality can only be achieved in conjunction with the port unit defining the appropriate pin as an output signal with the timer output special function enabled. In this mode, the appropriate port output will be toggled when the timer count reaches 0, and will continue toggling each time that the timer times out.
Zilog BCTL bit 1 to 1. Configured in this way, PB1 has the capability of being a clock output for timer0, toggling the PB1 output pin on each timer0 timeout. At end-of-count, the interrupt request line IRQ0 , clocks a toggle flip-flop. The output of this flip-flop drives the TOUT line, PB1. In all cases, when timer0 reaches its end-ofcount, TOUT toggles to its opposite state (Figure 22). If, for example, timer0 is in Continuous Counting Mode, Tout will have a 50 percent duty cycle output. This duty cycle can easily be controlled by varying the initial values after each end-of-count.
TOUT Mode
The PortB special function register PTBSFR (0D7H) (Figure 20), is used in conjunction with the Port B directional control register PTBDIR (0D6) (Figure 21) to configure PB1 for TOUT operation for timer0. In order for TOUT to function, PB1 must be defined as an output line by setting PT-
0D7
PTBSFR D6 D5 D4 D3 D2 D1 D0
D7
1 = ENABLE BIT 0 AS SMR INPUT 0 = NO SPECIAL FUNCTIONALITY 1 = ENABLE BIT 1 AS TIMER0 OUTPUT 0 = NO SPECIAL FUNCTIONALITY 1 = ENABLE BIT 2 AS INT1 INPUT 0 = NO SPECIAL FUNCTIONALITY
D4 D3 COMPAR. INTERRUPTS --- --- -------------- ------------------0 0 DISABLED DISABLED 0 1 ENABLED DISABLED 1 0 DISABLED ENABLED 1 1 ENABLED ENABLED BIT 3: COMP. REF. INPUT BIT 4: COMP. SIGNAL INPUT/ INT0/INT2 RESERVED (MUST BE 0)
Figure 22. PortB Special Function Register (Tout Operation)
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0D6
PTBDIR D6 D5 D4 D3 D2 D1 D0
D7
1 = BIT N SET AS OUTPUT 0 = BIT N SET AS INPUT RESERVED (MUST BE 0) Figure 23. PortB Directional Control Register
IRQ0 (T0 End-of-Count)
/2
PB1
TOUT
Figure 24. Timer T0 Output Through TOUT
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RESET CONDITIONS
After a hardware RESET, the timers are disabled. See Table 4 for timer control, value, and auto-initialization register status after RESET.
I/O PORTS
The Z8E001 has 13 lines dedicated to input and output. These lines are grouped into two ports known as Port A and Port B. Port A is an 8-bit port, bit programmable as either inputs or outputs. Port B can be programmed to provide standard input/output or the following special functions: timer0 output, comparator input, SMR input, and external interrupt inputs. All ports have push-pull CMOS outputs. In addition, the outputs of Port A on a bit-wise basis may be configured for open-drain operation.The ports operate on a bit-wise basis. As such, the register values for/at a given bit position only affect the bit in question. Each port is defined by a set of four control registers. See Figure 25, below. Each port on the Z8E001 has a Special Function Register that in conjunction with the directional control register implements, on a bit-wise basis, any special functionality that may be defined for each particular port bit.
Input and Output Value Registers
Each port has an Output Value Register and an Input Value Register. For port bits configured as an input by means of the Directional Control Register, the Input Value Register for that bit position will contain the current synchronized input value. For port bits configured as an output by means of the Directional Control Register, the value held in the corresponding bit of the Output Value Register is driven directly onto the output pin. The opposite register bit for a given pin (the output register bit for an input pin and the input register bit for an output pin) will hold their previous value. They will not be changed by hardware nor will they have any effect on the hardware.
Directional Control and Special Function Registers
Each port on the Z8E001 has an associated, dedicated Directional Control Register that determines on a bit-wise basis whether a given port bit will operate as an input or as an output.
REGISTER Port B SPECIAL FUNCTION Port B DIRECTION CONTROL Port B OUTPUT VALUE Port B INPUT VALUE Port A SPECIAL FUNCTION Port A DIRECTION CONTROL Port A OUTPUT VALUE Port A INPUT VALUE
ADDRESS IDENTIFIER 0D7H 0D6H 0D5H 0D4H 0D3H 0D2H 0D1H 0D0H PTBSFR PTBDIR PTBOUT PTBIN PTASFR PTADIR PTAOUT PTAIN
Figure 25. Z8E001 I/O Ports Registers
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READ/WRITE OPERATIONS
The control for each port is done on a bit-wise basis. All bits are capable of operating as inputs or outputs, depending upon the setting of the port's directional control register. If configured as an input, each bit is given a Schmitttrigger. The output of the Schmitt-trigger is latched twice to perform a synchronization function, and the output of the synchronizer is fed to the port input register, which can be read by software. A write to a port input register has the effect of updating the contents of the input register, but subsequent reads will not necessarily return the same value that was written. If the bit in question is defined as an input, the input register for that bit position will contain the current synchronized input value. Thus, writes to that bit position will be overwritten on the next clock cycle with the newly sampled input data. However, if the particular port bit is programmed as an output, the input register for that bit will retain the software-updated value since the port bits that are programmed as outputs do not sample the value being driven out. Any bit in either port can be defined as an output by setting the appropriate bit in the directional control register. If this is the case, the value held in the appropriate bit of the port output register is driven directly onto the output pin. Note, however, that this does not necessarily reflect the actual output value. If an external error is holding an output pin either high or low against the output driver, the software read will return the DESIRED value, not the actual state caused by the contention. When a bit is defined as an output , the Schmitt-trigger on the input will be disabled to save power. Updates to the output register will take effect based upon the timing of the internal instruction pipeline, but will be referenced to the rising edge of the clock. The output register can be read at any time, and will return the current output value that is held. No restrictions are placed on the timing of reads and/or writes to any of the port registers with respect to the others, but care should be taken when updating the directional control and special function registers. When updating a directional control register, the special function register should first be disabled. If this precaution is not taken, spurious events could take place as a result of the change in port I/O status. This is especially important when defining changes in Port B, since the spurious event referred to above could be one or more interrupts. Clearing of the SFR register should be the first step in configuring the port, and setting the SFR register should be the last step in the port configuration process. To ensure deterministic behavior, the SFR register should not be written until the pins are being driven appropriately and all initialization has been completed.
PORT A
Port A is a general-purpose port. Figure 25 shows a block diagram of Port A. Each of its lines can be independently programmed as input or output via the Port A Directional Control Register (PTADIR at 0D2H) as seen in Figure 24. A bit set to a 1 in PTADIR configures the corresponding bit in Port A as an output, while a bit cleared to 0 configures the corresponding bit in Port A as an input.
Register 0D2H PTADIR Register D7 D6 D5 D4 D3 D2 D1 D0 1 = Output 0 = Input
The input buffers are Schmitt-triggered. Bits programmed as outputs may be individually programmed as either push-pull or open drain by setting the corresponding bit in the Special Function Register (PTASFR, Figure 29.)
Figure 26. Port A Directional Control Register
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PTASF.bitN N = 0...7 PTADIR.bitN N = 0...7 PA0-PA7 PIN
PTAOUT.bitN N = 0...7
PTAIN.bitN N = 0...7
Figure 27. Port A Configuration with Open-Drain Capability and Schmitt-Trigger
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Z8E001 CMOS OTP Microcontroller Port A Input Value Register
Port A Register Diagrams
Register 0D0H
PTAIN D5 D4 D3 D2 D1 D0
D7
D6
PORT A BIT N CURRENT INPUT VALUE (only updated for pins in input mode)
Figure 28. Port A Input Value Register Port A Output Value Register
Register 0D1H
PTAOUT D5 D4 D3 D2 D1 D0
D7
D6
PORT A BIT N CURRENT OUTPUT VALUE
Figure 29. Port A Output Value Register
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Z8E001 CMOS OTP Microcontroller Port A Directional Control Register
Zilog
Register 0D2H
PTADIR D5 D4 D3 D2 D1 D0
D7
D6
1 = BIT N SET AS AN OUTPUT 0 = BIT N SET AS AN INPUT
Figure 30. Port A Directional Control Register Port A Special Function Register
Register 0D3H
PTASFR D5 D4 D3 D2 D1 D0
D7
D6
1 = BIT N IN OPEN-DRAIN MODE 0 = BIT N IN PUSH-PULL MODE
Figure 31. Port A Special Function Register
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PORT B Port B Description
Port B is a 5-bit, bidirectional, CMOS-compatible I/O port. These five I/O lines can be configured under software control to be an input or output, independently. Input buffers are Schmitt-triggered. See Figures 31 through 34 for diagrams of all five Port B pins. In addition to standard input/output capability on all five pins of Port B, each pin provides special functionality as shown in the following table: Table 6. Port B Special Functions Port Pin PB0 PB1 PB2 PB3 PB4 Input Special Function Stop Mode Recovery Input None Interrupt1 Comparator Reference Input Comparator Signal Input/Interrupt0/ Interrupt2 Output Special Function None Timer0 Output None None None
Special functionality is invoked via the Port B Special Function Register. See Figure 30 for the arrangement and control conventions for this register.
Register 0D7H
PTBSFR D5 D4 D3 D2 D1 D0
D7
D6
1 = ENABLE PB0 AS SMR INPUT 0 = NO SPECIAL FUNCTIONALITY 1 = ENABLE PB1 AS TIMER0 OUTPUT 0 = NO SPECIAL FUNCTIONALITY 1 = ENABLE PB2 AS INT1 INPUT 0 = NO SPECIAL FUNCTIONALITY 1 = Analog Comparator on PB3 & PB4 0 = Digital Inputs on PB3 & PB4 1 = PB4 Interrupts Enabled 0 = PB4 Interrupts Disabled
RESERVED (MUST BE 0)
Figure 32. Port B Special Function Register
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Z8E001 CMOS OTP Microcontroller
Zilog
PORT B - PIN 0 CONFIGURATION
PTBDIR.bit0
PTBIN.bit0
SMR RESET
PTBSF.bit0 SMR Flag
PTBDIR.bit0 PB0 PIN
PTBOUT.bit0
Figure 33. Port B Pin 0 Diagram
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Z8E001 CMOS OTP Microcontroller
PORT B - PIN 1 CONFIGURATION
PTBDIR.bit1
PTBIN.bit1
PTBDIR.bit1 PB1 PIN
PTBOUT.bit1 TIMER0 Output PTBSF.bit1
M U X
Figure 34. Port B Pin 1 Diagram
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Z8E001 CMOS OTP Microcontroller
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PORT B - PIN 2 CONFIGURATION
PTBDIR.bit2
PTBIN.bit2 INT1 EDGE DETECT LOGIC PTBSF.bit2
PTBDIR.bit2 PB2 PIN
PTBOUT.bit2
Figure 35. Port B Pin 2 Diagram
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PORT B - PINS 3 AND 4 CONFIGURATION
PTBDIR.bit4 PTBIN.bit4 M U X AN IN
INT0 INT2
EDGE DETECT LOGIC
PTBSF.bit4 PTBSF.bit3
+ REF
PTBDIR.bit3 PTBIN.bit3
PTBDIR.bit3 PB3 PIN
PTBOUT.bit3
PTBDIR.bit4 PB4 PIN
PTBOUT.bit4
Figure 36. Port B Pins 3 and 4 Diagram
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PORT B CONTROL REGISTERS
Register 0D4H
PTBIN D5 D4 D3 D2 D1 D0
D7
D6
PORT B BIT N CURRENT INPUT VALUE (only updated for pins in input mode) RESERVED (MUST BE 0)
Figure 37. Port B Input Value Register
Register 0D5H
PTBOUT D5 D4 D3 D2 D1 D0
D7
D6
PORT B BIT N CURRENT OUTPUT VALUE RESERVED (MUST BE 0)
Figure 38. Port B Output Value Register
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Register 0D6H
PTBDIR D5 D4 D3 D2 D1 D0
D7
D6
1 = BIT N SET AS OUTPUT 0 = BIT N SET AS INPUT RESERVED (MUST BE 0)
Figure 39. Port B Directional Control Register
Register 0D7H
PTBSFR D5 D4 D3 D2 D1 D0
D7
D6
1 = ENABLE PB0 AS SMR INPUT 0 = NO SPECIAL FUNCTIONALITY 1 = ENABLE PB1 AS TIMER0 OUTPUT 0 = NO SPECIAL FUNCTIONALITY 1 = ENABLE PB2 AS INT1 INPUT 0 = NO SPECIAL FUNCTIONALITY 1 = Analog Comparator on PB3 & PB4 0 = Digital Inputs on PB3 & PB4 1 = PB4 Interrupts Enabled 0 = PB4 Interrupts Disabled
RESERVED (MUST BE 0)
Figure 40. Port B Special Function Register
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I/O PORT RESET CONDITIONS Full Reset
Port A and Port B output value registers are not affected by RESET. On RESET, the Port A and Port B directional control registers will be cleared to all zeros, which will define all pins in both ports as inputs. On RESET, since the directional control registers have redefined all pins as inputs, the Port A and Port B input value registers will have the previously held data overwritten with the current sample of the input pins. On RESET, the Port A and Port B special function registers will be cleared to all zeros, which will deactivate all port special functions. Note: The SMR and WDT timeout events are NOT full device resets. None of the port control registers is effected by either of these events.
ANALOG COMPARATOR
The Z8E001 includes one on-chip analog comparator. Pin PB4 has a comparator front end. The comparator reference voltage is on pin PB3. When the analog comparator function is enabled, bit 4 of the input register will be defined as holding the synchronized output of the comparator, while bit 3 will retain a synchronized sample of the reference input. If the interrupts for PB4 are enabled when the comparator special function is selected, the output of the comparator will generate interrupts.
Comparator Description
The on-chip comparator can process an analog signal on PB4 with reference to the voltage on PB3. The analog function is enabled by programming the Port B Special Function Register bits 3 and 4.
COMPARATOR OPERATION
The comparator output reflects the relationship between the analog input to the reference input. If the voltage on the analog input is higher than the voltage on the reference input, then the comparator output will be at a high state. If the voltage on the analog input is lower than the voltage on the reference input, then the analog output will be at a Low state.
HALT Mode
The analog comparator is functional during HALT Mode. If the interrupts are enabled, an interrupt generated by the comparator will cause a return from HALT Mode.
STOP Mode
The analog comparator is disabled during STOP Mode. The comparator is powered down to prevent it from drawing any current.
Comparator Definitions
VICR The usable voltage range for the positive input and the reference input is called the common mode voltage range (VICR). The comparator is not guaranteed to work if the input is outside of the VICR range. Voffset The absolute value of the voltage between the positive input and the reference input required to make the comparator output voltage switch is the input offset voltage (Voffset). IIO For the CMOS voltage comparator input, the input offset current (IIO) is the leakage current of the CMOS input gate.
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INPUT PROTECTION
All I/O pins on the Z8E001 have diode input protection. There is a diode from the I/O pad to VCC and to VSS. See Figure 41. However, on the Z8E001, the /RESET pin has only the input protection diode from pad to VSS. See Figure 42.
VCC
PIN
/RESET
PIN
VSS
Figure 42. /RESET Pin Input Protection The high-side input protection diode was removed on this pin to allow the application of high voltage during the OTP programming mode.
VSS
Figure 41. I/O Pin Diode Input Protection
For better noise immunity in applications that are exposed to system EMI, a clamping diode to VCC from this pin may be required to prevent entering the OTP programming mode or to prevent high voltage from damaging this pin.
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PACKAGE INFORMATION
Figure 43. 18-Pin DIP Package Diagram
Figure 44. 18-Pin SOIC Package Diagram
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Figure 45. 20-Pin SSOP Package Diagram
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ORDERING INFORMATION
Standard Temperature 18-Pin DIP Z8E00110PSC 18-Pin SOIC Z8E00110SSC 20-Pin SSOP Z8E00110HSC
Extended Temperature 18-Pin DIP Z8E00110PEC 18-Pin SOIC Z8E00110SEC 20-Pin SSOP Z8E00110HEC
For fast results, contact your local Zilog sales office for assistance in ordering the part(s) desired.
CODES Preferred Package
P = Plastic DIP
Speed
10 = 10 MHz
Longer Lead Time
S = SOIC H = SSOP
Environmental
C = Plastic Standard
Preferred Temperature
S = 0C to +70C E = -40C to +105C
Example: Z 8E001 10 P S C
is a Z86E001, 10 MHz, DIP, 0 to +70C, Plastic Standard Flow Environmental Flow Temperature Package Speed Product Number Zilog Prefix
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Zilog Pre-Characterization Product: The product represented by this CPS is newly introduced and Zilog has not completed the full characterization of the product. The CPS states what Zilog knows about this product at this time, but additional features or nonconformance with some aspects of the CPS may be found, Low Margin: Customer is advised that this product does not meet Zilog's internal guardbanded test policies for the specification requested and is supplied on an exception basis. Customer is cautioned that delivery may be uncertain and that, in addition to all other limitations on
Z8E001 CMOS OTP Microcontroller
either by Zilog or its customers in the course of further application and characterization work. In addition, Zilog cautions that delivery may be uncertain at times, due to start-up yield issues.
Zilog liability stated on the front and back of the acknowledgement, Zilog makes no claim as to quality and reliability under the CPS. The product remains subject to standard warranty for replacement due to defects in materials and workmanship.
(c) 1998 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. ZILOG, INC. MAKES NO WARRANTY, EXPRESS, STATUTORY, IMPLIED OR BY DESCRIPTION, REGARDING THE INFORMATION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE.
Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http://www.zilog.com
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