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| CUSTOMER PROCUREMENT SPECIFICATION Z86127 LOW-COST DIGITAL TELEVISION CONTROLLER (LDTC) GENERAL DESCRIPTION The Z86127 Low-Cost Digital Television Controller (LDTC) introduces a new level of sophistication to single-chip architecture. The Z86127 is a member of the Z8(R) singlechip microcontroller family with 8 Kbytes of ROM and 236 bytes of RAM. The device is housed in a 64-pin DIP package, in which only 52 are active, and are CMOS compatible. The LDTC offers mask programmed ROM which enables the Z8 microcontroller to be used in a high volume production application device embedded with a custom program (customer supplied program). Zilog's LDTC offers fast execution, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, and easy hardware/software system expansion along with low cost and low power consumption. The device provides an ideal performance and reliability solution for consumer and industrial television applications. The Z86127 architecture is characterized by utilizing Zilog's advanced SuperintegrationTM design methodology. The device has an 8-bit internal data path controlled by a Z8 microcontroller and On Screen Display (OSD) logic circuits/ Pulse Width Modulators (PWM). On-chip peripherals include two register mapped I/O ports (Ports 2 and Port 3), interrupt control logic (one software, two external and three internal interrupts) and a standby mode recovery input port (Port 3, pin P30). The OSD control circuits support 8 rows by 20 columns of characters. The character color is specified by row. One of the eight rows is assigned to show two kinds of colors for bar type displays such as volume control. The OSD is capable of displaying either low resolution (5x7 dot pattern) or high resolution (11x15 dot pattern) characters. The Z86C97 currently supports high resolution characters only. A 14-bit PWM port provides enough voltage resolution for a voltage synthesizer tuning system. Three 6-bit PWM ports are used for controlling audio signal levels. Five 8-bit PWM ports are used to vary picture levels. The LDTC applications demand powerful I/O capabilities. The Z86127 fulfills this with 27 I/O pins dedicated to input and output. These lines are grouped into four ports, and are configurable under software control to provide timing, status signals, parallel I/O and an address/data bus for interfacing to external memory. There are three basic address spaces available to support this wide range of configurations: Program Memory, Video RAM, and Register File. The Register File is composed of 236 bytes of general purpose registers, two I/O Port registers, 15 control and status registers and three reserved registers. To unburden the program from coping with the real-time problems such as counting/timing and data communication, the LDTC offers two on-chip counter/timers with a large number of user selectable modes (Functional Block Diagram). Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD VSS DC-4063-00 (10-16-91) 1 GENERAL DESCRIPTION (Continued) XTAL1 XTAL2 /RESET RESET Oscillator WDT Counter Timer Counter Timer P30 P31 P34 P35 P36 P50( P00 ) P51( P01 ) P52( P02 ) P53( P03 ) P54( P04 ) P55( P05 ) P56( P06 ) P57( P07 ) P60( /AS ) P61( /DS ) P62( R//W ) P63( SCLK ) P64( P66 )* P65( P67 )* AFCIN Port 3/ Interrupt 256 Byte Register File PWM 1 14 -bit PWM 1 8 KByte Program ROM Port 2 Z8 CPU Core P27 P26 P25 P24 P23 P22 P21 P20 Port 5 (Port 0) Port 0 A8:15 Port 1 AD0:7 PWM 6 to PWM 8 6-bit Port 6 (Control) PWM 9 to PWM 13 8-bit PWM 6 PWM 7 PWM 8 PWM 9 PWM 10 PWM 11 PWM 12 PWM 13 160 Byte Character RAM On Screen Display 4 KByte Character ROM OSCIN OSCOUT HSYNC VSYNC VRED VGREEN VBLUE VBLANK Functional Block Diagram 2 PIN CONFIGURATION N/C N/C N/C N/C PWM1 P35 P36 P34 P31 P30 XTAL1 XTAL2 /RESET P60 GND P61 P62 VCC P63 P64 P65 AFCIN P50 P51 P52 P53 P54 P55 P56 P57 OSCIN OSCOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PWM6 PWM7 PWM8 PWM9 PWM10 PWM11 PWM12 PWM13 P27 P26 P25 P24 P23 GND P22 P21 VCC P20 N/C N/C N/C N/C N/C N/C N/C N/C VBLANK VBLUE VGREEN VRED VSYNC HSYNC Z86127 (LDTC) 64-Pin Mask-ROM Plastic DIP 3 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational Symbol VCC VI VI VO IOH IOH IOL IOL IOL TA TSTG Parameters Power Supply Voltage* Input Voltage Input Voltage Output Voltage Output Current High Output Current High Output Current Low Output Current Low Output Current Low Operating Temperature Storage Temperature sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Min -0.3 -0.3 -0.3 -0.3 Max +7 VCC+0.3 VCC+0.3 VCC+8.0 -10 -100 20 40 200 Units V V V V mA mA mA mA mA C Notes [1] [2] 1 pin All total 1 pin [3] (1 pin) All total -65 +150 Notes: [1] Port 2 open drain [2] PWM open-drain outputs [3] Port 5 * Voltage on all pins with respect to GND. See Ordering Information STANDARD TEST CONDITIONS The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Test Load Diagram). From Output Under Test VDD RLL 150 pF RLH Test Load Diagram CAPACITANCE TA=25C; VCC=GND=0V; Freq=1.0 MHz; unmeasured pins to GND. Parameter Input capacitance Output capacitance I/O capacitance AFCIN input capacitance Max 10 20 25 10 Units pF pF pF pF 4 DC CHARACTERISTICS TA=0C to +70C; VCC=+4.5V to +5.5V; FOSC=4 MHz Sym VIL VILC VIH VIHC VHY VPU VOL Parameter Input Voltage Low Input XTAL/Osc In Low Input Voltage XTAL/Osc In High Input XTAL/Osc in High Schmitt Hysteresis Maximum Pull-up Voltage Output Voltage Low TA=0C to +70C Min Max 0 0.7 VCC 0.8 VCC 0.1 VCC 0.2 VCC 0.07 VCC VCC VCC 12 0.4 0.4 0.4 1.5 0.5 VCC VCC-0.4 -3.0 -3.0 0.45 VCC 0.75 VCC -80 3.0 3.0 20 6 10 0.16 0.19 0.19 1.00 1.9 3.12 4.75 -46 0.01 0.02 13.2 3.2 0 Typical Units @ 25C 1.48 0.98 3.2 3.0 0.8 V V V V V V V V V V V V V A A A mA mA A Conditions External Clock Generator Driven External Clock Generator Driven External Clock Generator Driven [2] IOL=1.00mA IOL=3.2mA, [1] IOL=0.75mA [2] IOL=10mA [1] V00-01 V01-11 VOH IIR IIL IOL ICC ICC1 ICC2 AFC Level 01 In AFC Level 11 In Output Voltage High Reset Input Current Input Leakage Tri-State Leakage Supply Current IOH=-0.75mA VRL=0V 0V,VCC 0V,VCC All inputs at rail All inputs at rail All inputs at rail Notes: [1] Port 5 [2] PWM open drain 5 AC CHARACTERISTICS Timing Diagrams 1 3 XTAL1 3 2 2 External Clock 7 5 Tin 4 6 Counter Timer IRQn 8 9 Interrupt Request 6 Vcc 10 11 Internal /RESET 12 External /RESET Power On Reset HSYNC 13 14 OSC2 On Screen Display 7 AC CHARACTERISTICS TA=0 C to +70 C; VCC=+4.5V to +5.5V; FOSC=4 MHz, No 1 2 3 4 5 6 7 8a 8b 9 10 11 12 13 14 15 Symbol TpC TrC,TfC TwC TwTinL TwTinH TpTin TrTin,TfTin TwIL TwIL TwIH TdPOR TdLVIRES TwRES TdHsOI TdHsOh TdWDT Parameter Input Clock Period Clock Input Rise and Fall Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period Timer Input Rise and Fall Int Req Input Low Int Request Input High Power On Reset Delay Low Voltage Detect to Internal RESET Condition Reset Minimum Width Hsync Start to Vosc Stop Hsync End to Vosc Start WDT Refresh Time Min 250 70 70 3TpC 8TpC 100 70 3TpC 3TpC 25 200 5TpC 2TpV ns ns Max 1000 15 Unit ns ns ns ns 100 ms ns 3TpV 1TpV 12 ms Note: Refer to DC Characteristics for details on switching levels. (c) 1991 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of mer- chantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 171-980 A/B ZILOG CPTO FAX 408 370-8056/8027 8 |
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