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DATA SHEET
MOS INTEGRATED CIRCUIT
PD16857
MONOLITHIC 6 channel H-BRIDGE DRIVER
DESCRIPTION
PD16857 is monolithic 6 channel H-bridge driver employing power MOS FETs in the output stages. The MOS
FETs in the output stage lower the saturation voltage and power consumption as compared with conventional drivers using bipolar transistors. In addition, a low-voltage malfunction prevention circuit is also provided that prevents the IC from malfunctioning when the supply voltage drops. A 30-pin plastic shrink SOP package is adopted to help create compact and slim application sets. In the output stage H bridge circuits, two low-ON resistance H-bridge circuits for driving actuators, and another three channels for driving sled motors and tilt control, and another channel for driving loading motor are provided, making the product ideal for applications in DVD-ROM/DVD-RAM.
FEATURES
* Six H-bridge outputs employing power MOS FETs. * High speed PWM drive corresponding: Operating input frequency 120 kHz (MAX.) * Low voltage malfunction prevention circuit: Operating control block voltage under 2.5 V (TYP.) * Loading into 38-pin shrink SOP (300 mil).
ABSOLUTE MAXIMUM RATINGS (TA = 25 C)
Parameter Control block supply voltage Output block supply voltage Input voltage Output current Power consumptionNote Peak junction temperature Storage temperature range Symbol VDD VM VIN ID(pulse) PT TCH(MAX) Tstg PW 5 ms, Duty 20 % Condition Rating -0.5 to +6.0 -0.5 to +13.5 -0.5 to VDD+0.5 1.0 1.0 150 -55 to +150 Unit V V V A/ch W C C
Note
When mounted on a glass epoxy board (10 cm x 10 cm x 1 mm, 15 % copper foil)
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S13908EJ1V0DS00 (1st edition) Date Published July 1999 N CP(K) Printed in Japan
(c)
1999
PD16857
RECOMMENDED OPERATING CONDITIONS
Parameter Control block supply voltage Output block supply voltage Output current (pulse) Operating frequency Operating temperature range Peak junction temperature Symbol VDDNote VM ID(pulse) fIN TA TCH(MAX) 0 PW < 5 ms, Duty < 10 % Condition MIN. 3.0 10.8 -0.6 TYP. 3.3 12 MAX. 3.6 13.2 0.6 120 75 125 Unit V V A kHz C C
Note
The low-voltage malfunction prevention circuit (UVLO) operates when VDD is 2.1 V TYP.
CHARACTERISTICS TA = 25 C and the other parameters are within their recommended operating ranges as described above
unless otherwise specified. The parameters other than changes in delay time are when the current is ON.
Parameter VM pin current (OFF state) VDD pin current High level input current Low level input current High level input voltage Low level input voltage H-bridge ON resistance (ch1, 3, 5, 6) H-bridge ON resistance (ch2, 4) H-bridge switching current without load (ch1, 3, 5, 6)Note H-bridge switching current without load (ch2, 4)Note
Symbol IM IDD IIH IIL VIH VIL RONa VM = 13.2 V VDD = 3.6 V VIN = VDD
Condition
MIN.
TYP.
MAX. 50 200 0.15
Unit
A A
mA
VIN = 0, IN and SEL pins VDD = 3.3 V, VM = 12 V IN and SEL pins
-2.0 0.7VDD -0.3 2.5 VDD 0.3VDD 3.5
A
V V mA
VDD = 3.3 V, VM = 12 V RONb upper + lower 1.5 2.0
Isa(AVE) VDD = 3.3 V, VM = 12 V Isb(AVE) 100 kHz switching
3.0
4.5
mA
Note
Average value of the current consumed internally by an H-bridge circuit when the circuit is switched without load.
2
Data Sheet S13908EJ1V0DS00
PD16857
CHARACTERISTICS TA = 25 C and the other parameters are within their recommended operating ranges as described above
unless otherwise specified. The parameters other than changes in delay time are when the current is ON.
Parameter Symbol (ch1, 3, 5 Rise time Rising delay time Change in rising delay time Fall time Falling delay time Change in falling delay time tTLHa tPLHa VDD = 3.3 V VM = 12 V RL(load) = 20 100 kHz switching Condition 1A, 1B, 3A, 3B, 5A, 5B output) 200 350 110 200 350 130 (ch1, 3, 5 Rising delay time differential Falling delay time differential tPLHa(A-B) tPHLa(A-B) 1A-1B, 3A-3B, 5A-5B) 50 50 ns ns ns ns ns ns ns ns MIN. TYP. MAX. Unit
tPLHa
tTHLa tPHLa
tPHLa
VDD = 3.3 V, VM = 12 V RL = 20 , 100 kHz SW (ch2, 4 2A, 2B, 4A, 4B output)
Rise time Rising delay time Change in rising delay time Fall time Falling delay time Change in falling delay time
tTLHb tPLHb VDD = 3.3 V VM = 12 V RL(load) = 10 100 kHz switching
200 350 110 200 350 130 (ch2, 4 2A-2B, 4A-4B) 50 50
ns ns ns ns ns ns
tPLHb
tTHLb tPHLb
tPHLb
Rising delay time differential Falling delay time differential
tPLHb(A-B) tPHLb(A-B)
VDD = 3.3 V, VM = 12 V RL = 10 , 100 kHz SW (ch6 6A, 6A output) 100
ns ns
Rise time Rising delay time Fall time Falling delay time
tTLHC tPLHC tTHLC tPHLC
VDD = 3.3 V VM = 12 V RL(load) = 20 100 kHz switching
ns 1.0
s
ns
100 1.0
s
Data Sheet S13908EJ1V0DS00
3
PD16857
PIN CONNECTION
ch1
ch2
ch5 ch6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
VDD IN1A IN1B IN2A IN2B 1A GND 1B VM 2A GND 2B VM 5A GND 6A VMLD IN5A IN5B
IN3B IN3A IN4B IN4A VM 3B GND 3A VM 4B GND 4A VM 5B GND 6B IN6B IN6A SEL
38 37 36 35 34 33 32 31 30 29 28 2B 26 25 24 23 22 21 20
ch3
ch4
Pin No. Pin name 1 VDD
Pin function Control block supply voltage pin (3.3 V input) ch1 input pin ch1 input pin ch2 input pin ch2 input pin ch1 output pin Ground pin ch1 output pin Output block supply voltage pin (12 V input) ch2 output pin Ground pin ch2 output pin Output block supply voltage pin (12 V input) ch5 output pin Ground pin ch6 output pin Output block supply voltage pin (12 V input) ch5 input pin ch5 input pin
Pin No. Pin name 20 SEL
Pin function Output enable pin
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
IN1A IN1B IN2A IN2B 1A GND 1B VM 2A GND 2B VM 5A GND 6A VMLD IN5A IN5A
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
IN6A IN6B 6B GND 5B VM 4A GND 4B VM 3A GND 3B VM IN4A IN4B IN3A IN3B
ch6 input pin ch6 input pin ch6 output pin Ground pin ch5 output pin Output block supply voltage pin (12 V input) ch4 output pin Ground pin ch4 output pin Output block supply voltage pin (12 V input) ch3 output pin Ground pin ch3 output pin Output block supply voltage pin (12 V input) ch4 input pin ch4 input pin ch3 input pin ch3 input pin
4
Data Sheet S13908EJ1V0DS00
PD16857
BLOCK DIAGRAM
IN1B 3
IN1A 2
VDD 1
IN3B 38
IN3A 37
IN4B 36
4
IN2A
ch2 Control
ch1 Control
LVP
ch3 Control
ch4 Control
IN4A
35
level shift
level shift
level shift
level shift
5
IN2B 1A H Bridge (ch1)
Predriver Predriver
VM 3B H Bridge (ch3)
34
6
Predriver
Predriver
33
7
GND
GND
32
8
1B
3A
31
9
VM
VM
30
10
2A H Bridge (ch2)
Predriver Predriver
4B H Bridge (ch4)
29
11
GND
GND
28
12
2B
Predriver
Predriver
4A
27
13 14
VM
VM
26 25
5A
H Bridge (ch5)
Predriver
Predriver
H Bridge (ch5)
5B
15
GND 6A
GND 6B
24
H Bridge (ch6)
Predriver
Predriver
H Bridge (ch6)
16
ch5 Control
level shift
level shift
ch6 Control
23
17 VMLD
18 IN5A
19 IN5B
SEL
20 SEL
21 IN6A
22 IN6B
Remark Plural terminal (VM, VMLD, GND) is not only 1 terminal and connect all terminals.
Data Sheet S13908EJ1V0DS00
5
PD16857
FUNCTION TABLE
VM, VMLD VDD (COMMON)
IN1A - IN6A 1A - 6A(OUTA) IN1B - IN6B SEL 1B - 6B(OUTB)
GND (COMMON) PGND
INPUT IN1A - IN6A L L H H X IN1A - IN6A L H L H X SEL H H H H L
OUTPUT 1A - 6A L L H H Z 1B - 6B L H L H Z
X: Don't care
Z: High impedance
6
Data Sheet S13908EJ1V0DS00
PD16857
TYPICAL CHARACTERISTICS
PT vs. TA characteristics 50 TA=25C VM=12V Total power dissipation PT (W) 1.0 125C/W VDD pin current IDD ( A) 40 IDD vs. VDD characteristics
30
0.5
20
10
0
25
50
75
100
125
150
0
3.0
3.3
3.6
Ambient temperature TA (C)
Control block supply voltage VDD (V)
VIH vs. VIL-VDD characteristics 3.0 H-bridge ON resistance RONa, RONb () TA=25C VM=12V High level input voltage VIH (V) Low level input voltage VIL (V) 3.0
RON vs. VM characteristics TA=25C VDD=3.3V RONa(ch6) RONa(ch1. 3. 5) 2.0
VIH , VIL 1.5
RONb(ch2. 4) 1.0
1.0 3.0 3.3 3.6 Control block supply voltage VDD (V) Isa, Isb. vs. VDD characteristics Switching current without load Isa, Isb (mA) 3.0 TA=25C VM : 10.8V 12V 13.2V VDD : 3.0V 3.3V 3.6V VDD pin current IDD ( A) Isb(ch2. 4) 2.0
10
11
12
13
14
Output block supply voltage VM (V) IDD vs. TA characteristics 100 VDD=3.6V 80
60
40
1.0
Isa(ch1. 3. 5)
20 Isa(ch6) 0 10 11 12 13 14 0 20 40 60 80
Output block supply voltage VM (V)
Data Sheet S13908EJ1V0DS00
Ambient temperature TA (C)
7
PD16857
RON vs. TA characteristics 250 VM=12V
H-bridge ON resistance RONa, RONb ()
tTLHa, tTLHb, tTLHc, vs. TA characteristics VDD=3.3V VM=12V
Rise time tTLHa, tTLHb, tTLHc (ns)
3.0 RONa(ch6) 2.5 200
RONa(ch1. 3. 5)
150
tTLHc
2.0
100
tTLHb tTLHa
1.5 RONb(ch2. 4) 1.0 0 20 40 60 80
50
0
20
40
60
80
Ambient temperature TA (C)
Ambient temperature TA (C)
tTHLa, tTHLb, tTHLc vs. TA characteristics 250
Rising delay time tPLHa, tPLHb, tPLHc (ns)
tPLHa, tPLHb, tPLHc, vs. TA characteristics VDD=3.3V VM=12V
VDD=3.3V VM=12V
Fall time tTHLa, tTHLb, tTHLc (ns)
600
200
500 tPLHc 400
150 tTHLa 100 tTHLc 50 tTHLb
300 tPLHb tPLHa 200 0 20 40 60 80
0
20
40
60
80
Ambient temperature TA (C)
Ambient temperature TA (C)
tPHLa, tPHLb, tPHLc vs. TA characteristics
tPLHb (ns)
tPLHa, 100
tPLHb, vs. TA characteristics VDD=3.3V VM=12V
350
Falling delay time tPHLa, tPHLb, tPHLc (ns)
VDD=3.3V VM=12V 300 tPHLa tPHLb 250 tPHLc 200
80 tPLHb 60 tPLHa 40
Change in rising delay time
tPLHa,
150
20
100
0
20
40
60
80
0
20
40
60
80
Ambient temperature TA (C)
Ambient temperature TA (C)
8
Data Sheet S13908EJ1V0DS00
PD16857
tPHLa,
tPHLb (ns)
tPHLc, vs. TA characteristics
Rising delay time differential tPLHa(A-B), tPLHb(A-B) (ns)
tPLHa(A-B), tPLHb(A-B), vs. TA characteristics 25 VDD=3.3V VM=12V 20
120 VDD=3.3V VM=12V 100
tPHLa,
Change in falling delay time
80 tPHLa tPHLb 60
15
10
40
5 tPLHa(A-B) 0 20 40
tPLHb(A-B)
20
0
20
40
60
80
60
80
Ambient temperature TA (C)
Ambient temperature TA (C)
tPHLa(A-B), tPHLb(A-B), vs. TA characteristics
Falling delay time differential tPHLa(A-B), tPHLb(A-B) (ns)
25 VDD=3.3V VM=12V 20
15
10
5
tPHLa(A-B) tPHLb(A-B)
0
20
40
60
80
Ambient temperature TA (C)
Data Sheet S13908EJ1V0DS00
9
PD16857
ABOUT SWITCHING OPERATION
VM
When output A is switched as shown in the figure on the right, a dead time (time during which both Pch and Nch are off) elapses to prevent through current. Therefore, the waveform of output A (rise time, fall time, and delay time) changes depending on whether output B is fixed to the high or low level. The output voltage waveforms of A in response to an input waveform where output B is fixed to the low level (1) or high level (2) are shown below.
Nch Nch A B Pch Pch
(1) Output B: Fixed to low level Output A: Switching operation (Operations of Pch switch and Nch switch are shown.)
Dead time Input waveform
Pch : OFF OFF ON Nch : ON OFF OFF
ON OFF
OFF OFF OFF ON
Voltage waveform at point A Current ON
Current OFF
Output A goes into high-impedance state and is in an undefined status during the dead time period. But, because output B is pulled down by the load, a low level is output to A. (2) Output B: Fixed to high level Output A: Switching operation (Operations of Pch switch and Nch switch are shown.)
Dead time Input waveform
Pch : OFF OFF ON Nch : ON OFF OFF
ON OFF
OFF OFF OFF ON
Voltage waveform at point A Current OFF
Current ON
Output A goes into high-impedance state and is in an undefined status during the dead time period. But, because output B is pulled up by the load, a high level is output to A.
10
Data Sheet S13908EJ1V0DS00
PD16857
The switching characteristics shown on the preceding pages are specified as follow ("output at one side" means output B for H-bridge output A, or output A for output B). [Rise time] Rise time when the output at one side is fixed to the low level (specified on current ON). [Fall time] Fall time when the output at one side is fixed to the high level (specified on current ON). [Rising delay time] Rising delay time when the output at one side is fixed to the low level (specified on current ON). [Falling delay time] Falling delay time when the output at one side is fixed to the high level (specified on current ON). [Change in rising delay time] Change (difference) in the rising delay time between when the output at one side is fixed to the low level and when the output at the other side is fixed to the high level. [Change in falling delay time] Change (difference) in the falling delay time between when the output at one side is fixed to the low level and when the output at the other side is fixed to the high level. [Rising delay time differential] Difference in rising delay time between output A and output B. [Falling delay time differential] Difference in falling delay time between output A and output B. Caution Because this LSI switches a high current at high speeds, surge may occur due to the VM and GND wiring and inductance and degrade the performance of the LSI. On the PWB, keep the pattern width of the VM and GND lines as wide and short as possible, and insert the bypass capacitors between VM and GND at location as close to the LSI as possible. Connect a low inductance magnetic capacitor (4700 pF or more) and an electrolytic capacitor of 10 F or so, depending on the load current, in parallel.
Data Sheet S13908EJ1V0DS00
11
PD16857
PACKAGE DIMENSION
38-PIN PLASTIC SSOP (300 mil)
38 20 detail of lead end F G
1 A
19 E
P
L
H I S J
C D M
M
N
S
B K
NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D E F G H I J K L M N P
MILLIMETERS 12.70.3 0.65 MAX. 0.65 (T.P.) 0.37+0.05 -0.1 0.1250.075 1.6750.125 1.55 7.70.2 5.60.2 1.050.2 0.2 +0.1 -0.05 0.60.2 0.10 0.10 3+7 -3 P38GS-65-BGG
12
Data Sheet S13908EJ1V0DS00
PD16857
RECOMMENDED SOLDERING CONDITIONS
Solder this product under the following recommended conditions. For details of the recommended soldering conditions, refer to information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended, consult NEC.
Recommended Condition symbol
Soldering Method
Soldering Conditions Package peak temperature: 235 C; Time: 30 secs. max. (210 C min.); Number of times: 3 times max.; Number of day: none; Flux: Rosin-based flux with little chlorine content (chlorine: 0.2 Wt% max.) is recommended Package peak temperature: 215 C; Time: 40 secs. max. (200 C min.); Number of times: 3 times max.; Number of day: none; Flux: Rosin-based flux with little chlorine content (chlorine: 0.2 Wt% max.) is recommended. Package peak temperature: 260 C; Time: 10 secs. max.; Number of times: once; Flux: Rosin-based flux with little chlorine content (chlorine: 0.2 Wt% max.) is recommended.
Infrared reflow
IR35-00-3
VPS
VP15-00-3
Wave soldering
WS60-00-1
Caution Do not use two or more soldering methods in combination.
Data Sheet S13908EJ1V0DS00
13
PD16857
[MEMO]
14
Data Sheet S13908EJ1V0DS00
PD16857
[MEMO]
Data Sheet S13908EJ1V0DS00
15
PD16857
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98.8

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