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Fibre Channel Transmitter and Receiver Chipset Technical Data
HDMP-1512 Transmitter HDMP-1514 Receiver
Features
* ANSI X3.230-1994 Fibre Channel Standard Compatible (FC-0) * Selectable 531.25 Mbaud or 1062.5 Mbaud Data Rates * Selectable On Chip Laser Driver and 50 Cable Driver * TTL Compatible I/Os * Single +5.0 V Power Supply
Applications
* Mass Storage System I/O Channel * Work Station/Server I/O Channel * High Speed Peripheral Interface
converts the data to a serial stream and sends it over a copper cable or fiber-optic link. The receiver converts the serial data stream back to parallel encoded data and presents it, along with the recovered transmit byte clock, to the receiving system. The sending system has the option to electrically wrap the transmitted data back to the local receiver. It is possible to transmit over the cable driver, or laser driver when data is being wrapped back to the local receiver. The two-chip set (transmitter chip and receiver chip) is compatible with the FC-0 layer of the American National Standards Institute (ANSI), Fibre Channel specification, X3.230-1994. This specification defines four standard rates of operation for Fibre Channel links. The HDMP1512 and HDMP-1514 chip-set will operate at the two highest defined serial rates of 531.25 Mbaud and 1062.5 Mbaud. These serial baud rates correspond to 8B/10B encoded byte rates of 50 Mbytes/sec and 100 Mbytes/sec respectively. The proper setting of a single pin on each chip selects the desired rate of operation.
Description
The HDMP-1512 transmitter and the HDMP-1514 receiver are bipolar integrated circuits, separately packaged, in 80 pin MQuad packages. They are used to build a high speed Fibre Channel link for point to point data communications. Shown in Figure 1 is a typical full duplex point-topoint Fibre Channel link. The sending system provides parallel, 8B/10B, encoded data and a transmit byte clock to the HDMP1512 transmitter. Using the transmit byte clock, the transmitter
Several features, exclusive to this chip-set, make it ideal for use in Fibre Channel links. In addition, the laser driver on the transmitter chip, the dual loss of light detectors on the receiver chip, and the power supervisor and power reset features make this chip-set ideal for use with laser optics. The serial cable driver (transmitter chip), and the cable equalizer (on the receiver chip), can be operated in conjunction with, or as an alternative to, the laser driver. The laser driver can also be driven directly with an external high speed serial input. Altogether, the various features, input/output options, and flexibility of this chip-set make several unique link configurations possible. In particular, it is ideally suited for use in applications where conformance to the FCSI specification # 301-Rev 1.0, Gbaud Link Module Specification, is desired.
656
5964-6637E (4/96)
REF CLOCK
CLOCK Tx ENCODED DATA
CLOCK SERIAL LINK Rx ENCODED DATA
ENCODED DATA Rx CLOCK SERIAL LINK Tx
ENCODED DATA CLOCK
REF CLOCK
Figure 1. Point-to-Point Data Link.
-COMGEN
EWRAP
TS2
TS1
SI
DATA BYTE 0 Tx [00:09] DATA BYTE 1 Tx [10:19]
10 TTL INTERFACE AND INPUT LATCH 10 20 FRAME MULTIPLEXER I/O SELECT CABLE DRIVERS
2
LOUT
2
SO
2 TBC PLL/CLOCK GENERATOR INTERNAL CLOCKS LASER DRIVER
LZOUT LASER CONTROLS
-LZON
PPSEL
Figure 2. HDMP-1512 (Tx) Block Diagram.
Transmitter Operation
The block diagram of the HDMP1512 transmitter is shown in Figure 2. The basic functions of the transmitter chip are the TTL Interface and Input Latch, Frame Multiplexing, Input/Output selection, cable drivers, Laser Driver, and monolithic Phase Locked loop clock generator. The actual operation of each function changes slightly, according to the desired configuration and option settings. Figures 18 and 19 show schematically how to terminate each pin on the HDMP-1512 when used in systems incorporating either copper or fiber media.
There are two main modes of operation for the transmitter chip, both are based on the selected baud rate. The baud rate is controlled by the appropriate setting of the SPDSEL pin, #67. When this pin is set low, the transmitter operates at a serial rate of 531.25 Mbaud. When pin #67 is set high the transmitter operates at a serial rate of 1062.5 Mbaud. As such, the two main modes of operation are the 531.25 Mbaud mode and the 1062.5 Mbaud mode. The transmitter does not encode the applied data. It assumes the
SPDSEL
data is pre-encoded using the 8B/10B encoding scheme as defined in ANSI X3.230-1994. The TTL input interface receives data at the standard TTL levels specified in the dc Electrical Specification table. The internal phase locked loop (PLL) locks to the transmit byte clock, TBC. TBC is supplied to the transmitter chip by the sending system. TBC should be a 53.125 MHz clock ( 100 ppm) as defined in X3.230-1994. Once the PLL has locked to TBC, all the clocks used by the transmitter are generated by the internal clock generator.
FAULT
657
When operating in the 531.25 Mbaud mode, data byte 0, Tx[00:09], is active and is clocked into the input latch a single byte (10 bits) on each rising edge of TBC. In the 1062.5 Mbaud mode both data byte 0, Tx[00:09], and data byte 1, Tx[10:19], are active. In 1062.5 Mbaud mode, data byte 0 and data byte 1 are clocked into the transmitter on the rising edge of every clock cycle, (TBC). There is one minor variation possible in the 1062.5 Mbaud mode, referred to as "ping-pong" mode. Pingpong mode is selected by setting the PPSEL pin (#34) high. In this mode the transmitter clocks data into the input latch one byte per half clock cycle. Data byte 0 is transmitted on the rising edge of TBC and data byte 1 is transmitted 1/2 clock cycle later. See Figure 16 for timing information. The input latch will stop sending the data applied to the Tx[00:09] data pins when a low is applied to the -COMGEN pin (#32) and will send the pre-set special Fibre Channel character, K28.5 instead. The 8B/10B coding scheme, adopted by Fibre Channel, converts 8 bit data words into 10 bit representations of the actual data. Of all the possible combina-
tions of 10 bit binary words, the 8B/10B code reserves 256 of them to represent the valid combinations of 8 bit data. Some of the remaining combinations are reserved for special functions. The character reserved for defining the transmitted word boundary has been defined as the K28.5 character, also known as a comma character. The receiver will automatically reset registers and clock when it receives a comma character (this will be discussed in more detail in the receiver operation section). Every valid 8 bit data word is actually represented by one of two 10 bit codes, indicating either positive or negative running disparity. The input latch only generates the K28.5 character with positive disparity (0011111010). In Figure 2, the Frame Multiplexer utilizes shift registers and a multi-stage multiplexing scheme to convert the 10 or 20 parallel data bits to a serial data stream. This serial data stream is then fed directly into the Input/ Output Select portion of the transmitter. The I/O Select function allows use of both the internally serialized Fibre Channel data stream and an
externally supplied Fibre Channel data stream denoted as SI (pins 11 and 12). By using the proper settings of TS1, TS2, and EWRAP (pins 76, 75, and 71 respectively), the internal data stream and the external data stream can be directed to various combinations of the cable driver output, the laser driver output, and the electrical loopback output. The possible I/O combinations are listed in the Input Output Select Table and the functionality is described in more detail in the Transmitter Laser Driver Operation section below. The cable driver function provides a 50 differential cable driver output at pins 5 and 6 ( SO). The simplified circuit is the O-BLL section shown in Figure 10. A similar output is provided to allow electrical loopback, or wrap of the local data back to the local receiver for diagnostics. This is denoted as LOUT on pin 8 and pin 9. The final function on the transmitter chip is the Laser Driver block which provides a high speed differential output, LZOUT, at pins 19 and 20. There are several other laser control I/Os which will be
HDMP-1512 Input Output Select Table
Mode 0 1 2 3 4 5 6 7 658 TS1 0 0 0 0 1 1 1 1 TS2 0 0 1 1 0 0 1 1 EWRAP 0 1 0 1 0 1 0 1 Data Source For: SO LZOUT LOUT NA Internal NA NA NA Internal Internal Internal NA Internal NA Internal Internal NA NA NA Internal Internal Internal SI NA Internal NA SI Active Outputs SO LZOUT LOUT no yes no no no yes yes yes no yes no yes yes no no no yes yes yes yes no yes no yes
INTERNAL INPUT SELECT DATA STREAM
Tx CHIP BOUNDARY VCC_LZAC
17
5 0.1 F
VCC 0.1 F
SI VCC_LZ1 VCC_LZ GND_LZ
11 12 16 23 24 25 26
+ MUX AC AMP -
+LZOUT
19 20
-LZOUT LZCSE
25 TRANSMISSION LINE
14
AC AMP DISABLE
POT 2 50 5
0.1 F 25
-LZON LZPWRON
30
LASER ON
36
LZDC WINDOW DETECTOR - DC OP-AMP + 10 nF 10 nF
21
VCC 0.1 F P2 0.1 F 301 2.2 P1 ( >= 100)
EXTERNAL CONTROL
FAULT
29
ERROR DETECTOR BANDGAP REFERENCE
8 25
0.1 F
BANDGAP DETECTOR
15 27 28 22
VCC-LZBG
LZTC 0.1 F
LZBTP
LZMDF
POT 1 5 K
Figure 3. Laser Driver Block Diagram and External Circuitry.
described in more detail in the laser driver operation section below.
Transmitter Laser Driver Operation
The block diagram of the HDMP1512, Tx, laser driver circuitry is shown in Figure 3. The laser driver is enabled by setting -LZON (pin 30) low and LZPWRON (pin 36) high. The circuitry in Figure 3, shown outside the chip boundary (dotted box), illustrates the external components required to complete a typical laser driver connection. The input data source to the laser driver is user selected from either the internally generated data stream, or an externally supplied high speed data stream. The externally supplied data stream is applied to the high speed input
SI pins. The user selects between these two data sources through the proper settings of pins TS1, TS2, and EWRAP (pins 76, 75, and 71). The possible combinations of active inputs and outputs are shown in the Input/ Output Select Table. The chosen high speed input is then modulated onto the laser by the ac amplifier. The external potentiometer, Pot 2, shown connected to pin LZCSE (# 14) is used to adjust the laser modulation depth. The laser driver output is at pins 19 and 20, LZOUT. Laser diode dc bias control is provided through the LZDC (# 21) pin. Adjustment of Pot 1 sets the nominal dc bias desired for the laser diode. The equivalent output circuit of LZDC is shown in Figure 4. Laser diode fault and safety control is implemented through the combination
VCC_LZ
54
400
LZDC
Figure 4. LZDC Equivalent Output Circuit (Tx pin # 21).
of the window detector, error detector, Laser On pin # 30 (-LZON), laser monitor diode feedback pin # 22 (LZMDF), and the op-amp dc bias control circuit. The window detector monitors the voltage on pin LZMDF. If this voltage goes out of range by more than 10% from the nominal setting, the 659
capacitor on pin LZTC (# 27) will begin to discharge. After approximately 2 msec, the voltage on LZTC falls to the fault value and the error detector will bring the FAULT pin (# 29) high to alert the system. The error detector will also hold the voltage on LZMDF low, until a reset is initiated. The -LZON pin is used to disable the laser driver under system control or in conjunction with an external open-fiber control (OFC) chip. This pin is also used to reset the error detector and recharge the capacitor on pin LZTC. The LZPWRON pin, # 36, is used to hold off dc power to the laser driver until proper dc bias is applied to the laser diode. When LZPWRON goes high, the laser driver is enabled, when it is low, it is disabled. If not used, this pin should be tied low.
Receiver Operation
The block diagram of the HDMP1514 receiver is shown in Figure 5. The functions included on the receiver are a coaxial cable equalizer, two independent loss of light (LOL) detectors, an input select function, monolithic phase locked loop and clock recovery circuits, a clock generator, frame demultiplexer and comma detector, power supply supervisor, and output latch with TTL drivers. Figures 20 and 21 show schematically how to terminate each pin on the HDMP-1514 when used in systems incorporating either copper or fiber media. In the most basic sense, the receiver accepts a serial electrical data stream at 1062.5 Mbaud or 531.25 Mbaud and recovers the 8B/10B encoded parallel data and clock that was applied to the transmitter. Like the transmitter, the receiver has several configuration options which interrelate
-TCLKSEL -LCK_REF L_UNUSE SPDSEL EWRAP
according to the desired mode of operation. The two main modes of operation for the receiver are based on the desired signalling rate. The signalling rate is controlled by the proper setting of the SPDSEL pin # 71. When this pin is set low, the receiver operates at a serial rate of 531.25 Mbaud. When pin # 71 is set high, the receiver operates at a serial rate of 1062.5 Mbaud. In a typical configuration, the serial electrical data stream will be applied to the DI pins, # 19 and # 20 on the receiver. The serial electrical data stream may have been transmitted over a fiber optic link or a copper cable link (several variations of each link type is possible). For use with copper links, a selectable cable equalizer is available at the input. This equalizer can be switched into or out of the data
DR_REF
LOL DETECTORS
CLKIN
LOLA
LOLB
DI
CABLE EQUALIZER
INPUT SELECT
PLL AND CLOCK SELECT
RBC0 CLOCK GENERATOR INTERNAL CLOCKS RBC1
-EQEN LIN COM_DET
VCC_HS
SUPPLY SUPERVISOR
FRAME DEMUX AND COMMA DETECT
20
OUTPUT LATCH AND TTL INTERFACE
10
DATA BYTE 0 Rx [00:09] DATA BYTE 1 Rx [10:19]
10
PS_CT
-POR
Figure 5. HDMP-1514 (Receiver) Block Diagram.
660
EN_CDET
PPSEL
path using the -EQEN pin, # 32. Setting pin #32 high disables the equalizer. Setting pin # 32 low enables the equalizer. The typical performance of the input equalizer is shown in the (frequency response) plot of Figure 7. The impact of the equalizer is improved BER performance over long lengths of cable (10 to 20 meters). Connected to the DI input pins, prior to the equalizer, are the loss of light detectors, LOLA (pin 28) and LOLB (pin 29). Actually, since these detectors monitor the incoming serial electrical data stream, they can be thought of as loss of "signal" detectors. These signals can be used to determine if the incoming signal line is connected properly. In the case of a fiber optic system they can be used to shut down laser output power for laser safety considerations. The LOL detectors measure transitions in the incoming data stream that exceed a pre-set peak-to-peak differential signal or threshold level. The default peakto-peak differential threshold voltage is 25 mV and can be adjusted by connecting a resistive divider to the DR_REF pin (#21) as shown in Figure 6. The rela-
tionship of the DR_REF voltage to the peak-to-peak differential threshold voltage is shown in Figure 8. When the input signal level falls below the threshold voltage for 4 clock cycles, or 80 bit times, the signals at pins 28 and 29 will go high. Once the serial data stream passes the cable equalizer function it is directed to an Input Select section. A second high speed serial data input, denoted LIN, is applied at pins # 16 and # 17 and is connected directly to the Input Select section. This data input is intended for diagnostic purposes. It is not affected by the cable equalizer and has no effect on the loss of light detectors. The LIN input should mainly be used when it is desired to directly connect the local transmitter serial output data stream to the local receiver (local loopback). The Input Select function uses the EWRAP signal, pin # 34, to determine which serial data stream to pass on to the rest of the receiver. If EWRAP is high, then the LIN signal is used. If EWRAP is low the DI signal is used. The PLL and Clock select circuitry contains a monolithic, tunable, oscillator. This oscillator phase locks to the selected high speed data input and recovers the high speed serial clock. To keep the internal oscillator tuned close to the incoming signal frequency, an external reference oscillator is applied to the CLKIN input, pin # 7. The signal on the -LCK_REF input, pin # 36, controls whether the receiver oscillator locks to the reference oscillator or to the
+5 V
2 K
8 K POTENTIOMETER PIN #21, DR_REF 2 K
incoming data stream. When -LCK_REF is toggled low, the receiver frequency locks to the signal at CLKIN. When the -LCK_REF pin is toggled high, the receiver phase locks to the selected high speed serial data input. This process of locking to a local reference oscillator, prior to receiving incoming data, improves (shortens) the overall time required by the receiver to acquire lock. The LUNUSE input, pin 73 will cause the receiver to frequency lock on the CLKIN signal under faulty or no input signal conditions. The LUNUSE signal needs to be provided to the receiver by an external open fiber control circuit or other control logic. Once the receiver has locked to the incoming data stream at DI (EWRAP = 0 and -LCKREF = 1), if LUNUSE toggles high then the receiver will switch to frequency lock on CLKIN. If, however, the receiver is locked onto the local data wrapped back to the LI input (EWRAP = 1 and -LCKREF = 1) then the receiver stays locked to the incoming signal at LI even when LUNUSE goes high. In summary, when the LUNUSE input is set low, the receiver frequency locks to the CLKIN signal when the input to -LCKREF is low and phase locks to either the DI or LI signal, depending on which input is selected, when -LCKREF toggles high. LUNUSE then, is used to cause the receiver to frequency lock to the reference oscillator at CLKIN after the receiver has established phase lock to the incoming data signal at DI, and the system determines the link is faulty and not in EWRAP mode.
Figure 6. Simple Circuit Used to Adjust the Voltage on Rx pin # 21, DR_REF.
661
4
RELATIVE GAIN - dB
-LCK_REF 0 1 1 1 1
EWRAP x 0 0 1 1
LUNUSE x 0 1 1 0
Rx Lock CLKIN DI CLKIN LI LI
2 0 -2 -4 -6 -8
The table above llustrates these various settings. Normally, the recovered serial clock is used by the clock generator to generate the various internal clocks the receiver uses including the receive clock outputs RBC0 (pin 69) and RBC1 (pin 67). The final receiver clocking feature is included for test purposes only. By applying a low to the -TCLKSEL input, pin 5, the internal phase locked loop is bypassed and the receiver uses the CLKIN signal as the high speed serial clock. Under normal operating conditions the -TCLKSEL pin should be tied high. In a Fibre Channel link, frame alignment is accomplished through the transmission and detection of the special character K28.5, also known as a comma character. Prior to actual data transmission the system will transmit a comma character over the physical link. To start, the receiver should be frequency locked to the local reference oscillator (-LCKREF set low). To ensure frequency lock is achieved, -LCKREF should be held low for a minimum of 500 sec (see Rx Timing Characteristics, tflock). It then should be toggled high. At this point the receiver will phase lock to the 662
incoming data stream at the DI input but the actual frame or word boundary will be undetermined. The EN_CDET pin (# 38) should be set high now. With the EN_CDET pin set high, the receiver will scan the incoming data stream for a comma character. Once a comma character is received, the internal clocks and registers are reset giving proper frame alignment. The receiver will reset on every comma character that is transmitted as long as EN_CDET is held high. When the internal clock generator is reset due to the detection of a comma character, internal circuitry prevents a clock "sliver" from appearing at the receive clock outputs (RBC0 and RBC1). This antisliver circuit assures each clock output high, or low, will be held for at least one half the frame rate time. When EN_CDET is set low the receiver ignores all incoming comma characters and assumes the current frame and bit alignment is correct. EN_CDET is automatically disabled when -LCKREF is set low. The COM_DET pin, #75, on the receiver will go high when a comma character is detected (see Figure 15). Now that frame alignment has been achieved, the receiver is ready to receive full speed serial data and demultiplex it back to its original 10 bit or 20 bit
-10 1.00E + 06
1.00E + 07
1.00E + 08
1.00E + 09
1.00E + 10
FREQUENCY - f - Hz
Figure 7. Typical Frequency Response Plot of the Internal Input Equalizer.
parallel word format. This data is then placed into the output latch. The data output is presented in the standard TTL output levels and characteristics specified in the dc and ac Electrical Specification tables. When operating in 531 Mbaud mode the receiver generates output data in a single byte wide (10 bits) output format. This is data byte 0 and is denoted RX[00:09] on pins 53 through 62. In 1063 Mbaud mode the data output is generated in a two byte wide (20 bits) format, data byte 0 and data byte 1. Data byte 0 is denoted RX[00:09] on pins 53 through 62 and data byte 1 is denoted RX[10:19] on pins 43 through 52. In standard operation data byte 0 and data byte 1 will both be clocked into the output latch at the same time, on the falling edge of RBC0. An alternate mode of operation is ping-pong mode. In ping-pong mode the data is clocked out 1 byte at a time with byte 0 clocked out on the falling edge of RBC0 and byte 1 clocked out on the falling edge of RBC1. To set the receiver to operate in ping-pong mode, the PPSEL pin, # 76, should be set high (otherwise it should be tied low).
Rx Power Supply Supervisor
A power supply supervisor feature has been designed into the receiver as a system aid during power-up. The -POR (pin # 27) output is held low until the power supply voltage (VCC) crosses the nominal threshold of 4.25 volts. Then, following a delay time determined by the capacitor value connected to the PS_CT pin (# 22), the -POR output goes high. The typical delay time is 8 msec, with a 0.47 F capacitor attached to PS_CT.
90
LOL THRESHOLD VOLTAGE - p-p DIFFERENTIAL - mV
Recommended Handling Precautions
80 70 60 50 40 30 20 10 0 0 0.5 1.0 1.5 2.0 2.5 DEFAULT THRESHOLD
DR_REF VOLTAGE - V
Figure 8. Typical Plot of Loss of Light Threshold Voltage vs. DR_REF Voltage.
Additional circuitry is built into the various input and output pins on these chips to protect them against low level electrostatic discharge, however, they are still ESD sensitive and standard procedures for static sensitive devices should be used in the handling and assembly of the HDMP-1512 and the HDMP-1514. The packing materials used for shipment of these devices was selected to provide ESD protection and to prevent mechanical damage. During test and use, under powerup conditions, extreme care should be taken to prevent the high speed I/Os from being connected to ground as permanent damage to the device is likely.
HDMP-1512 (Tx), HDMP-1514 (Rx)
Absolute Maximum Ratings Operation in excess of any one of these conditions may result in permanent damage. Symbol VCC VIN,TTL VIN,H50 IO,TTL Tstg TJ Tmax Parameter Supply Voltage TTL Input Voltage I-H50 Input Voltage, Figure 9 TTL Output Source Current Storage Temperature Junction Operating Temperature Maximum Assembly Temperature (for 10 seconds maximum) Units V V V mA C C C Min. -0.5 -0.7 VCC - 2.0 -40 0 0 Max. 6.0 VCC + 0.7 VCC + 0.7 13 +130 +130 +260
HDMP-1512 (Tx), HDMP-1514 (Rx)
Specified Operating Rates TC = 0C to +85C, VCC = 4.5 V to 5.5 V Transmit Byte Clock (TBC) (MHz) Min. Max. 52.0 54.0 52.0 54.0 Serial Baud Rate (MBaud/sec) Min. Max. 520 540 1040 1080 663
SPDSEL 0 1
HDMP-1512 (Tx), HDMP-1514 (Rx)
Transmitter & Receiver Byte Rate Clock Requirements TC = 0C to +85C, VCC = 4.5 V to 5.5 V Symbol f Ftol Symm Parameter Nominal Frequency Frequency Tolerance (For Fibre Channel Compliance) Symmetry (Duty Cycle) Unit MHz ppm % Min. 53.120 -100 40 Typ. 53.125 Max. 53.130 +100 60
HDMP-1512 (Tx), HDMP-1514 (Rx)
AC Electrical Specifications TC = 0C to +85C, VCC = 4.5 V to 5.5 V, Unless Otherwise Specified Symbol Parameter tr,TTLin Input TTL Rise Time, 20% to 80% tf,TTLin Input TTL Fall Time, 20% to 80% tr,TTLout Output TTL Rise Time, 20% to 80%, 15 pF Load tf,TTLout Output TTL Fall Time, 20% to 80%, 15 pF Load tr, BLL BLL Rise Time, AC Coupled, 50 source and load, 20% to 80% tf,BLL BLL Fall Time, AC Coupled, 50 source and load, 20% to 80% VSWRi,H50 H50 Input VSWR, AC Coupled, 50 source and load VSWRo,BLL BLL Output VSWR, AC Coupled, 50 source and load VIP,H50 H50 Input Peak-to-Peak Differential Voltage, AC Coupled, 50 Source LOLTh Loss of Light Threshold, Peak-to-Peak, Differential, TC = 60C, VCC = 5.0 V VOP,BLL BLL Output Peak-To-Peak Differential Voltage, AC Coupled, 50 Load PSDT Power Supervisor Delay Time, with PS_CT terminated in 0.47 F
Units nsec nsec nsec nsec psec psec
Min.
Typ. 2 2 2 2 150 150 2.0 2.0 1200 25 1400 15
Max.
4 4 350 350
mV mV mV msec
50 13 1200
2000 40
HDMP-1512 (Tx)
Output Jitter Characteristics TC = 0C to +85C, VCC = 4.5 V to 5.5 V Symbol RJ DJ Parameter RMS Random Jitter at SO, the High Speed Electrical Data Port RMS Deterministic Jitter at SO, the High Speed Electrical Data Port Units psec psec Min. Typ. 10 22 Max.
664
HDMP-1512 (Tx), HDMP-1514 (Rx)
DC Electrical Specifications TC = 0C to +85C, VCC = 4.5 V to 5.5 V Symbol VIH,TTL VIL,TTL VOH,TTL VOL,TTL ICC,Tx ICC,Rx PSTH Parameter TTL Input High Voltage Level, Guaranteed high signal for all inputs, IIH = 100 A TTL Input Low Voltage Level, Guaranteed low signal for all inputs, IIL = -1mA TTL Output High Voltage Level, IOH = 1 mA TTL Output Low Voltage Level, IOL = -1 mA Transmitter VCC Supply Current, without laser biased Receiver VCC Supply Current, with TTL output data 50% 1's Power Supervisor DC Threshold Voltage Unit V V V V mA mA V Min. 2 0 2.4 0 320 400 4.25 Typ. Max. 5 0.8 5 0.6 450 550 4.5
4.0
HDMP-1512 (Tx)
Laser Driver Characteristics TC = 0C to +85C, VCC = 4.5 V to 5.5 V Symbol Ipb Parameter Laser Diode Prebias Current Set Range (Using External pnp Transistor, P1 in Figure 3, with > 100) Laser Diode Modulation Current Set Range (Peak to Peak) into 25 Load Laser Driver Rise Time, 25 load, 20% to 80% Laser Driver Fall Time, 25 load, 20% to 80% Time for VLZTC to Discharge to Fault Threshold when Terminated with C = 0.1 F LZCSE Reference Voltage Bandgap Test Point Reference Voltage Laser Monitor Diode Feedback Voltage Laser Driver DC Operational Amplifier Gain, Unloaded, see Figure 3 Laser Driver DC Operational Amplifier Bandwidth Recommended LZDC Operating Range, Laser Diode DC Bias Control LZDC Laser DC Bias Low Voltage Setting LZDC Laser DC Bias High Voltage Setting LZDC Load Current, over VLZDC_OP LZDC AC Output Impedance LZMDF AC Input Impedance LZMDF Input Current Units mA Min. Typ. 20 Max. 130
Imod tr,LZOUT tf,LZOUT tLZTC VLZCSE VLZBTP VLZMDF ADCOA f-3dB VLZDC_OP VLZDC_DCL VLZDC_DCH ILZDC_L ZLZDC_ACO ZLZMDF_ACI ILZMDF
mA psec psec msec V V V dB MHz V V V mA A
25 325 325 2 0.4 2.3 1.85 35 300 VCC - 1.8 VCC - 0.75 VCC - 2.0 VCC - 0.6 1.3 400 10,000 6
15
665
HDMP-1512 (Tx)
Timing Characteristics TC = 0C to +85C, VCC = 4.5 V to 5.5 V, PPSEL = 0, SPDSEL = 1 Symbol Parameter ts Setup Time th Hold Time t_txlat Transmit Lateny[1]
Units nsec nsec nsec
Min.
Typ.
Max. 2 2.3
18
Note: 1. The Transmitter Latency is defined as the delay time from when a valid data word at TX[00:19] is clocked into the transmitter (triggered by the rising edge of TBC during the time th) and when the first serial bit is transmitted on pins SO (defined by the leading edge of the first bit transmitted).
HDMP-1514 (Rx)
Timing Characteristics TC = 0C to +85C, VCC = 4.5 V to 5.5 V, PPSEL = 0, SPDSEL = 1 Symbol Parameter tflock Frequency Lock Rate, Loop Filter Capacitor = 0.01 F BLT Bit Lock Time ts Setup Time th Hold Time ts ' Setup Time for Data Rx[10:19] in Ping-Pong Mode th ' Hold Time for Data Rx[10:19] in Ping-Pong Mode t_rxlat Receive Latency[1]
Units kHz/sec bit times nsec nsec nsec nsec nsec
Min.
Typ. 100
Max. 2500
2.5 6.0 6 8 38
Note: 1. The Receiver Latency is defined as the delay time from receiving the first serial bit of a parallel data word (defined by the rising edge of the first bit received at pins DI), and when that word is first clocked out at RX[00:19] (as defined by the falling edge of RBC0 or RBC1, following time ts).
HDMP-1512 (Tx), HDMP-1514 (Rx)
Thermal Characteristics, TC = 0C to +85C Symbol Parameter PD, Tx Transmitter Power Dissipation, VCC = +5 V PD, Rx Receiver Power Dissipation, VCC = +5 V jc Thermal Resistance, Junction to Case Units Watt Watt C/Watt Typ. 1.6 2 12
I/O Type Definitions
I/O Type I-TTL O-TTL O-BLL Definition Input TTL. Floats high when left open. Output TTL. 50 buffer line logic output driver. Should be ac coupled to drive 50 loads. It can also drive the I-H50 inputs through differential direct coupling. Note: all unused outputs should be terminated with 50 to VCC. Input with internal 50 terminations. Input is diode level shifted so that it can swing around VCC. Can be driven with single-ended or differential, ac coupled configuration. To avoid permanent damage, these inputs should not be connected to ground. External circuit node. Power supply or ground.
I-H50
C S 666
VCC_TTL
O_TTL
I_TTL
VCC_TTL
800
72
VCC_LOG
VCC_LOG
ESD
ESD
10 K
10 K
6K
36 VBB 1.4 V ESD GND_LOG GND_TTL ESD GND_LOG GND_TTL
Figure 9. O-TTL and I-TTL Simplified Circuit Schematic.
O-BLL
VCC_HS VCC_LOG
I-H50
VCC_HS VCC_LOG 50
80
80
ESD ESD ESD ESD
Zo = 50
0.1 F ESD
ESD ESD
Zo = 50
0.1 F
ESD 50
VCC_HS GND_HS GND_LOG GND_LOG GND_HS
Figure 10. O-BLL and I-H50 Simplified Circuit Schematics. (Note: I-H50 Inputs Should Never Be Connected to Ground as Permanent Damage to the Device May Result.)
667
HDMP-1512 (Tx)Pin Assignments
Pin 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 Name CAP1A CAP1B GND_A GND_A +SO -SO VCC_HS1 +LOUT -LOUT GND_LZHS +SI -SI VCC_HS2 LZCSE VCC_LZBG VCC_LZ1 VCC_LZAC GND_LZHS +LZOUT -LZOUT
VCC_TTL VCC_TTL
Pin 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Name LZDC LZMDF VCC_LZ VCC_LZ GND_LZ GND_LZ LZTC LZBTP FAULT -LZON GND_LOG -COMGEN VCC_LOG PPSEL GND_LOG LZPWRON VCC_LOG NC GND_TTL GND_TTL
Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Name VCC_TTL VCC_TTL TX[00] TX[01] TX[02] TX[03] TX[04] TX[05] TX[06] TX[07] TX[08] TX[09] TX[10] TX[11] TX[12] TX[13] TX[14] TX[15] TX[16] TX[17]
VCC_TTL VCC_TTL
Pin 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Name TX[18] TX[19] VCC_TTL VCC_TTL GND_TTL GND_TTL SPDSEL VCC_LOG -ECLKSEL GND_LOG EWRAP VCC_LOG TBC GND_LOG TS2 TS1 VCC_A VCC_A CAP0A CAP0B
Tx[19]
Tx[18]
Tx[17]
Tx[16]
Tx[15]
Tx[14]
Tx[13]
Tx[12]
Tx[11]
Tx[10]
Tx[09]
Tx[08]
Tx[07]
Tx[06]
Tx[05]
Tx[04]
Tx[03]
Tx[02]
Tx[01]
GND_TTL GND_TTL SPDSEL VCC_LOG -ECLKSEL GND_LOG EWRAP VCC_LOG TBC GND_LOG TS2 TS1 VCC_A VCC_A CAP0A CAP0B
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 65 40 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Tx[00]
GND_TTL GND_TTL NC VCC_LOG LZPWRON GND_LOG PPSEL VCC_LOG -COMGEN GND_LOG -LZON FAULT LZBTP LZTC GND_LZ GND_LZ
HDMP-1512
TOP VIEW
CAP1A
CAP1B
GND_A
GND_A
+SO
-SO
VCC_LZBG
VCC_LZAC
GND_LZHS
+LZOUT
-LZOUT
LZDC
VCC_LZ1
LZMDF
VCC_LZ
GND_LZHS
VCC_HS1
VCC_HS2
Figure 11. HDMP-1512 (Tx) Package Layout, Top View.
668
VCC_LZ
+ LOUT
- LOUT
LZCSE
+SI
-SI
HDMP-1512 (Tx), Signal Definitions
Symbol CAP0[A:B] Signal Name Loop Filter Capacitor Pins [79,80] Loop Filter Capacitor Pins [1,2] Comma Generate Pin [32] External Clock Select Pin [69] Enable Wrap Pin [71] Laser Fault Indicator Pin [29] I/O C Logic Type Description PLL filter capacitor should be connected from pins 79 and 80 to pins 1 and 2 (typical value = 0.01 F). See Figures 18, 19, 20, and 21. PLL filter capacitor should be connected from pins 79 and 80 to pins 1 and 2 (typical value = 0.01 F). See Figures 18, 19, 20, and 21. An active low input, causes the transmitter to internally generate the positive disparity K28.5 byte (0011111010) for transmission. An active low input, selects the TBC inputs to be used as the serial clock, bypassing the PLL. Used mainly for testing. Works in conjunction with TS1 and TS2 to specify input and output ports. Indicates the laser output level has moved outside of the window detector set boundary and the laser test capacitor (LZTC) has discharged to a fault level. This output is reset by the -LZON pin. Normally 0 volts. Used to provide a clean ground plane for the critical PLL and high speed analog cells. Normally 0 volts. Used for all internal PECL logic. Should be completely isolated from the noisy TTL ground. Normally 0 volts. Used for all laser circuitry. Normally 0 volts.
CAP1[A:B]
C
-COMGEN
Input
TTL
-ECLKSEL
Input
TTL
EWRAP FAULT
Input Output
TTL TTL
GND_A GND_LOG
Analog Ground Pins [3,4] Logic Ground Pins [31,35,70,74] Laser Ground Pins [25,26] Laser High Speed Ground Pins [10,18] TTL Ground Pins [39,40,65,66] Local Serial Data Pins [8,9] Laser Bandgap Test Point Pin [28] Laser Current Source Emitter Pin [14] Laser DC Drive Pin [21] Laser Driver Serial Output Pins [19,20] Laser Monitor Diode Feedback Pin [22] Laser Control and Reset Pin [30]
S S
GND_LZ GND_LZHS
S S
GND_TTL LOUT LZBTP
S Output C BLL
Normally 0 volts. Used for all TTL I/O buffer cells. High speed data port, typically connected to the LIN port on the local receiver during serial wrap mode. This pin is internally set to 2.3 VDC and normally should connect to one terminal of the laser DC bias resistor (pot1 Figure 3). Used to set the bias current of the AC laser driver. Typical use is shown in Figure 3 where pot2 is used to set the laser modulation depth. Used to control the laser diode DC bias (Figure 3). AC driver to the laser diode. The outputs should be AC coupled to the laser bias circuit. Connects to the laser monitor diode and one terminal of the laser DC bias resistor (pot1). Under normal operating conditions, the voltage on this pin will be 1.85 V. The laser diode is turned on (active low) or off (high) with this input. In the off state the capacitor on pin LZTC charges, resetting the window detector (Figure 3).
LZCSE
C
LZDC LZOUT
C C
LZMDF
C
-LZON
Input
TTL
669
HDMP-1512 (Tx), Signal Definitions (cont'd.)
Symbol LZPWRON Signal Name Laser Power On Pin [36] Laser Timing Cap Pin [27] Logic Type Description TTL Used in conjunction with the dual loss of light detectors and the OFC circuit to assure the system is ready to power up the laser. C The capacitor connected to this pin will be precharged at power-up. During operation, if the window detector detects the laser bias to be out of range, this capacitor will begin to discharge. If the condition lasts long enough, the capacitor voltage will fall below the fault level and the FAULT pin will go high. Nominal fault level is <1.0 volts. Input TTL A high signal applied to this pin causes the transmitter to clock the data in by alternating between data byte 0 on the rising edge of TBC and data byte 1 one half clock cycle later. When this pin is low, both data bytes are clocked in on the rising edge of TBC. Input H50 The signal on this pin is input directly to the internal laser driver circuitry or the LOUT pin. This input is selected with the proper setting of TS1, TS2 and EWRAP (see Input/Output Select table). Output BLL High speed data output port. See Input/Output Select table to enable this output. Input Input TTL TTL Sets the chip to operate at the serial data rate of 1062.5 Mbaud (high) or 531.25 Mbaud (low). A 53.125 Mhz clock supplied by the host system. This reference clock is multiplied by 10 or 20 to generate the serial bit clock (531.25 MHz or 1062.5 MHz). TS1 and TS2 work in conjunction with EWRAP to specify active input and output ports. Two, 10 bit, pre-encoded data bytes. Byte 0 is comprised of bits TX[00:09] and byte 1 is comprised of bits TX[10:19]. The serialized bit stream is transmitted TX[00] through TX[09] then TX[10] through TX[19]. Provides a clean power source for the critical PLL and high speed analog cells. Normally +5.0 volts. Provides a clean power source for the high speed cells. Noise on this line should be minimized for best performance. Normally +5.0 volts. Provides a clean power source for the high speed cells. Noise on this line should be minimized for best performance. Normally +5.0 volts. Used for all internal PECL logic. Isolate from the noisy TTL supply. Normally +5.0 volts. Power supply for low speed laser driver circuitry. Normally +5.0 volts. Power supply for all laser driver AC circuitry. Normally +5.0 volts. I/O Input
LZTC
PPSEL
Ping-Pong Select Pin [34]
SI
Laser External Serial Input Pins [11,12] Cable Serial Data Output Pins [5,6] Serial Speed Select Pin [67] Transmit Byte Clock Pin [73] Input/Output Select Input Pins [75,76] Data Inputs Pins [43:62]
SO
SPDSEL TBC
TS[1:2]
Input
TTL
TX[00.19]
Input
TTL
VCC_A VCC_HS1
Analog Supply Pins [77, 78] High Speed Supply 1 Pin [7] High Speed Supply 2 Pin [13] Logic Power Supply Pins [33,37,68,72] Laser Power Supply Pins [23,24] Laser Power Supply Pin [16]
S S
VCC_HS2
S
VCC_LOG VCC_LZ VCC_LZ1
S S S
670
HDMP-1512 (Tx), Signal Definitions (cont'd.)
Symbol VCC_LZAC VCC_LZBG VCC_TTL NC Signal Name Laser Power Supply Pin [17] Laser Power Supply Pins [15] TTL Power Supply Pins [41,42,63,64] Pin [38] I/O S S S Logic Type Description Power supply for all high speed laser driver circuitry. Normally +5.0 volts. Power supply for low speed laser driver circuitry. Normally +5.0 volts. Power supply for all TTL buffer I/O cells. Normally +5.0 volts. No connection.
VCC_TTL
VCC_TTL
VCC_TTL
GND_TTL GND_TTL RBC[1] VCC_LOG RBC[0] GND_LOG SPDSEL VCC_LOG L_UNUSE GND_LOG COM_DET PPSEL VCC_A VCC_A CAP0A CAP0B
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 65 40 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
VCC_TTL
Rx[00]
Rx[01]
Rx[02]
Rx[03]
Rx[04]
Rx[05]
Rx[06]
Rx[07]
Rx[08]
Rx[09]
Rx[10]
Rx[11]
Rx[12]
Rx[13]
Rx[14]
Rx[15]
Rx[16]
Rx[17]
Rx[18]
Rx[19]
GND_TTL GND_TTL EN_CDET VCC_LOG -LCK_REF GND_LOG EWRAP VCC_LOG -EQEN GND_LOG NC LOLB LOLA POR GND_HS GND_HS
HDMP-1514
TOP VIEW
CLKIN (& TCLK)
CAP1A
CAP1B
GND_A
GND_A
-TCLKSEL
N_RXTEMP
P_RXTEMP
GND_TTLA
VCC_TTLA
VCC_HS2
-LIN
+LIN
VCC_HS2
-DI
+DI
DR_REF
VCC_HS
PS_CT
VCC_HS
Figure 12. HDMP-1514 (Rx) Package Layout.
GND_HS
VCC_HS
NC
NC
671
HDMP-1514 (Rx) Pin Assignments
Pin 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 Name CAP1A CAP1B GND_A GND_A -TCLKSEL N_RXTEMP CLKIN (TCLK) P_RXTEMP GND_TTLA VCC_TTLA NC NC VCC_HS GND_HS VCC_HS2 -LIN +LIN VCC_HS2 -DI +DI Pin 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name DR_REF PS_CT VCC_HS VCC_HS GND_HS GND_HS -POR LOLA LOLB NC GND_LOG -EQEN VCC_LOG EWRAP GND_LOG -LCK_REF VCC_LOG EN_CDET GND_TTL GND_TTL Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Name VCC_TTL VCC_TTL RX[19] RX[18] RX[17] RX[16] RX[15] RX[14] RX[13] RX[12] RX[11] RX[10] RX[09] RX[08] RX[07] RX[06] RX[05] RX[04] RX[03] RX[02] Pin 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Name RX[01] RX[00] VCC_TTL VCC_TTL GND_TTL GND_TTL RBC[1] VCC_LOG RBC[0] GND_LOG SPDSEL VCC_LOG L_UNUSE GND_LOG COM_DET PPSEL VCC_A VCC_A CAP0A CAP0B
HDMP-1514 (Rx), Signal Definitions
Symbol CAP0[A:B] Signal Name Loop Filter Capacitor Pins [79,80] Loop Filter Capacitor Pins [1,2] Receive Reference Clock Pin [7] Comma Detect Pin [75] Serial Data Inputs Pins [19,20] I/O C Logic Type Description PLL filter capacitor should be connected from pins 79 and 80 to pins 1 and 2 (typical value = 0.01 F). See Figures 18, 19, 20, and 21. PLL filter capacitor should be connected from pins 79 and 80 to pins 1 and 2 (typical value = 0.01 F). See Figures 18, 19, 20, and 21. A 53.125 MHz clock supplied by the host system. CLKIN is used by the internal PLL to acquire frequency lock when the -LCKREF input is brought low. Indicates the detection of a comma character (K28.5 of positive disparity). It is only active when EN_CDET is high. High speed serial data inputs, selected when EWRAP is set low. An optional cable equalizer may also be enabled, see EQEN.
CAP1[A:B]
C
CLKIN (TCLK) COM_DET
Input
TTL
Output
TTL
DI
Input
H50
672
HDMP-1514 (Rx), Signal Definitions (cont'd.)
Symbol DR_REF EN_CDET Signal Name Receiver Reference Pin [21] Enable Comma Detect Pin [38] I/O C Input Logic Type Description This node is used to set the peak-to-peak signal level of the loss of light detection circuitry. When high, the receiver will reset internal clocks and registers when an incoming comma character (K28.5) of positive disparity (0011111xxx) is detected. When low, clocks and registers will not reset and the comma detect output is disabled. Comma detect is also disabled whenever -LCK_REF is set low. When set low, the internal cable equalizer amplifier on the DI lines is enabled. When set high, the high speed data is taken from the LIN port, enabling the data input from the local transmitter. When this input is set low, the high speed input is taken from the DI lines. Normally 0 volts. Used to provide a clean ground plane for the critical PLL and high speed analog cells. Normally 0 volts. Normally 0 volts. Used for all internal PECL logic. Should be completely isolated from the noisy TTL ground. Normally 0 volts. Used for all TTL I/O buffer cells. Normally 0 volts. TTL A low input causes the internal PLL to acquire frequency lock on the external reference signal applied at CLKIN. To assure lock, this pin should be held low for at least 500 sec and held high at all other times. A low input disables the comma detect function. Typically supplied from open fiber control circuitry. Used in conjunction with EWRAP and -LCK_REF to keep the internal Vco near operational frequency, optimizing frequency lock times. High speed data port, typically connected to the LOUT port on the local transmitter when in serial wrap mode. A high signal on this pin indicates the amplitude of the input serial data has fallen below a preset level (see DR_REF) or no transitions have been detected within 4 cycles of TBC. A high signal on this pin indicates the amplitude of the input serial data has fallen below a preset level (see DR_REF) or no transitions have been detected within 4 cycles of TBC. Used in conjunction with pin 8 (P_RXTEMP) to monitor the on-chip temperature diode (Cathode.) Used in conjunction with pin 6 (N_RXTEMP) to monitor the on-chip temperature diode (Anode.) Active low output. Monitors the power supply voltage on startup to assure VCC is at the proper DC level.
TTL
-EQEN EWRAP
Equalizer Enable Input Input Pin [32] Enable Wrap Input Pin [71]
TTL TTL
GND_A GND_HS GND_LOG
Analog Ground Pins [3,4] High Speed Ground Pins [14,25,26] Logic Ground Pins[31,35,70,74] TTL Ground Pins [39,40,65,66] TTL Ground Pin [9] Lock to Reference Pin [36]
S S S
GND_TTL GND_TTLA -LCK_REF
S S Input
L_UNUSE
Link Unusable Pin [73]
Input
TTL
LIN LOLA
Local Serial Data Pins [16,17] Loss of Light Signal Pin [28] Loss of Light Signal Pin [29] Temperature Monitor Pin [6] Temperature Monitor Pin [8] Power on Reset Pin [27]
Input Output
H50 TTL
LOLB
Output
TTL
N_RXTEMP P_RXTEMP -POR
C C Output TTL
673
HDMP-1514 (Rx), Signal Definitions (cont'd.)
Symbol PPSEL Signal Name Ping-Pong Select Pin [76] I/O Input Logic Type Description TTL A high input instructs the receiver to clock the data out in ping-pong mode. Byte 0 will be clocked out on the falling edge of RBC0 and byte 1 will be clocked out on the falling edge of RBC1. A low input instructs the receiver to clock both data bytes out on the falling edge of RBC0. Pin for connecting the timing capacitor for the power supervisor circuit. TTL Two clocks, 180 out of phase, generated from the recovered data. Used to clock out the two 10 bit data bytes. Two, 10 bit, bytes. Byte 0 is comprised of bits RX[00:09] and byte 1 is comprised of bits RX[10:19]. The serialized bit stream is received TX[00] through TX[09] then TX[10] through TX[19]. Sets the chip to operate at the serial data rate of 1062.5 Mbaud (high) or 531.25 Mbaud (low). An applied low selects CLKIN as the serial/bit-rate clock and bypasses the internal PLL. Used for testing only. Provides a clean power source for the critical PLL and high speed analog cells. Normally +5.0 volts. Provides a clean power source for the high speed receiver cell I-H50. Noise on this line should be minimized for best performance. Normally +5.0 volts. Provides a clean power source for the high speed receiver cell I-H50. Noise on this line should be minimized for best performance. Normally +5.0 volts. Used for all internal PECL logic. Isolate from the noisy TTL supply. Normally +5.0 volts. Power supply for all TTL buffer I/O cells. Normally +5.0 volts. Power supply for all TTL I/O buffer cells. Normally +5.0 volts. No connection.
PS_CT
RBC[0:1]
Power Supply Timing Cap Pin [22] Receive Byte Clocks Pin [67, 69] Data Outputs Pins [43, 62]
C
Output
RX[00:19]
Output
TTL
SPDSEL -TCLKSEL VCC_A VCC_HS1
Serial Speed Select Pin [71] Test Clock Select Pin [5] Analog Supply Pins [77, 78] High Speed Supply Pins [13,23,24] High Speed Supply 2 Pins [15,18] Logic Power Supply Pins [33,37,68,72] TTL Power Supply Pins [41,42,63,64] TTL Power Supply Pin [10] Pins [11,12,30]
Input Input S S
TTL TTL
VCC_HS2
S
VCC_LOG VCC_TTL VCC_TTLA NC
S S S
674
Package Description and Assembly Recommendations
The HDMP-1512 and HDMP1514 are available in the industry standard M-Quad 80 lead package. The outline dimensions conform to JEDEC plastic QFP specifications and are shown in Figure 13. The package material is aluminum. To facilitate surface mounting, the leads have been formed into a "GullWing" configuration. We recommend keeping the package temperature, TC, below 85C. Forced air cooling may be required.
M-Quad 80 Package Specifications
Item Package Material Lead Finish Material Lead Finish Thickness Lead Coplanarity Specification Aluminum 85/15 Sn/Pb 300-600 inches 0.004 inches maximum
PIN #1 ID
23.20 0.10 (0.913 0.004)
TOP VIEW
+ 0.18 19.786 - 0.08 + 0.008 - 0.002 0.15 (0.006)
(0.779
)
0.35 TYP. (0.014 ) 0.80 TYP. (0.0315 ) 7
0.80 0.13 (0.031 0.005)
(0.543
+ 0.16 13.792 - 0.04 + 0.008 - 0.002 17.20 0.10 (0.677 0.004)
)
2.64 0.13 (0.104 0.005) 0.38 0.05 (0.015 0.002)
ALL DIMENSIONS ARE IN MILLIMETERS (INCHES).
Figure 13. HDMP-1512 and HDMP-1514 Package Outline.
675
TBC
Tx[00:19]
Figure 14. HDMP-1512 (Transmitter) Timing Diagram, with PPSEL = 0.
,,,,,, , , ,,,,
ts th DATA DATA DATA DATA DATA
COM_DET
Rx[00:19]
RBCO
Figure 15. HDMP-1514 (Receiver) Timing Diagram, with PPSEL = 0.
, , , , ,
K28.5 DATA ts th ts th 18.8 ns
DATA
676
Figure 16. HDMP-1512 (Transmitter) Timing Diagram In Ping-Pong Mode, PPSEL = 1.
Figure 17. HDMP-1514 (Receiver) Timing Diagram in Ping-Pong Mode, with PPSEL = 1.
,,,,,,, ,, ,,, , , ,, ,,, ,,,, ,,, ,,, , ,,,
TBC ts th Tx[00:09] DATA DATA DATA DATA DATA ts th Tx[10:19] DATA DATA DATA DATA 1/2 CLOCK CYCLE (TBC)
Rx[10:19]
DATA
DATA
DATA
ts
th
RBC1
18.8 ns
COM_DET
Rx[00:09]
K28.5
DATA
DATA
ts'
th'
ts'
th'
RBC0
18.8 ns
677
Tx[19]
Tx[18]
Tx[17]
Tx[16]
Tx[15]
Tx[14]
Tx[13]
Tx[12]
Tx[11]
Tx[10]
Tx[09]
Tx[08]
Tx[07]
Tx[06]
Tx[05]
Tx[04]
Tx[03]
Tx[02]
Tx[01]
+5.0 V
Tx[00]
+5.0 V
0.1 F 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 65 40 66 67 68 69 70 EWRAP TBC 71 72 73 74 75 +5.0 V 76 77 78 79 80 1 0.1 F 0.01 F 2 3 4 5 6 7 8 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
0.1 F
NC
HDMP-1512
TOP VIEW
NC NC NC
+5.0 V
+So
-So
+ LOUT
- LOUT
+Si
-Si
NC
NC
NC
NC
0.1 F
Figure 18. Typical Transmitter Pin Terminations for Applications Requiring High Speed Serial Copper Drivers ( So). Laser Driver Outputs are Disabled. For 1062.5 MBd Operation Only, SPDSEL (pin 67) Set High, Non Ping-Pong Mode (PPSEL = 0).
678
NC
Tx[19]
Tx[18]
Tx[17]
Tx[16]
Tx[15]
Tx[14]
Tx[13]
Tx[12]
Tx[11]
Tx[10]
Tx[09]
Tx[08]
Tx[07]
Tx[06]
Tx[05]
Tx[04]
Tx[03]
Tx[02]
Tx[01]
+5.0 V
Tx[00]
+5.0 V
0.1 F 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 65 40 66 67 68 69 70 EWRAP TBC TS1,2 +5.0 V 71 72 73 74 75 76 77 78 79 80 1 0.1 F 0.01 F 2 3 4 5 6 7 8 39 38 37 36
0.1 F
NC LZPWRON*
HDMP-1512
TOP VIEW
35 34 33 32 31 30 29 28 27 26 -LZON* FAULT* LZBTP* LZTC*
25 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 0.1 F
+5.0 V
+So -So + LOUT - LOUT +Si -Si LZCSE* +LZOUT* -LZOUT* LZDC* VCC_LZAC* LZMDF*
Figure 19. Typical Transmitter Pin Terminations for Applications Using the On-Chip Laser Driver. For Details of the Laser Driver Connections, Indicated by "*," see Figure 3 on page 4. For 1062.5 MBd Operation Only, SPDSEL (pin 67) Set High, Non Ping-Pong Mode (PPSEL = 0).
679
Rx[00]
Rx[01]
Rx[02]
Rx[03]
Rx[04]
Rx[05]
Rx[06]
Rx[07]
Rx[08]
Rx[09]
Rx[10]
Rx[11]
Rx[12]
Rx[13]
Rx[14]
Rx[15]
Rx[16]
Rx[17]
Rx[18]
+5.0 V
Rx[19]
+5.0 V
0.1 F 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 65 40 66 RBC1 RBC0 67 68 69 70 71 72 LUNUSE COM_DET +5.0 V 73 74 75 76 77 78 79 80 1 0.1 F 0.01 F 2 3 4 5 6 7 8 39 38 37 36
0.1 F
EN_CDET -LCK_REF EWRAP
HDMP-1514
TOP VIEW
35 34 33 32 31 30 29 28 27 26 NC LOLB LOLA -POR
25 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 0.1 F
+5.0 V
-LIN REFCLK +LIN NC NC -DIN +DIN NC
0.47 F
Figure 20. Typical Receiver Pin Terminations for Applications Using High Speed Serial Copper Links ( DIN). For 1062.5 MBd Operation Only, SPDSEL (pin 71) Set High, Non Ping-Pong Mode (PPSEL = 0).
680
Rx[00]
Rx[01]
Rx[02]
Rx[03]
Rx[04]
Rx[05]
Rx[06]
Rx[07]
Rx[08]
Rx[09]
Rx[10]
Rx[11]
Rx[12]
Rx[13]
Rx[14]
Rx[15]
Rx[16]
Rx[17]
Rx[18]
+5.0 V
Rx[19]
+5.0 V
0.1 F 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 65 40 66 RBC1 RBC0 67 68 69 70 71 72 73 74 COM_DET +5.0 V 75 76 77 78 79 80 1 0.1 F 0.01 F 2 3 4 5 6 7 8 39 38 37 36
0.1 F
EN_CDET -LCK_REF EWRAP
HDMP-1514
TOP VIEW
35 34 33 32 31 30 29 28 27 26 NC LOLB LOLA -POR
25 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 0.1 F
+5.0 V
-LIN REFCLK +LIN NC NC -DIN +DIN NC
0.47 F
Figure 21. Typical Receiver Pin Terminations for Applications Using High Speed Fiber Links ( DIN). For 1062.5 MBd Operation Only, SPDSEL (pin 71) Set High, Non Ping-Pong Mode (PPSEL = 0).
681

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