View CDP1802AC_23862.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CDP1802AC/3
March 1997
High-Reliability CMOS 8-Bit Microprocessor
Description
The CDP1802A/3 High-Reliability LSI CMOS 8-bit register oriented Central-Processing Unit (CPU) is designed for use as a general purpose computing or control element in a wide range of stored-program systems or products. The CDP1802A/3 includes all of the circuits required for fetching, interpreting, and executing instructions which have been stored in standard types of memories. Extensive input/output (I/O) control features are also provided to facilitate system design. The 1800 Series Architecture is designed with emphasis on the total microcomputer system as an integral entity so that systems having maximum flexibility and minimum cost can be realized. The 1800 Series CPU also provides a synchronous interface to memories and external controllers for I/O devices, and minimizes the cost of interface controllers. Further, the I/O interface is capable of supporting devices operating in polled, interrupt-driven, or direct memory-access modes. The CDP1802AC/3 is functionally identical to its predecessor, the CDP1802. The "A" version includes some performance enhancements and can be used as a direct replacement in systems using the CDP1802. This type is supplied in 40 lead dual-in-line sidebrazed ceramic packages (D suffix).
Features
* For Use In Aerospace, Military, and Critical Industrial Equipment
[ /Title (CDP1 802AC /3) /Subject Highelibility MOS 8-Bit icrorocesor) /Autho () /Keyords Interil orpoation, -bit icrorocesors, 8 it icrorocesors, eriphrals) /Cretor () /DOCI FO dfark
* Minimum Instruction Fetch-Execute Time of 4.5s (Maximum Clock Frequency of 3.6MHz) at VDD = 5V, TA = +25oC * Operation Over the Full Military Temperature Range . . . . . . . . . . . . . . . -55oC to +125oC * Any Combination of Standard RAM and ROM Up to 65,536 Bytes * 8-Bit Parallel Organization With Bidirectional Data Bus and Multiplexed Address Bus * 16 x 16 Matrix of Registers for Use as Multiple Program Counters, Data Pointers, or Data Registers * On-Chip DMA, Interrupt, and Flag Inputs * High Noise Immunity . . . . . . . . . . . . . . . . . . 30% of VDD
Ordering Information
PACKAGE SBDIP TEMP. RANGE (oC) -55 to 125 5V - 3.2MHz CDP1802ACD3 PKG NO. D40.6
Pinout
CDP1802AC/3 (SBDIP) TOP VIEW
CLOCK WAIT CLEAR Q SC1 SC0 MRD BUS 7 BUS 6 1 2 3 4 5 6 7 8 9 40 VDD 39 XTAL 38 DMA IN 37 DMA OUT 36 INTERRUPT 35 MWR 34 TPA 33 TPB 32 MA7 31 MA6 30 MA5 29 MA4 28 MA3 27 MA2 26 MA1 25 MA0 24 EF1 23 EF2 22 EF3 21 EF4
BUS 5 10 BUS 4 11 BUS 3 12 BUS 2 13 BUS 1 14 BUS 0 15 VCC 16 N2 17 N1 18 N0 19 VSS 20
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
1441.2
3-30
CDP1802AC/3
ADDRESS BUS
CDP1852 INPUT PORT
CS2
N0
MA0-7
MA0-7
MA0-4
CS1
MRD CDP1802 8-BIT CPU MWR DATA CDP1852 OUTPUT CLOCK PORT CS1 CS2 N1 TPB DATA TPA
MRD CDP1833 1K-ROM
MRD CDP1824 32 BYTE RAM MWR CEO CS DATA
TPA DATA
8-BIT DATA BUS
FIGURE 1. TYPICAL CDP1802A/3 SMALL MICROPROCESSOR SYSTEM
3-31
CDP1802AC/3
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal) CDP1802AC/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, any One Input . . . . . . . . . . . . . . . . . . . . . . . . .10mA
Thermal Information
Thermal Resistance (Typical) JA (oC/W) JC (oC/W) SBDIP Package. . . . . . . . . . . . . . . . . . . . 55 15 Device Dissipation Per Output Transistor TA = Full Package Temperature Range. . . . . . . . . . . . . . . . . 100mW Operating Temperature Range (TA) Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC Storage Temperature Range (TSTG). . . . . . . . . . . .-65oC to +150oC Lead Temperature (During Soldering) At distance 1/16 1/32 In. (1.59 0.79mm) from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Recommended Operating Conditions
PARAMETER DC Operating Voltage Range Input Voltage Range Maximum Clock Input Rise or Fall Time
TA = Full Package Temperature Range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges MIN 4 VSS MAX 6.5 VDD 1 UNITS V V s
Performance Specifications
PARAMETER Minimum Instruction Time (Note 1) Maximum DMA Transfer Rate Maximum Clock Input Frequency, Load Capacitance (CL) = 50pF, fCL NOTE: 1. Equals 2 machine cycles - one Fetch and one Execute operation for all instructions except Long Branch and Long Skip, which require 3 machine cycles - one Fetch and two Execute operations. VDD (V) 5 5 5 -55oC TO +25oC 4.5 450 DC-3.6 +125oC 5.9 340 DC-2.7 UNITS s Kbytes/s MHz
Static Electrical Specifications
All Limits are 100% Tested CONDITIONS VOUT (V) 0.4 -55oC, +25oC +125oC
PARAMETER Quiescent Device Current, IDD Output Low Drive (Sink) Current (Except XTAL), IOL XTAL Output High Drive (Source) Current (Except XTAL), IOH XTAL Output Voltage Low-Level, VOL Output Voltage High-Level, VOH
VIN, (V) 0, 5
VCC, VDD (V) 5 5
MIN 1.20
MAX 100 -
MIN 0.90
MAX 250 -
UNITS A mA
0.4
5
5
185
-
140
-
A
4.6 4.6 -
0, 5 0 0, 5 0, 5
5 5 5 5
4.9
-0.30 -135 0.1 -
4.8
-0.20 -100 0.2 -
mA A V V
3-32
CDP1802AC/3
Static Electrical Specifications
All Limits are 100% Tested (Continued) CONDITIONS VOUT (V) 0.5, 4.5 0.5, 4.5 Any Input 0, 5 -55oC, +25oC +125oC
PARAMETER Input Low Voltage, VIL Input High Voltage, VIH Input Leakage Current, IIN
VIN, (V) 0, 5
VCC, VDD (V) 5 5 5
MIN 3.5 -
MAX 1.5 1 1
MIN 3.5 -
MAX 1.5 5 5
UNITS V V A A
Three-State Output Leakage Current, IOUT NOTE:
0, 5
5
-
-
2. 5V level characteristics apply to Part No. CDP1802AC/3, and 5V and 10V level characteristics apply to part No. CDP1802A/3.
Timing Specifications
As a Function of T (T = 1/fCLOCK), CL = 50 pF LIMITS (NOTE 3) PARAMETER VDD (V) Time, tSU 5 5 5 5 5 -55oC, +25oC 2T-450 T/2 +0 T-30 T-170 5T-300 +125oC 2T-580 T/2 +0 T-40 T-250 5T-400 UNITS ns ns ns ns ns
High-Order Memory-Address Byte Setup to TPA
High-Order Memory-Address Byte Hold After TPA Time, tH Low-Order Memory-Address Byte Hold After WR Time, tH CPU Data to Bus Hold After WR Time, tH Required Memory Access Time Address to Data, tACC NOTE: 3. These limits are not directly tested.
Implicit Specifications
(Note 4) TA = -55oC to +25oC TYPICAL VALUES 4
PARAMETER Typical Total Power Dissipation Idle "00" at M(0000), CL = 50pF Effective Input Capacitance any Input Effective Three-State Terminal Capacitance Data Bus Minimum Data Retention Voltage Data Retention Current NOTE: f = 2MHz
SYMBOL -
VDD (V) 5
UNITS mW
-
CIN
-
5 7.5 2.4 10
pF pF V A
VDR IDR
2.4
4. These specifications are not tested. Typical values are provided for guidance only.
3-33
CDP1802AC/3
Dynamic Electrical Specifications
CL = 50pF, Timing Measurement at 0.5 VDD Point -55oC TO +25oC PARAMETERS Progagation Delay Times, tPLH, tPHL Clock to TPA, TPB Clock-to-Memory High Address Byte, tPLH, tPHL Clock-to-Memory Low Address Byte Valid, tPLH, tPHL Clock to MRD, tPLH, tPHL Clock to MWR, tPLH, tPHL Clock to (CPU DATA to BUS) Valid, tPLH, tPHL Clock to State Code, tPLH, tPHL Clock to Q, tPLH, tPHL Clock to N (0 - 2), tPLH, tPHL Interface Timing Requirements (Note 5) Data Bus Input Setup, tSU Data Bus Input Hold, t H DMA Setup, tSU DMA Hold, t H Interrupt Setup, t SU Interrupt Hold, tH WAIT Setup, tSU EF1-4 Setup, tSU EF1-4 Hold, tH Required Pulse Width Times CLEAR Pulse Width, tWL CLOCK Pulse Width, tWL NOTE: 5. Minimum input setup and hold times required by Part CDP1802AC/3. 5 5 150 140 200 185 ns ns 5 5 5 5 5 5 5 5 5 10 175 10 200 10 175 30 20 100 10 230 10 270 10 230 30 20 135 ns ns ns ns ns ns ns ns ns 5 5 5 5 5 5 5 5 5 275 725 340 340 275 430 440 375 400 370 950 425 425 370 550 550 475 525 ns ns ns ns ns ns ns ns ns VDD (V) MIN MAX +125oC MIN MAX UNITS
3-34
CDP1802AC/3
0 CLOCK tW 00 01 10
1 20
2 30
3 40
4 50
5 60
6 70
7 00
0
11
21
31
41
51
61
71
01
tPLH TPA
tPHL
tPLH TPB tSU MEMORY ADDRESS MRD (MEMORY READ CYCLE) MWR (MEMORY WRITE CYCLE)
tPLH, tPHL
tPHL
tH
tPLH, tPHL
HIGH ORDER ADDRESS BYTE
LOW ORDER ADDRESS BYTE
tPLH, tPHL
tPLH
tPHL
tPLH
tPLH tPHL
tPHL
tPLH
DATA FROM CPU TO BUS
tPLH, tPHL
STATE CODES
tPLH tPHL tPLH, tPHL
tPLH tPHL
Q N0, N1, N2 (I/O EXECUTION CYCLE)
tPLH
tPHL DATA LATCHED IN CPU
DATA FROM BUS TO CPU DMA DMA REQUEST tSU
tSU
tH
SAMPLED (S1, S2, S3) tH
INTERRUPT SAMPLED (S1, S2) FLAG LINES SAMPLED (IN SI) tSU tH
INTERRUPT REQUEST
tSU
tH
EF 1-4
WAIT
tSU
ANY NEGATIVE TRANSITION
CLEAR
tW
NOTES: 6. This timing diagram is used to show signal relationships only, and does not represent any specific machine cycle. 7. All measurements are referenced to 50% point of the waveforms. 8. Shaded areas indicate "don't care" or undefined state. Multiple transitions may occur during this period. FIGURE 2. TIMING WAVEFORMS
3-35
CDP1802AC/3 Performance Curves
SYSTEM MAXIMUM CLOCK FREQUENCY (fCL) (MHz) SYSTEM MAXIMUM CLOCK FREQUENCY (fCL) (MHz) 8 LOAD CAPACITANCE (CL) = 50pF 7 6 5 4 VDD = 5V 3 2 1 0 25 35 45 55 65 75 85 95 105 115 125 8 LOAD CAPACITANCE (CL) = 50pF 7 6 5
LA TE D PO
TA = 25oC
4 3 2 1 0 2 3
EX TR
TA = 125oC
A
4
5
6
7
8
9
10
11
12
AMBIENT TEMPERATURE (TA) (oC)
SUPPLY VOLTAGE (VDD) (V)
FIGURE 3. TYPICAL MAXIMUM CLOCK FREQUENCY AS A FUNCTION OF TEMPERATURE
400
FIGURE 4. TYPICAL MAXIMUM CLOCK FREQUENCY AS A FUNCTION OF SUPPLY VOLTAGE
0 OUTPUT HIGH (SOURCE) CURRENT (IOH -mA)
TRANSITION TIME (tTHL, t TLH) (ns)
350 300 250 200 150 100 50 0 0
AMBIENT TEMPERATURE (TA) = 25oC
GATE TO SOURCE VOLTAGE (VGS) = -5V 1 2 3 4 AMBIENT TEMPERATURE = -40 TO +85oC 5 6 -10
tTLH tTHL
25
50 75 100 125 150 LOAD CAPACITANCE (CL) (pF)
175
200
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
DRAIN TO SOURCE VOLTAGE (VDS) (V)
FIGURE 5. TYPICAL TRANSITION TIME vs LOAD CAPACITANCE
OUTPUT LOW (SINK) CURRENT (IOL) (mA) 35 AMBIENT TEMPERATURE = -40oC TO +85oC 30 25 20 15 10 5 0 0 1 2 3 4 5 6 7 8 9 10 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
1000 TYPICAL POWER DISSIPATION (PD) (mW) AMBIENT TEMPERATURE (TA) = 25oC 100
10
V CC
D = VD
=5
V =+ 5V
GATE TO SOURCE VOLTAGE (VGS) = 5V
1
"B
RA
N
" CH
V CC
D = VD
"ID
" LE
0.1 0.01
0.1
1
10
CLOCK INPUT FREQUENCY (f CL) (MHz)
NOTES: 9. Idle = "00" at M (0000) 10. Branch = "3707" at M (8107)
FIGURE 7. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
FIGURE 8. TYPICAL POWER DISSIPATION AS A FUNCTION OF CLOCK FREQUENCY FOR BRANCH INSTRUCTION AND IDLE INSTRUCTION
3-36
CDP1802AC/3 Performance Curves
(Continued)
150 PROPAGATION DELAY TIME (tPLH, tPHL) (ns) AMBIENT TEMPERATURE (TA) = 25oC
125 100 75
V
C C
=
50
V
25 0
t PL
H
VCC t PH
L
= VDD
0
50 100 150 LOAD CAPACITANCE ( CL) (pF)
D D
=
= 5V
5V
200
NOTE: Any output except XTAL. FIGURE 9. TYPICAL CHANGE IN PROPAGATION DELAY AS A FUNCTION OF A CHANGE IN LOAD CAPACITANCE
Burn-In Circuit
VDD 1 2 3 4 5 6 7 8 NC 9 10 11 12 13 14 15 VDD NC 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD NC VDD
ALL RESISTORS ARE 47k 20%
TYPE CDP1802AC
VDD 7V
TEMPERATURE +125oC
TIME 160 Hours
FIGURE 10. BIAS/STATIC BURN-IN CIRCUIT
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
3-37

▲Up To Search▲

Price & Availability of CDP1802AC

	To Download CDP1802AC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .