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High Performance 32Kx8 CMOS SRAM 32Kx8 CMOS SRAM (Common I/O)
FEATURES
* Organization: 32,768 words x 8 bits * High speed - 10/12/15/20/25/35 ns address access time - 3/3/4/5/6/8 ns output enable access time * Low power consumption - Active: - Standby: 660 mW max (10 ns cycle) 11 mW max, CMOS I/O 2.75 mW max, CMOS I/O, L version * Equal access and cycle times
AS7C256 AS7C256L
* Easy memory expansion with CE and OE inputs * TTL-compatible, three-state I/O * 28-pin JEDEC standard packages - 300 mil PDIP and SOJ Socket compatible with 7C512 and 7C1024 - 330 mil SOIC - 8x13.4 TSOP * ESD protection > 2000 volts * Latch-up current > 200 mA
- Very low DC component in active power * 2.0V data retention (L version)
LOGIC BLOCK DIAGRAM
PIN ARRANGEMENT
DIP, SOJ, SOIC
Vcc GND INPUT BUFFER
A0 A1 A2 A3 A4 A5 A6 A14
ROW DECODER
I/O7 256x128x8 ARRAY (262,144) SENSE AMP
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
Vcc WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
I/O0
TSOP 8x13.4
COLUMN DECODER WE CONTROL CIRCUIT OE CE AAAAAAA 7 8 9 10 11 12 13
AS7C256-01
SELECTION GUIDE
7C256-10 Maximum Address Access Time Maximum Output Enable Access Time Maximum Operating Current Maximum CMOS Standby Current 10 3 120 2.0 L 0.5 7C256-12 12 3 115 2.0 0.5
OE A11 A9 A8 A13 WE Vcc A14 A12 A7 A6 A5 A4 A3
22 23 24 25 26 27 28 1 2 3 4 5 6 7
AS7C256
AS7C256
21 20 19 18 17 16 15 14 13 12 11 10 9 8
A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 AS7C256-02 A1 A2
7C256-15 15 4 110 2.0 0.5
7C256-20 20 5 100 2.0 0.5
7C256-25 25 6 90 2.0 0.5
7C256-35 35 8 80 2.0 0.5
Unit ns ns mA mA mA
ALLIANCE SEMICONDUCTOR
AS7C256 AS7C256L
FUNCTIONAL DESCRIPTION The AS7C256 is a high performance CMOS 262,144-bit Static Random Access Memory (SRAM) organized as 32,768 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20/25/35 ns with output enable access times (tOE) of 3/3/4/5/6/8 ns are ideal for high performance applications. A chip enable (CE) input permits easy memory expansion with multiple-bank memory organizations. When CE is HIGH the device enters standby mode. The standard AS7C256 is guaranteed not to exceed 11 mW power consumption in standby mode; the L version is guaranteed not to exceed 2.75 mW, and typically requires only 500 W. The L version also offers 2.0V data retention, with maximum power consumption in this mode of 300 W. A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) HIGH. The chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is HIGH, or write enable is LOW, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply. The AS7C256 is packaged in all high volume industry standard packages.
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on Any Pin Relative to GND Power Dissipation Storage Temperature (Plastic) Temperature Under Bias DC Output Current Symbol Vt PD Tstg Tbias Iout Min -0.5 - -55 -10 - Max +7.0 1.0 +150 +85 20 Unit V W
oC oC
mA
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
.
TRUTH TABLE
CE H L L L WE X H H L OE X H L X Data High Z High Z Dout Din Mode Standby (ISB, ISB1) Output Disable Read Write
Key: X = Don't Care, L = LOW, H = HIGH
2
AS7C256 AS7C256L
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Symbol VCC GND VIH VIL Min 4.5 0.0 2.2 -0.5* Typ 5.0 0.0 - -
(Ta = 0C to +70C)
Max 5.5 0.0 VCC+1 0.8 Unit V V V V
Input Voltage *VIL min = -3.0V for pulse width less than tRC/2.
DC OPERATING CHARACTERISTICS1
-10 Parameter Input Leakage Current Output Leakage Current Operating Power Supply Current Symbol Test Conditions
(VCC = 5V10%, GND = 0V, Ta = 0C to +70C)
-12 -15 -20 -25 -35
Min Max Min Max Min Max Min Max Min Max Min Max Unit - - - L - - L - - L - - 2.4 1 1 120 115 45 40 2.0 0.5 0.4 - - - - - - - - - - 2.4 1 1 115 110 40 35 2.0 0.5 0.4 - - - - - - - - - - 2.4 1 1 110 105 30 25 2.0 0.5 0.4 - - - - - - - - - - 2.4 1 1 100 95 30 25 2.0 0.5 0.4 - - - - - - - - - - 2.4 1 1 90 85 25 20 2.0 0.5 0.4 - - - - - - - - - - 2.4 1 1 80 75 25 20 2.0 0.5 0.4 -
|ILI| |ILO|
ICC ISB
VCC = Max, Vin = GND to VCC CE = VIH, VCC = Max, Vout = GND to VCC CE = VIL, f = fmax, Iout = 0 mA CE = VIH, f = fmax CE > VCC-0.2V, f = 0, Vin 0.2V or Vin VCC-0.2V IOL = 8 mA, VCC = Min IOH = -4 mA, VCC = Min
A A
mA mA mA mA mA mA V V
Standby Power Supply Current
ISB1 VOL VOH
Output Voltage
CAPACITANCE2
Parameter Input Capacitance I/O Capacitance Symbol CIN CI/O Signals A, CE, WE, OE I/O
(f = 1 MHz, Ta = Room Temperature, VCC = 5V)
Test Conditions Vin = 0V Vin = Vout = 0V Max 5 7 Unit pF pF
3
AS7C256 AS7C256L
READ CYCLE 3, 9
-10 Parameter Read Cycle Time Address Access Time Chip Enable (CE) Access Time Output Enable (OE) Access Time Output Hold from Address Change CE LOW to Output in Low Z CE HIGH to Output in High Z OE LOW to Output in Low Z OE HIGH to Output in High Z Power Up Time Power Down Time -12
(VCC = 5V10%, GND = 0V, Ta = 0C to +70C)
-15 -20 -25 -35 Notes
Symbol Min Max Min Max Min Max Min Max Min Max Min Max Unit tRC tAA tACE tOE tOH tCLZ tCHZ tOLZ tOHZ tPU tPD 10 - - - 2 3 - 0 - 0 - - 10 10 3 - - 3 - 3 - 10 12 - - - 3 3 - 0 - 0 - - 12 12 3 - - 3 - 3 - 12 15 - - - 3 3 - 0 - 0 - - 15 15 4 - - 4 - 4 - 15 20 - - - 3 3 - 0 - 0 - - 20 20 5 - - 5 - 5 - 20 25 - - - 3 3 - 0 - 0 - - 25 25 6 - - 6 - 6 - 25 35 - - - 3 3 - 0 - 0 - - 35 35 8 - - 8 - 8 - 35 ns ns ns ns ns ns ns ns ns ns ns
3 3
5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5
TIMING WAVEFORM OF READ CYCLE 13, 6, 7, 9
tRC Address tAA Dout
AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA
(Address Controlled)
tOH Data Valid
TIMING WAVEFORM OF READ CYCLE 23, 6, 8, 9
tRC1 CE OEAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA tOLZ
AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA
(CE Controlled)
tOE
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tACE Dout tCLZ Supply Current tPU
tOHZ tCHZ
Data Valid tPD ICC ISB
AS7C256-04
50%
50%
4
AS7C256 AS7C256L
WRITE CYCLE 11
-10 Parameter Write Cycle Time Chip Enable to Write End Address Setup to Write End Address Setup Time Write Pulse Width Address Hold From End of Write Data Valid to Write End Data Hold Time Write Enable to Output in High Z Output Active from Write End -12
(VCC = 5V10%, GND = 0V, Ta = 0C to +70C)
-15 -20 -25 -35
Symbol Min Max Min Max Min Max Min Max Min Max Min Max Unit Notes tWC tCW tAW tAS tWP tAH tDW tDH tWZ tOW 10 9 9 0 7 0 6 0 - 3 - - - - - - - - 5 - 12 10 10 0 8 0 6 0 - 3 - - - - - - - - 5 - 15 12 12 0 9 0 8 0 - 3 - - - - - - - - 5 - 20 12 12 0 12 0 10 0 - 3 - - - - - - - - 5 - 20 15 15 0 15 0 10 0 - 3 - - - - - - - - 5 - 30 20 20 0 17 0 15 0 - 3 - - - - - - - - 5 - ns ns ns ns ns ns ns ns ns ns 4, 5 4, 5 4, 5
TIMING WAVEFORM OF WRITE CYCLE 1 10, 11
tWC tAW Address WE
AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA
(WE Controlled)
tAH
tWP tDW Data Valid tWZ tOW tDH
tAS Din
Dout
AS7C256-05
TIMING WAVEFORM OF WRITE CYCLE 2 10, 11
tWC tAW Address tAS CE WE AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tWZ Din Dout
AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
(CE Controlled)
tAH
tCW tWP tDW Data Valid
AS7C256-06
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tDH
5
AS7C256 AS7C256L
DATA RETENTION CHARACTERISTICS
Parameter VCC for Data Retention Data Retention Current Chip Enable to Data Retention Time Operation Recovery Time Input Leakage Current Symbol VDR ICCDR tCDR tR VCC = 2.0V CE VCC-0.2V Vin VCC-0.2V or Vin 0.2V Test Conditions Min 2.0 - 0 tRC - Max - 150 - - 1
(L Version Only)
Unit V
A
ns ns
| ILI |
A (L Version Only)
DATA RETENTION WAVEFORM
Data retention mode VCC 4.5V tCDR CE AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
VDR 2.0V
4.5V tR
VDR
VIH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AS7C256-07
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AC TEST CONDITIONS
- Output load: see Figure B, except for tCLZ and tCHZ see Figure C. - Input pulse level: GND to 3.0V. See Figure A. - Input rise and fall times: 5 ns. See Figure A. - Input and output timing reference levels: 1.5V. Dout 90% 10% 90% 10% 255 30 pF* GND Figure B: Output Load
AS7C256-09
Thevenin Equivalent: 168 Dout +1.728V +5V 480 +5V 480 Dout 255 5 pF*
*including scope and jig capacitance
+3.0V GND
Figure A: Input Waveform
AS7C256-08
GND Figure C: Output Load for tCLZ, tCHZ
AS7C256-10
NOTES
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled and not 100% tested. For test conditions, see AC Test Conditions, Figures A, B, C. tCLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured 500mV from steady-state voltage. This parameter is guaranteed but not tested. WE is HIGH for read cycle. CE and OE are LOW for read cycle. Address valid prior to or coincident with CE transition LOW. All read cycle timings are referenced from the last valid address to the first transitioning address. CE or WE must be HIGH during address transitions. All write cycle timings are referenced from the last valid address to the first transitioning address.
6
AS7C256 AS7C256L
TYPICAL DC AND AC CHARACTERISTICS
Normalized supply current ICC, ISB vs. supply voltage VCC 1.4 1.2 Normalized ICC, ISB 1.0 0.8 0.6 0.4 0.2 0.0 4.0 4.5 5.0 5.5 Supply voltage (V) Normalized access time tAA vs. supply voltage VCC 6.0 ISB Normalized ICC, ISB ICC Normalized supply current ICC, ISB vs. ambient temperature Ta 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -55 ISB ICC Normalized ISB1 (log scale) 625 25 5 1 0.2 Normalized supply current ISB1 vs. ambient temperature Ta
VCC = 5.0V
0.04 -55 -10 35 80 125 Ambient temperature (C)
-10 35 80 125 Ambient temperature (C) Normalized access time t AA vs. ambient temperature Ta
1.5 Normalized access time 1.4 1.3 1.2 1.1 1.0 0.9 0.8 4.0
1.5 Normalized access time 1.4
1.4 1.2
Normalized supply current ICC vs. cycle frequency 1/tRC, 1/tWC
Ta = 25C
1.2 1.1 1.0 0.9 0.8 -55 -10 35 80 125 Ambient temperature (C) Output sink current I OL vs. output voltage VOL
Normalized ICC
1.3
VCC = 5.0V
1.0 0.8 0.6 0.4 0.2 0.0 0
VCC = 5.0V Ta = 25C
4.5 5.0 5.5 Supply voltage (V) Output source current I OH vs. output voltage VOH
6.0
25 50 75 Cycle frequency (MHz)
100
Typical access time change tAA vs. output capacitive loading 35 30 Change in tAA (ns) VCC = 4.5V
140 Output source current (mA) 120 100 80 60 40 20 0 0.0
140 Output sink current (mA) 120 100 80 60 40 20 0 0.0
VCC = 5.0V Ta = 25C
VCC = 5.0V Ta = 25C
25 20 15 10 5 0
1.25 2.5 3.75 Output voltage (V)
5.0
1.25 2.5 3.75 Output voltage (V)
5.0
0
250 500 750 Capacitance (pF)
1000
AS7C256-11
7
AS7C256 AS7C256L
ORDERING CODES
Package / Access Time Plastic DIP, 300 mil Plastic SOJ, 300 mil Plastic SOIC, 330 mil TSOP 8x13.4 10 ns AS7C256-10PC AS7C256L-10PC AS7C256-10JC AS7C256L-10JC AS7C256-10SC AS7C256L-10SC AS7C256-10TC AS7C256L-10TC 12 ns AS7C256-12PC AS7C256L-12PC AS7C256-12JC AS7C256L-12JC AS7C256-12SC AS7C256L-12SC AS7C256-12TC AS7C256L-12TC 15 ns AS7C256-15PC AS7C256L-15PC AS7C256-15JC AS7C256L-15JC AS7C256-15SC AS7C256L-15SC AS7C256-15TC AS7C256L-15TC 20 ns AS7C256-20PC AS7C256L-20PC AS7C256-20JC AS7C256L-20JC AS7C256-20SC AS7C256L-20SC AS7C256-20TC AS7C256L-20TC 25 ns AS7C256-25PC AS7C256L-25PC AS7C256-25JC AS7C256L-25JC AS7C256-25SC AS7C256L-25SC AS7C256-25TC AS7C256L-25TC 35 ns AS7C256-35PC AS7C256L-35PC AS7C256-35JC AS7C256L-35JC AS7C256-35SC AS7C256L-35SC AS7C256-35TC AS7C256L-35TC
PART NUMBERING SYSTEM
AS7C SRAM Prefix 256 Device Number X Blank L = Standard Power = Low Power -XX Access Time X Package: P = PDIP 300 mil J = SOJ 300 mil S = SOIC 330 mil T = TSOP 8x14 C Commercial Temperature Range, 0C to 70 C
REPRESENTATIVES, DISTRIBUTORS, AND SALES OFFICES
DOMESTIC REPS
ALABAMA
Concord Component (205) 772-8883
INDIANA
CC Electro Sales (317) 921-5000
NEW HAMPSHIRE
Kitchen & Kutchin Inc. (617) 229-2660
SOUTH CAROLINA
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CANADA
Tech Trek Ltd. Mississauga: (905) 238-0366 Montreal: (514) 337-7540 Ottawa: (613) 599-8787 Vancouver: (604) 276-8735 Calgary: (403) 291-6866
PUERTO RICO
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KANSAS
CenTech (816) 358-8100
NEW JERSEY
North: ERA Associates (800) 645-5500 South: Vantage Sales (609) 424-6777
SOUTH DAKOTA
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TAIWAN
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Competitive Technology (602) 265-9224
KENTUCKY
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LOUISIANA
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TEXAS
Southern States Marketing
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DISTRIBUTORS
All-American Locations Nationwide Headquarters: (305) 621-8282 Axis Components Sunnyvale, CA (408) 522-9595 Axis Components Irvine, CA (714) 459-5510 Future Electronics Locations Worldwide Headquarters: (514) 594-7710 Interface Electronics Hopkinton, MA (800) 632-7792 (508) 435-0100
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Chesapeake Technology (301) 236-0530
HONG KONG
Eastele Technology +85-2-798-8860
MICHIGAN
Enco Group (810) 338-8600
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DELAWARE
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Priya Electronics, Inc. San Jose, CA USA (408) 954-1866
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FLORIDA
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MISSOURI
East: CenTech (314) 291-4230 West: CenTech (816) 358-8100
OHIO
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ISRAEL
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SALES OFFICES
HEADQUARTERS
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GEORGIA
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WYOMING
Technology Sales (303) 777-9726
HAWAII
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NORTHEAST AREA
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IDAHO
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PENNSYLVANIA
East: Vantage Sales (609) 424-6777 West: Midwest Marketing (216) 381-8575
INTERNATIONAL
AUSTRALIA
NJS Technology Pty Ltd. Mulgrave, Victoria +61-3-562-1244 R&D Electronics Dingley, Victoria +61-3-558-0444
KOREA
FM Korea +822-575-9720 Woo Young Tech +822-369-7099
ILLINOIS
North: El-Mech (312) 794-9100 South: CenTech (314) 291-4230
NEVADA
North: Brooks Technical (415) 960-3880 South: Competitive Tech. (602) 265-9224
RHODE ISLAND
Kitchen & Kutchin Inc. (617) 229-2660
MALAYSIA, SINGAPORE
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TECHNICAL CENTER
TAIWAN
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Alliance Semiconductor reserves the right to make changes in this data sheet at any time to improve design and supply the best product possible. Alliance Semiconductor cannot assume responsibility for circuits shown or represent that they are free from patent infringement. Alliance products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of Alliance. The Alliance logo is a trademark of Alliance Semiconductor Corporation. All other trademarks are property of their respective holders.
ALLIANCE SEMICONDUCTOR
Printed in U.S.A. 3099 North First Street San Jose, CA 95134 (408) 383-4900 Fax (408) 383-4999 Copyright (c) 1995 All rights reserved. May 1996

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