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74LVC574A Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State)
Product specification 1998 Jul 29
Philips Semiconductors
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State)
74LVC574A
FEATURES
* 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic * Supply voltage range of 2.7V to 3.6V * Complies with JEDEC standard no. 8-1A * Inputs accept voltages up to 5.5V * CMOS low power consumption * Direct interface with TTL levels * High impedance when VCC = 0V * 8-bit positive edge-triggered register * Independent register and 3-State buffer operation * Flow-through pin-out architecture
DESCRIPTION
The 74LVC574A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment. The 74LVC574A is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-State outputs for bus-oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. The eight flip-flops will store the state of their individual D-inputs that meet the setup and hold times requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the eight flip-flops is available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The '574A' is functionally identical to the '374A', but the '374A' has a different pin arrangement.
QUICK REFERENCE DATA
GND = 0V; Tamb =25C; tr = tf v 2.5ns SYMBOL tPHL/tPLH fmax CI CPD PARAMETER Propagation delay CP to Qn maximum clock frequency Input capacitance Power dissipation capacitance per flip-flop Notes 1 and 2 CONDITIONS CL = 50pF VCC = 3.3V TYPICAL 4.8 150 5.0 20 UNIT ns MHz pF pF
NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD x VCC2 x fi + S (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL x VCC2 x fo) = sum of outputs. 2. The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES 20-Pin Plastic Shrink Small Outline (SO) 20-Pin Plastic Shrink Small Outline (SSOP) Type II 20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I TEMPERATURE RANGE -40C to +85C -40C to +85C -40C to +85C OUTSIDE NORTH AMERICA 74LVC574A D 74LVC574A DB 74LVC574A PW NORTH AMERICA 74LVC574A D 74LVC574A DB 7LVC574APW DH PKG. DWG. # SOT163-1 SOT339-1 SOT360-1
1998 Jul 29
2
853-1863 19804
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State)
74LVC574A
PIN DESCRIPTION
PIN NUMBER 1 2, 3, 4, 5, 6, 7, 8, 9 19, 18, 17, 16, 15, 14, 13, 12 10 11 20 SYMBOL OE D0-D7 Q0-Q7 GND CP VCC FUNCTION Output enable input (active-Low) Data inputs Data outputs Ground (0V) Clock input (LOW-to-HIGH, edge-triggered) Positive supply voltage
LOGIC SYMBOL (IEEE/IEC)
1 11 EN
C1
2 3 4 5 6
1D
19 18 17 16 15 14 13 12
PIN CONFIGURATION
7 8 9
OE D0 D1 D2 D3 D4 D5 D6 D7
1 2 3 4 5 6 7 8 9
20 VCC 19 Q0 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7 11 CP 7 D5 D6 D7 CP OE 2 3 4 5 6 D0 D1 D2 D3 D4 FF! to FF8
SA00402
FUNCTIONAL DIAGRAM
Q0 Q1 Q2 Q3 3-State OUTPUTS Q4 Q5 Q6 Q7
19 18 17 16 15 14 13 12
GND 10
SA00400
8 9 11
LOGIC SYMBOL
11
1
SA00403
2 3 4 5 6 7 8 9
D0 D1 D2 D3 D4 D5 D6 D7
CP
Q0 Q1 Q2 Q3 Q4 Q5 Q6
19 18 17 16 15 14 13 12
OE
Q7
1
SA00401
1998 Jul 29
3
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State)
74LVC574A
LOGIC DIAGRAM
D0 D1 D2 D3 D4 D5 D6 D7
D CP FF1
Q
D CP FF2
Q
D CP FF3
Q
D CP
Q
D CP FF5
Q
D CP FF6
Q
D CP FF7
Q
D CP FF8
Q
FF4
CP
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
SA00404
FUNCTION TABLE
INPUTS OPERATING MODES Load and read register Load register and disable outputs H h L l Z OE L L H H LE Dn l h l h INTERNAL FLIP-FLOPS L H L H OUTPUTS Q0 to Q7 L H Z Z
= HIGH voltage level = HIGH voltage level one setup time prior to the LOW-to-HIGH CP transition = LOW voltage level = LOW voltage level one setup time prior to the LOW-to-HIGH CP transition = High impedance OFF-state = LOW-to-HIGH clock transition
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL PARAMETER DC supply voltage (for max. speed performance) VCC VI VO Tamb tr, tf DC supply voltage (for low-voltage applications) DC Input voltage range DC output voltage range; output HIGH or LOW state DC output voltage range; output 3-State Operating ambient temperature range in free-air Input rise and fall times VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V CONDITIONS MIN 2.7 1.2 0 0 0 -40 0 0 MAX 3.6 V 3.6 5.5 VCC 5.5 +85 20 10 C ns/V V V UNIT
1998 Jul 29
4
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State)
74LVC574A
ABSOLUTE MAXIMUM RATINGS1
In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC IIK VI IOK VO IO IGND, ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC input voltage DC output diode current DC output voltage; output HIGH or LOW state DC output voltage; output 3-State DC output source or sink current DC VCC or GND current Storage temperature range Power dissipation per package - plastic mini-pack (SO) - plastic shrink mini-pack (SSOP and TSSOP) above +70C derate linearly with 8 mW/K above +60C derate linearly with 5.5 mW/K VI t0 Note 2 VO uVCC or VO t 0 Note 2 Note 2 VO = 0 to VCC CONDITIONS RATING -0.5 to +6.5 -50 -0.5 to +6.5 "50 -0.5 to VCC +0.5 -0.5 to 6.5 "50 "100 -65 to +150 500 500 UNIT V mA V mA V mA mA C
mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40C to +85C MIN VIH HIGH level Input voltage VCC = 1.2V VCC = 2.7 to 3.6V LOW level Input voltage VCC = 1.2V VCC = 2.7 to 3.6V VCC = 2.7V; VI = VIH or VIL; IO = -12mA VO OH HIGH level output voltage VCC = 3.0V; VI = VIH or VIL; IO = -100A VCC = 3.0V; VI = VIH or VIL; IO = -18mA VCC = 3.0V; VI = VIH or VIL; IO = -24mA VCC = 2.7V; VI = VIH or VIL; IO = 12mA VOL LOW level output voltage VCC = 3.0V; VI = VIH or VIL; IO = 100A VCC = 3.0V; VI = VIH or VIL; IO = 24mA II IOZ Ioff ICC ICC Input leakage current2 3-State output OFF-state current Power off leakage supply Quiescent supply current Additional quiescent supply current per input pin VCC = 3 6V; VI = 5 5V or GND 3.6V; 5.5V VCC = 3.6V; VI = VIH or VIL; VO = 5.5V or GND VCC = 0.0V; VI or VO = 5.5V VCC = 3.6V; VI = VCC or GND; IO = 0 VCC = 2.7V to 3.6V; VI = VCC -0.6V; IO = 0 "0 1 "0.1 0.1 0.1 0.1 5 GND VCC*0.5 VCC*0.2 VCC*0.6 VCC*0.8 0.40 0.20 0.55 "5 "10 "10 10 500 A A A A A V VCC V VCC 2.0 GND V 0.8 TYP1 MAX V UNIT
VIL
NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25C. 2. The specified overdrive current at the data input forces the data input to the opposite logic input state.
1998 Jul 29
5
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State)
74LVC574A
AC CHARACTERISTICS
GND = 0V; tr = tf v 2.5ns; CL = 50pF; RL = 500; Tamb = -40C to +85C. SYMBOL tPHL tPLH tPZH tPZL tPHZ tPLZ tW tSU th PARAMETER Propagation delay CP to Qn 3-State output enable time OE to Qn 3-State output disable time OE to Qn Clock pulse width HIGH or LOW Setup time Dn to CP Hold time Dn to CP Maximum clock pulse frequency WAVEFORM VCC = 3.3V 0.3V MIN TYP1 MAX 1.5 1.5 1.5 3.4 2.0 1.5 4.8 4.0 3.5 1.7 0.3 -0.2 7.0 7.5 6.0 - - - - LIMITS VCC = 2.7V MIN MAX 1.5 1.5 1.5 3.4 2.0 1.5 80 8.0 8.5 6.5 - - - - VCC = 1.2V TYP 21 17 11 - - - - UNIT
1, 4 2, 4 2, 4 1 3 3
ns ns ns ns ns ns MHz
fmax 1 100 NOTE: 1. Unless otherwise stated, all typical values are at VCC = 3.3V and Tamb = 25C.
AC WAVEFORMS
VM = 1.5V at VCC w 2.7V; VM = 0.5 VCC at VCC t 2.7V. VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3V at VCC w 2.7V; VX = VOL + 0.1 VCC at VCC t 2.7V VY = VOH -0.3V at VCC w 2.7V; VY = VOH - 0.1 VCC at VCC t 2.7V
1/fmax VI CP INPUT
GND
VI nOE INPUT GND VM
tPLZ VCC Qn OUTPUT LOW-to-OFF OFF-to-LOW VX VOL tPLH tPHZ
tPZL
VM tw tPHL VOH
VM
VM
VM
tPZH
Qn OUTPUT VOL
VM
VM
VOH Qn OUTPUT HIGH-to-OFF OFF-to-HIGH VY VM
SA00394
Waveform 1. Clock (CP) to output (Qn) propagation delays, the clock pulse width, output transition times and the maximum clock pulse frequency.
VI CP INPUT GND tsu th VI Dn INPUT tsu th VM
GND outputs enabled outputs disabled
outputs enabled
SW00207
Waveform 3. 3-State enable and disable times.
TEST CIRCUIT
VCC S1 2 x VCC Open GND
VM
PULSE GENERATOR
VI D.U.T. RT
VO
500
GND
VOH Qn OUTPUT
VOL
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
Waveform 2. Data setup and hold times for the Dn input to the CP input.
1998 Jul 29
EEEEEEE EEEE EE EEEEEEE EEEE EE EEEEEEE EEEE EE
VM
CL
50pF
500
Test VCC t 2.7V 2.7V - 3.6V VI VCC 2.7V tPLH/tPHL tPLZ/tPZL tPHZ/tPZH
S1 Open 2 x VCC GND
SW00107
SY00003
Waveform 4. Load circuitry for switching times.
6
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State)
74LVC574A
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
1998 Jul 29
7
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State)
74LVC574A
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
1998 Jul 29
8
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State)
74LVC574A
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
1998 Jul 29
9
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State)
74LVC574A
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 08-98 9397-750-04514
Philips Semiconductors
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