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CXD1172AM/AP
6-bit 20MSPS Video A/D Converter (CMOS)
Description CXD1172AM/AP is a 6-bit CMOS A/D converter for video use. The adoption of a 2-step parallel system achieves low consumption at a maximum conversion speed of 20MSPS minimum, 35MSPS typical. Features * Resolution: 6-bit 1/2LSB * Max. sampling frequency: 20MSPS * Low power consumption: 40mW (at 20MSPS typ.) (Reference current excluded) * Built-in sampling and hold circuit. * 3-state TTL compatible output. * Power supply: 5V single * Low input capacitance: 4pF * Reference impedance: 250 (typ.) Applications TV, VCR digital systems and a wide range of fields where high speed A/D conversion is required. Structure Silicon gate CMOS monolithic IC CXD1172AM 16 pin SOP (Plastic) CXD1172AP 16 pin DIP (Plastic)
Absolute Maximum Ratings (Ta = 25C) 7 V * Supply voltage VDD * Reference voltage VRT, VRB VDD + 0.5 to VSS - 0.5 V * Input voltage VIN VDD + 0.5 to VSS - 0.5 V (Analog) * Input voltage VCLK VDD + 0.5 to VSS - 0.5 V (Digital) * Output voltage VOH, VOL VDD + 0.5 to VSS - 0.5 V (Digital) * Storage temperature Tstg -55 to +150 C Recommended Operating Conditions * Supply voltage AVDD, AVSS 4.75 to 5.25 V DVDD, DVSS 4.75 to 5.25 V * Reference input voltage VRB 0 to 4.1 V VRT 0.9 to 5.0 V VRT - VRB 0.9 to AVDD V * Analog input voltage VIN VRB to VRT V * Clock pulse width TPW1, TPW0 23ns (min.) to 1.1s (max.) * Operating temperature Topr -20 to +75 C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E89320C78-PS
CXD1172AM/AP
Block Diagram and Pin Configuration
Reference voltage
D0 1 D1 2 D2 3 Lower Sampling comparators (3BIT)
16 AVSS 15 DVDD 14 AVDD 13 VRB
Lower data latchs
Lower encoder (3BIT)
D3 4 D4 5 D5 6 CLK 7 DVSS 8
Lower encoder (3BIT) Upper data latchs Upper encoder (3BIT)
Lower Sampling comparators (3BIT)
12 VIN 11 VRT 10 AVDD 9 DVDD
Upper Sampling comparators (3BIT)
Clook generator
Pln Description and Equivalent Circuits No. Symbol Equivalent Circuit Description
Di
1 to 6
D0 to D5
D0 (LSB) to D5 (MSB) output
DVDD
7
CLK
7 DVSS
Clock input
8 9, 15 10, 14 11
DVSS DVDD AVDD VRT
11 AVDD
Digital GND Digital +5V Analog +5V Reference voltage (Top)
13
13
VRB
AVDD
AVSS
Reference voltage (Bottom)
12
VIN
12
Analog input
AVSS
16
AVSS -2-
Analog GND
CXD1172AM/AP
Digital Output Compatibility between Analog input voltage and the digital output code is indicated in the chart below. Input signal voltage VRT Digital output code MSB LSB 111111 100000 011111 000000
TPW0
Step 0
..............
...
31 32
...
VRB
63
TPW1
Clock
Analog input
N
...
N+1
...
N+2
N+3
N+4
Data output
N-3
N-2
N-1
N
N+1
Td = 18ns
: Point for analog signal sampling.
Timing Chart 1
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CXD1172AM/AP
Electrical Characteristics Item Symbol
(VDD = 5V, VRB = 1.0V, VRT = 2.0V, Ta = 25C) Conditions VDD = 4.75 to 5.25V Ta = -20 to +75C VIN = 1.0 to 2.0V fIN = 1kHz ramp Fc = 20MSPS NTSC ramp wave input 3 Envelope VIN = 1.5V + 0.07Vrms 175 Potential difference to VRT Potential difference to VRB VDD = 4.75 to 5.25V Ta = -20 to +75C VIH = VDD VDD = max. VIL = 0V VOH = VDD + 0.5V VDD = min. VOL = 0.4V -1.1 3.7 18 0.3 End point 0.3 NTSC 40 IRE mod ramp Fc = 14.3MSPS 1.0 1.0 40 4 30 0.5 LSB 0.5 % deg ps ns ns 0 15 4.0 1.0 5 5 mA A Min. Typ. Max. Unit
Conversion speed
Fc
0.5
20
MSPS
Supply current Reference pin current Analog input band width (-1dB) Analog input capacitance Reference resistance (VRT to VRB) Offset voltage1
IDD IREF BW CIN RREF EOT EOB VIH VIL IIH IIL IOH IOL TDL
7 4 18 4 250 -20 35
12 mA 5.7 MHz pF 325 -40 55 V mV
Digital input voltage
Digital input current
Digital output current
Output data delay
With TTL 1 gate and 10pF load Ta = -20 to +75C VDD = 4.75 to 5.25V
Integral non-linearity error Differential non-linearity error Differential gain error Differential phase error Aperture jitter Sampling delay
EL ED DG DP Taj Tsd
1 The offset voltage EOB is a potential difference between VRB and a point of position where the voltage drops equivalent to 1/2 LSB of the voltage when the output data changes from "00000000" to "00000001". EOT is a potential difference between VRT and a potential of point where the voltage rises equivalent to 1/2 LSB of the voltage when the output data changes from "11111111" to "11111110".
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CXD1172AM/AP
Electrical Characteristics Test Circuit Integral non-linearity error Differential non-linearity Offset voltage
+V
}
S2 S1
Test Circuit
S1 : ON IF A < B S2 : ON IF B > A
-V AB COMPARATOR A6 B6 to to A1 B1 B0 A0
VIN
CXD1172A
6
6
BUFFER
"0" DVM CLK (20MHz)
"1" 6 000 ... 00 to 111 ... 0
CONTROLLER
Maximum operational speed Differential gain error Differential phase error
}
AMP
Test Circuit
2.0V FC - 1kHz S. G. 1 2 NTSC SIGNAL SOURCE 100 40 IRE MODULATION BURST 1.0V 620 TTL FC -5.2V ECL 2.0V -5.2V CLK 1.0V VIN CXD 1172A 6 TTL ECL 6 620 10bit D/A 2 VECTOR SCOPE D. G D. P CX20202A-1 1
ERROR RATE
H. P. F
COUNTER
IAE
0 -40
SYNC
S. G. (CW)
Digital output current test circuit
2.0V 1.0V
VRT VIN VRB
VCC IOL
2.0V 1.0V
VRT VIN VRB
VCC IOH
CLK GND
VOL
+ -
CLK GND
VOH
+ -
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CXD1172AM/AP
Timing Chart 2
Vi (1) Vi (2) Vi (3) Vi (4)
Analog input
External clock
Upper comparators block
S (1)
C (1)
S (2)
C (2)
S (3)
C (3)
S (4)
C (4)
Upper data
MD (0)
MD (1)
MD (2)
MD (3)
Lower reference voltage
RV (0)
RV (1)
RV (2)
RV (3)
Lower comparators A block
S (1)
H (1)
C (1)
S (3)
H (3)
C (3)
Lower data A
LD (-1)
LD (1)
Lower comparators B block
H (0)
C (0)
S (2)
H (2)
C (2)
S (4)
H (4)
Lower data B
LD (-2)
LD (0)
LD (2)
Digital output
Out (-2)
Out (-1)
Out (0)
Out (1)
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CXD1172AM/AP
Operation (See Block Diagram and Timing Chart) 1. CXD1172AM/AP is a 2-step parallel system A/D converter featuring a 3-bit upper comparators group and 2 Iower comparators groups of 3-bit each. The reference voltage that is equal to the voltage between VRTVRB/8 is constantly applied to the upper 3-bit comparator block. Voltage that corresponded to the upper data is fed through the reference supply to the lower data. 2. This IC uses an offset cancel type comparator and operates synchronously with an external clock. It features the following operating modes which are respectively indicated on the timing chart with S, H, C symbols. That is input sampling (auto zero) mode, input hold mode and comparison mode. 3. The operation of respective parts is as indicated in the chart. For instance input voltage Vi (1) is sampled with the falling edge of the first clock by means of the upper comparator block and the Iower comparator A block. The upper comparators block finalizes comparison data MD (1) with the rising edge of the first clock. Simultaneously the reference supply generates the lower reference voltage RV (1) that corresponded to the upper results. The lower comparator block finalizes comparison data LD (1) with the rising edge of the second clock. MD (1) and LD (1) are combined and output as Out (1) with the rising edge of the 3rd clock. Accordingly there is a 2.5 clock delay from the analog input sampling point to the digital data output. Operation Notes 1. VDD, Vss To reduce noise effects, separate the analog and digital systems close to the device. For both the digital and analog VDD pins, use a ceramic capacitor of about 0.1F set as close as possible to the pin to bypass to the respective GND's. 2. Analog input Compared with the flash type A/D converter, the input capacitance of the analog input is rather small. However it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability. When driving with an amplifier of low output impedance, parasite oscillation may occur. That may be prevented by inserting a resistance of about 100 in series between the amplifier output and A/D input. 3. Clock input The clock line wiring should be as short as possible also, to avoid any interference with other signals, separate it from other circuits. 4. Reference input Voltage between VRT to VRB is compatible with the dynamic range of the analog input. Bypassing VRT and VRB pins to GND, by means of a capacitor about 0.1F, stable characteristics are obtained. 5. Timing Analog input is sampled with the falling edge of CLK and output as digital data with a delay of 2.5 clocks and with the following rising edge. The delay from the clock rising edge to the data output is about 18ns. 6. About latch up It is necessary that AVDD and DVDD pins be the common source of power supply. This is to avoid latch up due to the voltage difference between AVDD and DVDD pins when power is ON. See "For latch up prevention" of CXD1172P/CXA1106P PCB description. (Page 6, 7) -7-
CXD1172AM/AP
Latch Up Prevention The CXD1172A is a CMOS IC which requires latch up precautions. Latch up is mainly generated by the lag in the voltage rising time of AVDD (Pins 10 and 14) and DVDD (Pins 9 and 15), when power supply is ON. 1. Correct usage a. When analog and digital supplies are from different sources
DVDD AVDD
10
14
9
15 C14
AVDD +5V +5V C6 CXD1172A
DVDD DIGITAL IC
AVSS 16 AVSS
DVSS 8 DVSS
b. When analog and digital supplies are from a common source (i)
DVDD
10
14
9
15 C14
AVDD +5V C6 CXD1172A
DVDD DIGITAL IC
AVSS 16 AVSS
DVSS 8 DVSS
(ii)
DVDD
10
14
9
15 C14
AVDD +5V C6 AVSS 16 AVSS DVSS CXD1172A
DVDD DIGITAL IC
DVSS 8
-8-
CXD1172AM/AP
2. Example when latch up easily occurs a. When analog and digital supplies are from different sources
DVDD AVDD 10 14 9 15
AVDD +5V +5V C6 CXD1172A
DVDD DIGITAL IC
AVSS AVSS 16
DVSS 8 DVSS
b. When analog and digital supplies are from common source (i)
DVDD AVDD 10 14 9 15
AVDD +5V C6 CXD1172A
DVDD DIGITAL IC
AVSS AVSS 16
DVSS 8 DVSS
(ii)
DVDD AVDD 10 14 9 15
AVDD +5V CXD1172A
DVDD DIGITAL IC
AVSS 16 AVSS
DVSS 8 DVSS
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CXD1172AM/AP
6-bit, 20MSPS ADC and DAC Evaluation Board Silk Side
Analog
VR5 C8
C9 CLK 74S174 C10 DA OUT A1106P D6 D4 D2 D7 D5 D3 D1 D0
D6 D7
Logic
VR3 C2 Q4 S IN VR1 R2 R1 C3 Q1 R3 Q2 C1 R4 R5 VR2
R9
R10 VR4
C7 R7 C6 Q3 C4 R6 R8
D1172P
AGND
Analog
A.GND C11 C12
C13 SW R11 D.GND CLK IN
Component Side
2 1
Soldering Side
3
- 10 -
OSC
C14
74HC04
74S174
Q5 C5
D0 D1 D2 D3 D4 D5
CLK DVDD AVDD GND +5V -5V
CXD1172AM/AP
Package Outline CXD1172AM
Unit: mm
16PIN SOP (PLASTIC) 300mil
+ 0.4 9.9 - 0.1
+ 0.4 1.85 - 0.15
16
9 0.15 + 0.2 0.1 - 0.05
+ 0.3 5.3 - 0.1
7.9 0.4
0.45 0.1
1.27
+ 0.1 0.2 - 0.05
0.12 M
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE PACKAGE WEIGHT SOP-16P-L01 SOP016-P-0300-A LEAD TREATMENT LEAD MATERIAL EPOXY RESIN SOLDER PLATING COPPER ALLOY
0.2g
CXD1172AP
16PIN DIP (PLASTIC)
+ 0.1 0.05 0.25 -
0 to 15
EPOXY RESIN SOLDER PLATING COPPER ALLOY 1.0 g
16
9
1 2.54
8
+ 0.4 3.7 - 0.1
0.5 MIN
0.5 0.1 1.2 0.15
3.0 MIN
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE DIP-16P-01 DIP016-P-0300 Similar to MO-001-AE LEAD TREATMENT LEAD MATERIAL PACKAGE MASS
- 11 -
7.62
Two kinds of package surface: 1.All mat surface type. 2.All mirror surface type.
+ 0.3 6.4 - 0.1
+ 0.4 19.2 - 0.1
0.5 0.2
1
8
6.9

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