 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT4515 4-to-16 line decoder/demultiplexer with input latches; inverting Product specification File under Integrated Circuits, IC06 September 1993 Philips Semiconductors Product specification 4-to-16 line decoder/demultiplexer with input latches; inverting FEATURES * Inverting outputs * Output capability: standard * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT4515 are high-speed Si-gate CMOS devices and are pin compatible with "4515" of the "4000B" series. They are specified in compliance with JEDEC standard no. 7A. 74HC/HCT4515 The 74HC/HCT4515 are 4-to-16 line decoders/demultiplexers having four binary weighted address inputs (A0 to A3) with latches, a latch enable input (LE), and an active LOW enable input (E). The 16 inverting outputs (Q0 to Q15) are mutually exclusive active LOW. When LE is HIGH, the selected output is determined by the data on An. When LE goes LOW, the last data present at An are stored in the latches and the outputs remain stable. When E is LOW, the selected output, determined by the contents of the latch, is LOW. When E is HIGH, all outputs are HIGH. The enable input (E) does not affect the state of the latch. When the "4515" is used as a demultiplexer, E is the data input and A0 to A3 are the address inputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". PARAMETER propagation delay An to Qn input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 25 3.5 44 HCT 26 3.5 46 ns pF pF UNIT September 1993 2 Philips Semiconductors Product specification 4-to-16 line decoder/demultiplexer with input latches; inverting PIN DESCRIPTION PIN NO. 1 2, 3, 21, 22 12 23 24 SYMBOL LE A0 to A3 GND E VCC 74HC/HCT4515 NAME AND FUNCTION latch enable input (active HIGH) address inputs multiplexer outputs (active LOW) ground (0 V) enable input (active LOW) positive supply voltage 11, 9, 10, 8, 7, 6, 5, 4,18, 17, 20, 19, 14, 13, 16, 15 Q0 to Q15 Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. September 1993 3 Philips Semiconductors Product specification 4-to-16 line decoder/demultiplexer with input latches; inverting 74HC/HCT4515 APPLICATIONS * Digital multiplexing * Address decoding * Hexadecimal/BCD decoding Fig.4 Functional diagram. FUNCTION TABLE INPUTS E H L L L L L L L L L L L L L L L L Notes 1. LE = HIGH H = HIGH voltage level L = LOW voltage level X = don't care A0 X L H L H L H L H L H L H L H L H A1 X L L H H L L H H L L H H L L H H A2 X L L L L H H H H L L L L H H H H A3 X L L L L L L L L H H H H H H H H Q0 H L H H H H H H H H H H H H H H H Q1 H H L H H H H H H H H H H H H H H Q2 H H H L H H H H H H H H H H H H H Q3 H H H H L H H H H H H H H H H H H Q4 H H H H H L H H H H H H H H H H H Q5 H H H H H H L H H H H H H H H H H Q6 H H H H H H H L H H H H H H H H H OUTPUTS Q7 H H H H H H H H L H H H H H H H H Q8 H H H H H H H H H L H H H H H H H Q9 H H H H H H H H H H L H H H H H H Q10 Q11 Q12 Q13 Q14 Q15 H H H H H H H H H H H L H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H L September 1993 4 Philips Semiconductors Product specification 4-to-16 line decoder/demultiplexer with input latches; inverting 74HC/HCT4515 Fig.5 Logic diagram. September 1993 5 Philips Semiconductors Product specification 4-to-16 line decoder/demultiplexer with input latches; inverting DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 min. tPHL/ tPLH propagation delay An to Qn propagation delay LE to Qn propagation delay E to Qn output transition time typ. 80 29 23 66 24 19 50 18 14 19 7 6 14 5 4 28 10 8 -11 -4 -3 max. 250 50 43 225 45 38 175 35 30 75 15 13 95 19 16 115 23 20 0 0 0 -40 to +85 min. max. 315 63 54 280 56 48 220 44 37 95 19 16 110 22 19 135 27 23 0 0 0 -40 to +125 min. max. 375 75 64 340 68 58 265 53 45 110 22 19 ns 74HC/HCT4515 TEST CONDITIONS UNIT V WAVEFORMS CC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.6 tPHL/ tPLH ns Fig.6 tPHL/ tPLH ns Fig.6 tTHL/ tTLH ns Fig.6 tW latch enable pulse width 75 HIGH 15 13 set-up time An to LE hold time An to LE 90 18 15 0 0 0 ns Fig.7 tsu ns Fig.7 th ns Fig.7 September 1993 6 Philips Semiconductors Product specification 4-to-16 line decoder/demultiplexer with input latches; inverting DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI 74HC/HCT4515 Note to HCT types The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT An LE E UNIT LOAD COEFFICIENT 0.65 1.40 1.00 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER +25 min. typ. tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tTHL/ tTLH tW tsu th propagation delay An to Qn propagation delay LE to Qn propagation delay E to Qn output transition time latch enable pulse width HIGH set-up time An to LE hold time An to LE 16 18 3 30 29 18 7 3 9 -2 max. 55 50 40 15 20 23 3 -40 to+85 min. max. 69 63 50 19 24 27 3 -40 to +125 min. max. 83 75 60 22 ns ns ns ns ns ns ns 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Fig.6 Fig.6 Fig.6 Fig.6 Fig.7 Fig.7 Fig.7 UNIT V WAVEFORMS CC (V) TEST CONDITIONS September 1993 7 Philips Semiconductors Product specification 4-to-16 line decoder/demultiplexer with input latches; inverting AC WAVEFORMS 74HC/HCT4515 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the input (An, LE, E) to output (Qn) propagation delays and the output transition times. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the minimum pulse width of the latch enable input (LE) and the set-up and hold times for LE to An. Set-up and hold times are shown as positive values but may be specified as negative values. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". September 1993 8 |
Price & Availability of 74HCT4515
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |