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INTEGRATED CIRCUITS
DATA SHEET
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* The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4316 Quad bilateral switches
Product specification File under Integrated Circuits, IC06 September 1993
Philips Semiconductors
Product specification
Quad bilateral switches
FEATURES * Low "ON" resistance: 160 (typ.) at VCC - VEE = 4.5 V 120 (typ.) at VCC - VEE = 6.0 V 80 (typ.) at VCC - VEE = 9.0 V * Logic level translation: to enable 5 V logic to communicate with 5 V analog signals * Typical "break before make" built in * Output capability: non-standard * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT4316 are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no. 7A.
74HC/HCT4316
The 74HC/HCT4316 have four independent analog switches. Each switch has two input/output terminals (nY, nZ) and an active HIGH select input (nS). When the enable input (E) is HIGH, all four analog switches are turned off. Current through a switch will not cause additional VCC current provided the voltage at the terminals of the switch is maintained within the supply voltage range; VCC >> (VY, VZ) >> VEE. Inputs nY and nZ are electrically equivalent terminals. VCC and GND are the supply voltage pins for the digital control inputs (E and nS). The VCC to GND ranges are 2.0 to 10.0 V for HC and 4.5 to 5.5 V for HCT. The analog inputs/outputs (nY and nZ) can swing between VCC as a positive limit and VEE as a negative limit. VCC - VEE may not exceed 10.0 V. See the "4016" for the version without logic level translation.
QUICK REFERENCE DATA VEE = GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL tPZH turn "ON" time E to VOS nS to VOS tPZL turn "ON" time E to VOS nS to VOS tPHZ/ tPLZ turn "OFF" time E to VOS nS to VOS CI CPD CS Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x where: VCC2 x fi + { (CL + CS) x VCC2 x fo } CL = output load capacitance in pF CS = max. switch capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V input capacitance power dissipation capacitance per switch max. switch capacitance notes 1 and 2 20 16 3.5 13 5 21 19 3.5 14 5 ns ns pF pF pF 19 16 24 21 ns ns PARAMETER CONDITIONS HC CL = 15 pF; RL = 1 k; VCC = 5 V 19 16 19 17 HCT ns ns UNIT
fi = input frequency in MHz fo = output frequency in MHz { (CL + CS) x VCC2 x fo } = sum of outputs
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Philips Semiconductors
Product specification
Quad bilateral switches
ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". PIN DESCRIPTION PIN NO. 1, 4, 10, 13 2, 3, 11, 12 7 8 9 15, 5, 6, 14 16 SYMBOL 1Z to 4Z 1Y to 4Y E GND VEE 1S to 4S VCC NAME AND FUNCTION independent inputs/outputs independent inputs/outputs enable input (active LOW) ground (0 V) negative supply voltage select inputs (active HIGH) positive supply voltage
74HC/HCT4316
(b)
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
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Philips Semiconductors
Product specification
Quad bilateral switches
FUNCTION TABLE INPUTS SWITCH E L L H Note 1. H = HIGH voltage level L = LOW voltage level X = don't care APPLICATIONS * Signal gating * Modulation * Demodulation * Chopper nS L H X off on off
74HC/HCT4316
Fig.4 Functional diagram.
Fig.5 Schematic diagram (one switch).
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Philips Semiconductors
Product specification
Quad bilateral switches
RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Voltages are referenced to VEE = GND (ground = 0 V) SYMBOL VCC IIK ISK IS IEE ICC; IGND Tstg Ptot PARAMETER DC supply voltage DC digital input diode current DC switch diode current DC switch current DC VEE current DC VCC or GND current storage temperature range power dissipation per package plastic DIL plastic mini-pack (SO) PS power dissipation per switch 750 500 100 mW mW mW -65 MIN. -0.5 MAX. +11.0 20 20 25 20 50 +150 UNIT V mA mA mA mA mA C
74HC/HCT4316
CONDITIONS for VI < -0.5 V or VI > VCC + 0.5 V for VS < -0.5 V or VS > VCC + 0.5 V for -0.5 V < VS < VCC + 0.5 V
for temperature range: -40 to +125 C 74HC/HCT above +70 C: derate linearly with 12 mW/K above +70 C: derate linearly with 8 mW/K
Note to ratings To avoid drawing VCC current out of terminal Z, when switch current flows in terminals Yn, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminals Z, no VCC current will flow out of terminal Yn. In this case there is no limit for the voltage drop across the switch, but the voltages at Yn and Z may not exceed VCC or VEE. RECOMMENDED OPERATING CONDITIONS 74HC
SYMBOL PARAMETER
74HCT
UNIT
CONDITIONS see Figs 6 and 7 see Figs 6 and 7
min. typ. max. min. typ. max. VCC VCC VI VS Tamb Tamb tr, tf DC supply voltage VCC-GND DC supply voltage VCC-VEE DC input voltage range DC switch voltage range 2.0 2.0 GND VEE 5.0 5.0 10.0 10.0 VCC VCC +85 1000 500 400 250 4.5 2.0 GND VEE -40 5.0 5.0 5.5 10.0 VCC VCC +85 V V V V C ns 6.0 500 see DC and AC CHARACTERISTICS VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 10.0 V
operating ambient temperature range -40 operating ambient temperature range -40 input rise and fall times 6.0
+125 -40
+125 C
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Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4316
Fig.6 Guaranteed operating area as a function of the supply voltages for 74HC4316.
Fig.7 Guaranteed operating area as a function of the supply voltages for 74HCT4316.
DC CHARACTERISTICS FOR 74HC/HCT For 74HC: VCC - GND or VCC - VEE = 2.0, 4.5, 6.0 and 9.0 V For 74HCT: VCC - GND = 4.5 and 5.5 V; VCC - VEE = 2.0, 4.5, 6.0 and 9.0 V Tamb (C) 74HC/HCT SYMBOL PARAMETER min. RON
ON resistance (peak)
TEST CONDITIONS UNIT VCC (V) VEE (V) IS (A) Vis VI
+25 typ. - 160 120 85 160 80 70 60 170 90 80 65 - 16 9 6 max. - 320 240 170 - 160 140 120 - 180 160 135
-40 to +85 min. max. - 400 300 215 - 200 175 150 - 225 200 170
-40 to +125 min. max. - 480 360 255 - 240 210 180 - 270 240 205

2.0 4.5 6.0 4.5 2.0 4.5 6.0 4.5 2.0 4.5 6.0 4.5 2.0 4.5 6.0 4.5
0 0 0 -4.5 0 0 0 -4.5 0 0 0 -4.5 0 0 0 -4.5
100 VCC VIH 1000 to or 1000 VEE VIL 1000 100 VEE VIH or 1000 1000 VIL 1000 100 VCC VIH 1000 or 1000 VIL 1000
VCC VH to or VEE VIL
RON
ON resistance (rail)
RON
ON resistance (rail)
RON
maximum ON resistance between any two channels
Notes 1. At supply voltages (VCC - VEE) approaching 2.0 V the analog switch ON-resistance becomes extremely non-linear. Therefore it is recommended that these devices are used to transmit digital signals only, when using these supply voltages. 2. For test circuit measuring RON see Fig.8. September 1993 6
Philips Semiconductors
Product specification
Quad bilateral switches
DC CHARACTERISTICS FOR 74HC Voltages are referenced to GND (ground = 0 V) Tamb (C) 74HC SYMBOL PARAMETER +25 min. typ. max. VIH
HIGH level input voltage
74HC/HCT4316
TEST CONDITIONS UNIT VCC VEE (V) (V) VI OTHER
-40 to +85 min. 1.5 3.15 4.2 6.3 0.5 1.35 1.8 2.7 0.1 0.2 0.1 0.5 1.35 1.8 2.7 1.0 2.0 1.0 max.
-40 to +125 min.
1.5 3.15 4.2 6.3 0.5 1.35 1.8 2.7
max. V 2.0 4.5 6.0 9.0 2.0 4.5 6.0 9.0
6.0 10.0 10.0
1.5 3.15 4.2 6.3
1.2 2.4 3.2 4.3 0.8 2.1 2.8 4.3
VIL
LOW level input voltage
V
II
input leakage
current
1.0 2.0 1.0
A
0 0 0
VCC or GND VIH or VIL VIH or VIL VCC or GND VS = VCC - VEE (see Fig.10) VS = VCC - VEE (see Fig.11) Vis = VEE or VCC; VOS = VCC or VEE
IS
analog switch OFF-state current analog switch ON-state current quiescent supply current
A
IS
0.1
1.0
1.0
A
10.0
0
ICC
8.0 16.0
80.0 160.0
160.0 320.0
A
6.0 10.0
0 0
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Philips Semiconductors
Product specification
Quad bilateral switches
AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 -40 to +85 -40 to +125 min. max. 90 18 15 12 310 62 53 56 265 53 45 51 330 66 56 59 265 53 45 54 ns 2.0 4.5 6.0 4.5 2.0 4.5 6.0 4.5 2.0 4.5 6.0 4.5 2.0 4.5 6.0 4.5 2.0 4.5 6.0 4.5 UNIT VCC (V)
74HC/HCT4316
TEST CONDITIONS VEE (V) OTHER
min. typ. max. min. max. tPHL/ tPLH propagation delay Vis to Vos turn "ON" time E to Vos 17 6 5 4 61 22 18 19 52 19 15 17 63 23 18 21 55 20 16 18 60 12 10 8 205 41 35 37 175 35 30 34 220 44 37 39 175 35 30 36 75 15 13 10 255 51 43 47 220 44 37 43 275 55 47 49 220 44 37 45
0 RL = ; CL = 50 pF 0 (see Fig.18) 0 -4.5 0 0 0 -4.5 0 0 0 -4.5 0 0 0 -4.5 0 0 0 -4.5 RL = 1 k; CL = 50 pF (see Figs 19, 20 and 21) RL = 1 k; CL = 50 pF (see Figs 19, 20 and 21) RL = 1 k; CL = 50 pF (see Figs 19, 20 and 21) RL = 1 k; CL = 50 pF (see Figs 19, 20 and 21)
tPZH/ tPZL
ns
tPZH/ tPZL
turn "ON" time nS to Vos
ns
tPHZ/ tPLZ
turn "OFF" time E to Vos turn "OFF" time nS to Vos
ns
tPHZ/ tPLZ
ns
September 1993
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Philips Semiconductors
Product specification
Quad bilateral switches
DC CHARACTERISTICS FOR 74HCT Voltages are referenced to GND (ground = 0) Tamb (C) 74HCT SYMBOL PARAMETER min. VIH HIGH level input voltage LOW level input voltage input leakage current analog switch OFF-state current analog switch ON-state current quiescent supply current 2.0 +25 typ. 1.6 -40 to +85 -40 to +125 UNIT VCC (V)
74HC/HCT4316
TEST CONDITIONS VEE (V) VI OTHER
max. min. max. min. max. 2.0 2.0 V 4.5 to 5.5 4.5 to 5.5 5.5 0
VCC or GND
VIL
1.2
0.8
0.8
0.8
V
II
0.1
1.0
1.0
A
IS
0.1
1.0
1.0
A
10.0 0
VIH or VIL VIH or VIL
VS = VCC - VEE (see Fig.10) VS = VCC - VEE (see Fig.11) Vis = VEE or VCC; VOS = VCC or VEE
IS
0.1
1.0
1.0
A
10.0 0
ICC
8.0 16.0
80.0 160.0
160.0 320.0
A
5.5 5.0
0 VCC -5.0 or
GND
ICC
additional quiescent supply current per input pin for unit load coefficient is 1 (note 1)
100
360
450
490
A
4.5 to 5.5
0
VCC other inputs -2.1 V at VCC or GND
Note 1. The value of additional quiescent supply current (ICC) for a unit load of 1 is given here. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT nS E UNIT LOAD COEFFICIENT 0.50 0.50
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Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4316
Fig.8 Test circuit for measuring RON.
Fig.9 Typical RON as a function of input voltage Vis for Vis = 0 to VCC - VEE.
Fig.10 Test circuit for measuring OFF-state current.
Fig.11 Test circuit for measuring ON-state current.
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Philips Semiconductors
Product specification
Quad bilateral switches
AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER +25 -40 TO +85 -40 to +125 min. max. 18 12 66 63 84 63 60 51 75 51 75 69 ns 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 UNIT
74HC/HCT4316
TEST CONDITIONS VCC (V) VEE (V) OTHER
min. typ. max. min. max. tPHL/ tPLH propagation delay Vis to Vos turn "ON" time E to Vos turn "ON" time E to Vos turn "ON" time nS to Vos turn "ON" time nS to Vos turn "OFF" time E to Vos 6 4 22 21 28 21 20 17 25 17 25 23 12 8 44 42 56 42 40 34 50 34 50 46 15 10 55 53 70 53 53 43 63 43 63 58
0 RL = ; -4.5 CL = 50 pF (see Fig.18) 0 RL = 1 k; -4.5 CL = 50 pF (see Figs 19, 0 -4.5 20 and 21) 0 RL = 1 k; -4.5 CL = 50 pF (see Figs 19, 0 -4.5 20 and 21) 0 RL = 1 k; -4.5 CL = 50 pF (see Figs 19, 20 and 21) 0 RL = 1 k; -4.5 CL = 50 pF (see Figs 19, 20 and 21)
tPZH tPZL tPZH tPZL tPHZ/ tPLZ
ns ns ns ns ns
tPHZ/ tPLZ
turn "OFF" time nS to Vos
22 20
44 40
55 50
66 60
ns
4.5 4.5
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Philips Semiconductors
Product specification
Quad bilateral switches
ADDITIONAL AC CHARACTERISTICS FOR 74HC/HCT Recommended conditions and typical values GND = 0 V; Tamb = 25 C SYMBOL PARAMETER sine-wave distortion f = 1 kHz sine-wave distortion f = 10 kHz switch "OFF" signal feed-through crosstalk between any two switches V(p-p) crosstalk voltage between control and any switch (peak-to-peak value) typ. 0.80 0.40 2.40 1.20 -50 -50 -60 -60 110 220 UNIT % % % % dB dB dB dB mV mV VCC (V) 2.25 4.5 2.25 4.5 2.25 4.5 2.25 4.5 4.5 4.5 VEE (V) -2.25 -4.5 -2.25 -4.5 -2.25 -4.5 -2.25 -4.5 0 -4.5 Vis(p-p) (V) 4.0 8.0 4.0 8.0 note 1 note 1
74HC/HCT4316
CONDITIONS RL = 10 k; CL = 50 pF (see Fig.14) RL = 10 k; CL = 50 pF (see Fig.14) RL = 600 ; CL = 50 pF f = 1 MHz (see Figs 12 and 15) RL = 600 ; CL = 50 pF; f = 1 MHz; (see Fig.16) RL = 600 k; CL = 50 pF; f = 1 MHz (E or nS, square-wave between VCC and GND, tr = tf = 6 ns) (see Fig.17)
fmax CS Notes
minimum frequency response (-3 dB) maximum switch capacitance
150 160 5
MHz MHz pF
2.25 4.5
-2.25 -4.5
note 2
RL = 50 ; CL = 10 pF (see Figs 13 and 14)
1. Adjust input voltage Vis to 0 dBm level (0 dBm = 1 mW into 600 ). 2. Adjust input voltage Vis to 0 dBm level at VOS for 1 MHz (0 dBm = 1 mW into 50 ).
General note
Vis is the input voltage at an nY or nZ terminal, whichever is assigned as an input. Vos is the output voltage at an nY or nZ terminal, whichever is assigned as an output.
Test conditions: VCC = 4.5 V; GND = 0 V; VEE = -4.5 V; RL = 50 ; Rsource = 1 k.
Fig.12 Typical switch "OFF" signal feed-through as a function of frequency.
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Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4316
Test conditions: VCC = 4.5 V; GND = 0 V; VEE = -4.5 V; RL = 50 ; Rsource = 1 k.
Fig.13 Typical frequency response.
Fig.14 Test circuit for measuring sine-wave distortion and minimum frequency response.
Fig.15 Test circuit for measuring switch "OFF" signal feed-through.
Fig.16 Test circuit for measuring crosstalk between any two switches. (a) channel ON condition; (b) channel OFF condition.
The crosstalk is defined as follows (oscilloscope output):
Fig.17 Test circuit for measuring crosstalk between control and any switch.
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Philips Semiconductors
Product specification
Quad bilateral switches
AC WAVEFORMS
74HC/HCT4316
Fig.18 Waveforms showing the input (Vis) to output (Vos) propagation delays.
(1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.19 Waveforms showing the turn-ON and turn-OFF times.
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Philips Semiconductors
Product specification
Quad bilateral switches
TEST CIRCUIT AND WAVEFORMS
74HC/HCT4316
Fig.20 Test circuit for measuring AC performance.
Fig.21 Input pulse definitions.
Conditions TEST tPZH tPZL tPHZ tPLZ others SWITCH VEE VCC VEE VCC open Vis VCC VEE VCC VEE pulse tr; tf FAMILY 74HC 74HCT AMPLITUDE VCC 3.0 V VM 50% 1.3 V fmax; PULSE WIDTH < 2 ns < 2 ns OTHER 6 ns 6 ns
Definitions for Figs 20 and 21: CL = load capacitance including jig and probe capacitance (see AC CHARACTERISTICS for values). RT = termination resistance should be equal to the output impedance ZO of the pulse generator. tr = tf = 6 ns; when measuring fmax, there is no constraint to tr, tf with 50% duty factor. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines".
September 1993
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