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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
* The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT259 8-bit addressable latch
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
8-bit addressable latch
FEATURES * Combines demultiplexer and 8-bit latch * Serial-to-parallel capability * Output from each storage bit available * Random (addressable) data entry * Easily expandable * Common reset input * Useful as a 3-to-8 active HIGH decoder * Output capability: standard * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT259 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT259 are high-speed 8-bit addressable latches designed for general purpose storage applications in digital systems. The "259" are multifunctional devices
74HC/HCT259
capable of storing single-line data in eight addressable latches, and also 3-to-8 decoder and demultiplexer, with active HIGH outputs (Q0 to Q7), functions are available. The "259" also incorporates an active LOW common reset (MR) for resetting all latches, as well as, an active LOW enable input (LE). The "259" has four modes of operation as shown in the mode select table. In the addressable latch mode, data on the data line (D) is written into the addressed latch. The addressed latch will follow the data input with all non-addressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the state of the D input with all other outputs in the LOW state. In the reset mode all outputs are LOW and unaffected by the address (A0 to A2) and data (D) input. When operating the "259" as an addressable latch, changing more than one bit of address could impose a transient-wrong address. Therefore, this should only be done while in the memory mode. The mode select table summarizes the operations of the "259".
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay D to Qn An, LE to Qn tPHL CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V MR to Qn input capacitance power dissipation capacitance per latch notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 18 17 15 3.5 19 20 20 20 3.5 19 ns ns ns pF pF HCT UNIT
December 1990
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Philips Semiconductors
Product specification
8-bit addressable latch
ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". PIN DESCRIPTION PIN NO. 1, 2, 3 4, 5, 6, 7, 9 10, 11, 12 8 13 14 15 16 SYMBOL A0 to A2 Q0 to Q7 GND D LE MR VCC NAME AND FUNCTION address inputs latch outputs ground (0 V) data input latch enable input (active LOW) conditional reset input (active LOW) positive supply voltage
74HC/HCT259
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
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Philips Semiconductors
Product specification
8-bit addressable latch
74HC/HCT259
Fig.4 Functional diagram.
MODE SELECT TABLE LE L H L H MR H H L L MODE addressable latch memory active HIGH 8-channel demultiplexer reset
December 1990
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Philips Semiconductors
Product specification
8-bit addressable latch
FUNCTION TABLE OPERATING MODES master reset INPUTS MR L L L L L L L L L H H H H H addressable latch H H H H Notes L L L L d d d d L H L H L L H H H H H H q0 q0 q0 q0 q1 q1 q1 q1 q2 q2 q2 q2 q3 q3 q3 q3 LE H L L L L L L L L H L L L L X d d d d d d d d X d d d d D A0 X L H L H L H L H X L H L H A1 X L L H H L L H H X L L H H A2 X L L L L H H H H X L L L L L Q=d L L L L L L L q0 Q=d q0 q0 q0 Q0 L L Q=d L L L L L L q1 q1 Q=d q1 q1 Q1 L L L Q=d L L L L L q2 q2 q2 Q=d q2 Q2 L L L L Q=d L L L L q3 q3 q3 q3 Q=d
74HC/HCT259
OUTPUTS Q3 L L L L L Q=d L L L q4 q4 q4 q4 q4 Q=d q4 q4 q4 Q4 L L L L L L Q=d L L q5 q5 q5 q5 q5 q5 Q=d q5 q5 Q5 L L L L L L L Q=d L q6 q6 q6 q6 q6 q6 q6 Q=d q6 Q6 L L L L L L L L Q=d q7 q7 q7 q7 q7 q7 q7 q7 Q=d Q7
demultiplex (active HIGH) decoder (when D = H)
store (do nothing)
1. H = HIGH voltage level L = LOW voltage level X = don't care d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition q = lower case letters indicate the state of the referenced output established during the last cycle in which it was addressed or cleared
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Philips Semiconductors
Product specification
8-bit addressable latch
74HC/HCT259
Fig.5 Logic diagram.
December 1990
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Philips Semiconductors
Product specification
8-bit addressable latch
DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER min. tPHL/ tPLH propagation delay D to Qn propagation delay An to Qn propagation delay LE to Qn propagation delay MR to Qn output transition time +25 typ. 58 21 17 58 21 17 55 20 16 50 18 14 19 7 6 70 14 12 70 14 12 80 16 14 0 0 0 2 2 2 17 6 5 17 6 5 19 7 6 -19 -6 -5 -11 -4 -3 max. 185 37 31 185 37 31 170 34 29 155 31 26 75 15 13 90 18 15 90 18 15 100 20 17 0 0 0 2 2 2 -40 to +85 min. max. 230 46 39 230 46 39 215 43 37 195 39 33 95 19 16 105 21 18 105 21 18 120 24 20 0 0 0 2 2 2 -40 to +125 min. max. 280 56 48 280 56 48 255 51 43 235 47 40 119 22 19 ns
74HC/HCT259
TEST CONDITIONS UNIT V WAVEFORMS CC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.7
tPHL/ tPLH
ns
Fig.8
tPHL/ tPLH
ns
Fig.6
tPHL
ns
Fig.9
tTHL/ tTLH
ns
Figs 6 and 7
tW
LE pulse width HIGH or LOW MR pulse width LOW set-up time D, An to LE hold time D to LE hold time An to LE
ns
Fig.6
tW
ns
Fig.9
tsu
ns
Figs 10 and 11
th
ns
Fig.10
th
ns
Fig.11
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Philips Semiconductors
Product specification
8-bit addressable latch
DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI Note to HCT types
74HC/HCT259
The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT An LE D MR
UNIT LOAD COEFFICIENT 1.50 1.50 1.20 0.75
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Philips Semiconductors
Product specification
8-bit addressable latch
AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER min. tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tPHL tTHL/ tTLH tW tW tsu tsu th th propagation delay D to Qn propagation delay An to Qn propagation delay LE to Qn propagation delay MR to Qn output transition time LE pulse width LOW MR pulse width LOW set-up time D to LE set-up time An to LE hold time D to LE hold time An to LE 19 18 17 17 0 0 +25 typ. 23 25 22 23 7 11 10 10 10 -8 -4 max. 39 41 38 39 15 24 23 21 21 0 0 -40 TO +85 -40 TO +125 min. max. 49 51 48 49 19 29 27 26 26 0 0 min. max. 59 62 57 59 22 ns ns ns ns ns ns ns ns ns ns ns
74HC/HCT259
TEST CONDITIONS WAVEFORMS UNIT V CC (V) 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Fig.7 Fig.8 Fig.6 Fig.9 Figs 6 and 7 Fig.6 Fig.9 Fig.10 Fig.11 Fig.10 Fig.11
December 1990
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Philips Semiconductors
Product specification
8-bit addressable latch
AC WAVEFORMS
74HC/HCT259
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.6
Waveforms showing the enable input (LE) to output (Qn) propagation delays, the enable input pulse width and the output transition times.
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7
Waveforms showing the data input (D) to output (Qn) propagation delays and the output transition times.
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8
Waveforms showing the address inputs (An) to outputs (Qn) propagation delays and the output transition times.
December 1990
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Philips Semiconductors
Product specification
8-bit addressable latch
74HC/HCT259
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing the conditional reset input (MR) to output (Qn) propagation delays.
The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.10 Waveforms showing the data set-up and hold times for the D input to LE input.
The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.11 Waveforms showing the address set-up and hold times for An inputs to LE input.
PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines".
December 1990
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