View UPD70208H_5604.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATA SHEET
PD70208H, 70216H
V40HLTM, V50HLTM 16/8, 16-BIT MICROPROCESSOR
MOS INTEGRATED CIRCUIT
DESCRIPTION
The PD70208H (V40HL) is a high-speed, low-power 16-/8-bit microprocessor based on the PD70208 (V40TM) with 16-bit architecture, 8-bit data bus, and general-purpose peripheral functions. The PD70216H (V50HL) is a high-speed, low-power 16-bit microprocessor based on the PD70216 (V50TM ) with 16bit architecture, 16-bit data bus, and general-purpose peripheral functions. The V40HL and V50HL offer 20 MHz operation, and in addition to the conventional standby functions, also allows the clock to be stopped by the use of fully static internal circuitry, thus achieving greatly reduced power consumption. It is also capable of 3 V operation in addition to the previous 5 V operation, making it ideally suited to battery driven systems. Details are given in the following manuals. Be sure to read when carrying out design work. * V40HL, V50HL User's Manual - Hardware (U11610E) * 16-bit V seriesTM User's Manual - Instruction (U11301J: Japanese version)
FEATURES
* *
High-speed, low-power version of V40 and V50 High-performance CPU (V20TM /V30TM software compatible) * Minimum instruction execution time: * Memory addressing space: 1M bytes * High-speed multiply/divide instructions: 100 ns (20 MHz, 5 V) 200 ns (10 MHz, 3 V)
0.95 to 2.8 s (20 MHz, 5 V) 1.9 to 5.6 s (10 MHz, 3 V) * Maskable (ICU) & non-maskable (NMI) interrupt inputs * PD8080AF emulation function * Standby functions, clock stoppage capability Standard peripheral LSI functions on chip * * * * * * * Clock generator (CG) Programmable wait control unit (WCU) Refresh control unit (REFU) Timer/counter unit (TCU) *** PD71054 subset Serial control unit (SCU) *** PD71051 subset Interrupt control unit (ICU) *** PD71059 subset DMA control unit (DMAU) *** PD71071/71037 subset (functions of either selectable) 10/12.5/16/20 MHz (at 5 V, with 20/25/32/40 MHz supplied externally) 5/6.25/8/10 MHz (at 3 V, with 10/12.5/16/20 MHz supplied externally)
*
*
Operating frequency:
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U13225EJ4V0DS00 (4th edition) Date Published April 1999 N CP(K) Printed in Japan
The mark
shows the the major revised points.
(c)
1995
PD70208H, 70216H
ORDERING INFORMATION
(1) V40HL Part Number Package 80-pin plastic QFP (14 x 20 mm) (Resin thickness 2.7 mm) 80-pin plastic QFP (14 x 20 mm) (Resin thickness 2.7 mm) 80-pin plastic QFP (14 x 20 mm) (Resin thickness 2.7 mm) 80-pin plastic QFP (14 x 20 mm) (Resin thickness 2.7 mm) 80-pin plastic TQFP (Fine pitch) (12 (Resin thickness 1.0 mm) 80-pin plastic TQFP (Fine pitch) (12 (Resin thickness 1.0 mm) 80-pin plastic TQFP (Fine pitch) (12 (Resin thickness 1.0 mm) 80-pin plastic TQFP (Fine pitch) (12 (Resin thickness 1.0 mm) 68-pin plastic QFJ (950 x 950 mil) 68-pin plastic QFJ (950 x 950 mil) 68-pin plastic QFJ (950 x 950 mil) 68-pin plastic QFJ (950 x 950 mil) Max. Operating Frequency (MHz) 10 12.5 16 20 x 12 mm) x 12 mm) x 12 mm) x 12 mm) 10 12.5 16 20 10 12.5 16 20
PD70208HGF-10-3B9 PD70208HGF-12-3B9 PD70208HGF-16-3B9 PD70208HGF-20-3B9 PD70208HGK-10-9EU PD70208HGK-12-9EU PD70208HGK-16-9EU PD70208HGK-20-9EU PD70208HLP-10 PD70208HLP-12 PD70208HLP-16 PD70208HLP-20
(2) V50HL Part Number
Package 80-pin plastic QFP (14 x 20 mm) (Resin thickness 2.7 mm) 80-pin plastic QFP (14 x 20 mm) (Resin thickness 2.7 mm) 80-pin plastic QFP (14 x 20 mm) (Resin thickness 2.7 mm) 80-pin plastic QFP (14 x 20 mm) (Resin thickness 2.7 mm) 80-pin plastic TQFP (Fine pitch) (12 (Resin thickness 1.0 mm) 80-pin plastic TQFP (Fine pitch) (12 (Resin thickness 1.0 mm) 80-pin plastic TQFP (Fine pitch) (12 (Resin thickness 1.0 mm) 80-pin plastic TQFP (Fine pitch) (12 (Resin thickness 1.0 mm) 68-pin plastic QFJ (950 x 950 mil) 68-pin plastic QFJ (950 x 950 mil) 68-pin plastic QFJ (950 x 950 mil) 68-pin plastic QFJ (950 x 950 mil)
Max. Operating Frequency (MHz) 10 12.5 16 20 x 12 mm) x 12 mm) x 12 mm) x 12 mm) 10 12.5 16 20 10 12.5 16 20
PD70216HGF-10-3B9 PD70216HGF-12-3B9 PD70216HGF-16-3B9 PD70216HGF-20-3B9 PD70216HGK-10-9EU PD70216HGK-12-9EU PD70216HGK-16-9EU PD70216HGK-20-9EU PD70216HLP-10 PD70216HLP-12 PD70216HLP-16 PD70216HLP-20
2
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
PIN CONFIGURATION (Top View)
(1) V40HL * 80-pin Plastic QFP (14 x 20 mm) PD70208HGF-10-3B9
PD70208HGF-12-3B9 PD70208HGF-16-3B9 PD70208HGF-20-3B9
A17/PS1 A18/PS2 A19/PS3 REFRQ HLDRQ HLDAK RESOUT VDD VDD RESET READY NMI BS2 BS1 BS0 MRD
A16/PS0 NC A15 A14 A13 A12 A11 A10 A9 A8 GND NC GND AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NC NC END/TC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
IORD NC MWR IOWR BUSLOCK BUFR/W BUFEN CLKOUT X1 X2 GND NC GND High ASTB QS0 QS1 POLL TCTL2 TOUT2 TCLK NC INTP7 INTP6
DMARQ0 DMAAK0 DMARQ1 DMAAK1 DMARQ2 DMAAK2 DMARQ3/RXD DMAAK3/TXD IC INTAK/SRDY/TOUT1 VDD INTP1 INTP2 INTP3 INTP4 INTP5
Caution Leave IC pin open.
Data Sheet U13225EJ4V0DS00
3
PD70208H, 70216H
* 80-pin Plastic TQFP (Fine pitch) (12 x 12 mm) PD70208HGK-10-9EU
PD70208HGK-12-9EU PD70208HGK-16-9EU PD70208HGK-20-9EU
NC A16/PS0 A17/PS1 A18/PS2 A19/PS3 REFRQ HLDRQ HLDAK RESOUT VDD VDD RESET READY NMI BS2 BS1 BS0 MRD IORD NC
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 A15 NC A14 A13 A12 A11 A10 A9 A8 GND GND AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 NC MWR IOWR BUSLOCK BUFR/W BUFEN CLKOUT X1 X2 GND GND High ASTB QS0 QS1 POLL TCTL2 TOUT2 TCLK NC
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
4
NC END/TC DMARQ0 DMAAK0 DMARQ1 DMAAK1 DMARQ2 DMAAK2 DMARQ3/RXD DMAAK3/TXD INTAK/SRDY/TOUT1 VDD INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTP7 NC
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
* 68-pin Plastic QFJ (950 x 950 mil) PD70208HLP-10
PD70208HLP-12 PD70208HLP-16 PD70208HLP-20
RESOUT A16/PS0 A17/PS1 A18/PS2 A19/PS3 REFRQ HLDRQ READY RESET HLDAK
98 A15 A14 A13 A12 A11 A10 A9 A8 GND AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
765
43
2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
IORD
MRD
BS2
BS1
BS0
NMI
VDD
MWR IOWR BUSLOCK BUFR/W BUFEN CLKOUT X1 X2 GND High ASTB QS0 QS1 POLL TCTL2 TOUT2 TCLK
44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
INTAK/SRDY/TOUT1
DMARQ3/RXD
DMAAK3/TXD
INTP1
INTP2
INTP3
INTP4
INTP5
INTP6
END/TC
DMARQ0
DMAAK0
DMARQ1
DMAAK1
DMARQ2
DMAAK2
INTP7
Data Sheet U13225EJ4V0DS00
5
PD70208H, 70216H
(2) V50HL * 80-pin Plastic QFP (14 x 20 mm) PD70216HGF-10-3B9
PD70216HGF-12-3B9 PD70216HGF-16-3B9 PD70216HGF-20-3B9
A17/PS1 A18/PS2 A19/PS3 REFRQ HLDRQ HLDAK RESOUT VDD VDD RESET READY NMI BS2 BS1 BS0 MRD A16/PS0 NC AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 GND NC GND AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NC NC END/TC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
IORD NC MWR IOWR BUSLOCK BUFR/W BUFEN CLKOUT X1 X2 GND NC GND UBE ASTB QS0 QS1 POLL TCTL2 TOUT2 TCLK NC INTP7 INTP6
6
DMARQ0 DMAAK0 DMARQ1 DMAAK1 DMARQ2 DMAAK2 DMARQ3/RXD DMAAK3/TXD IC INTAK/SRDY/TOUT1 VDD INTP1 INTP2 INTP3 INTP4 INTP5
Caution Leave IC pin open.
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
* 80-pin Plastic TQFP (Fine pitch) (12 x 12 mm) PD70216HGK-10-9EU
PD70216HGK-12-9EU PD70216HGK-16-9EU PD70216HGK-20-9EU
NC A16/PS0 A17/PS1 A18/PS2 A19/PS3 REFRQ HLDRQ HLDAK RESOUT VDD VDD RESET READY NMI BS2 BS1 BS0 MRD IORD NC
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 AD15 NC AD14 AD13 AD12 AD11 AD10 AD9 AD8 GND GND AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 NC MWR IOWR BUSLOCK BUFR/W BUFEN CLKOUT X1 X2 GND GND UBE ASTB QS0 QS1 POLL TCTL2 TOUT2 TCLK NC
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
NC END/TC DMARQ0 DMAAK0 DMARQ1 DMAAK1 DMARQ2 DMAAK2 DMARQ3/RXD DMAAK3/TXD INTAK/SRDY/TOUT1 VDD INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTP7 NC
Data Sheet U13225EJ4V0DS00
7
PD70208H, 70216H
* 68-pin Plastic QFJ (950 x 950 mil) PD70216HLP-10
PD70216HLP-12 PD70216HLP-16 PD70216HLP-20
RESOUT A16/PS0 A17/PS1 A18/PS2 A19/PS3 REFRQ HLDRQ READY RESET HLDAK
98 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 GND AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
765
43
2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
IORD
MRD
BS2
BS1
BS0
NMI
VDD
MWR IOWR BUSLOCK BUFR/W BUFEN CLKOUT X1 X2 GND UBE ASTB QS0 QS1 POLL TCTL2 TOUT2 TCLK
44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
INTAK/SRDY/TOUT1
DMARQ3/RXD
DMAAK3/TXD
INTP1
INTP2
INTP3
INTP4
INTP5
INTP6
END/TC
DMARQ0
DMAAK0
DMARQ1
DMAAK1
DMARQ2
8
Data Sheet U13225EJ4V0DS00
DMAAK2
INTP7
PD70208H, 70216H
PIN NAMES
A8-A15 A16/PS0-A19/PS3 AD0-AD15 ASTB BS0-BS2 BUFEN BUFR/W BUSLOCK CLKOUT DMAAK0-DMAAK2 DMAAK3/TXD DMARQ0-DMARQ2 DMARQ3/RXD END/TC GND High HLDAK HLDRQ IC INTAK/SRDY/TOUT1 INTP1-INTP7 IORD IOWR MRD MWR NC NMI POLL QS0, QS1 READY REFRQ RESET RESOUT TCLK TCTL2 TOUT2 UBE VDD X1, X2 : Address Bus : Address/Processor Status : Address Bus/Data Bus : Address Strobe : Bus Status : Buffer Enable : Buffer Read/Write : Bus Lock : Clock Output : DMA Acknowledge : DMA Acknowledge/Transmit Data : DMA Request : DMA Request/Receive Data : End/Terminal Count : Ground : High Level Output : Hold Acknowledge : Hold Request : Internally Connected : Interrupt Acknowledge/Serial Ready/Timer Output 1 : Interrupt Request from Peripherals : I/O Read : I/O Write : Memory Read : Memory Write : No Connection : Non-Maskable Interrupt Request : Poll : Queue Status : Ready : Refresh Request : Reset : Reset Output : Timer Clock : Timer Control 2 : Timer Output 2 : Upper Byte Enable : Power Supply : Crystal
Data Sheet U13225EJ4V0DS00
9
PD70208H, 70216H
AD0-AD7
SRDY
BS0-BS2
(1) V40HL
TXD RXD
A16/PS0-A19/PS3
BLOCK DIAGRAM
A8-A15
QS1
TOUT2 TOUT1 TCU TCTL2 TCLK SCU BIU
QS0
POLL BUSLOCK BUFEN BUFR/W High ASTB IOWR IORD
INTP7 MWR INTP6 INTP5 INTP4 INTP3 INTP2 INTP1 ICU CPU WCU MRD READY RESOUT RESET
INTAK NMI
BAU
HLDAK HLDRQ
X2 CG X1 DMAU REFU
CLKOUT
DMARQ0
DMAAK0
DMARQ1
DMAAK1
DMARQ2
DMAAK2
DMARQ3
DMAAK3
END/TC
CPU : CG : BIU : BAU : WCU :
Central Processing Unit Clock Generator Bus Interface Unit Bus Arbitration Unit Wait Control Unit
REFU : TCU : SCU ICU : :
Reflesh Control Unit Timer/Count Unit Serial Control Unit Interrupt Control Unit DMA Control Unit
DMAU :
10
Data Sheet U13225EJ4V0DS00
REFRQ
PD70208H, 70216H
(2) V50HL
A16/PS0-A19/PS3
AD0-AD15
SRDY
BS0-BS2
QS1
TOUT2 TOUT1 TCU TCTL2 TCLK SCU BIU
TXD
QS0
RXD
POLL BUSLOCK BUFEN BUFR/W UBE ASTB IOWR IORD
INTP7 MWR INTP6 INTP5 INTP4 INTP3 CPU INTP2 INTP1 ICU WCU MRD READY RESOUT RESET
INTAK NMI
BAU
HLDAK HLDRQ
X2 CG X1 DMAU REFU
CLKOUT
DMARQ0
DMAAK0
DMARQ1
DMAAK1
DMARQ2
DMAAK2
DMARQ3
DMAAK3
END/TC
REFRQ
Data Sheet U13225EJ4V0DS00
11
PD70208H, 70216H
DIFFERENCES FROM V40 AND V50
Item Operating supply voltage Operating frequency VDD = 5 V 3 V, 5 V
V40HL, V50HL 5V MAX. : 8, 10 MHz MIN. : 2 MHz No operation
V40, V50
MAX. : 10, 12.5, 16, 20 MHz MIN. : DC MAX. : 5, 6.25, 8, 10 MHz MIN. : DC Variable scaling factor Variable instruction cycle time Maximum input frequency: 40 MHz
VDD = 3 V
Clock generator (CG)
Fixed scaling factor Fixed instruction cycle time Maximum input frequency: 20 MHz V40: Relocation possible on 8-bit boundary V50: Relocation possible on 16-bit boundary Memory space: 3 divisions I/O space: Not divided Refresh address: 9 bits No REFRQ extended timing No dedicated baund rate generator incorporated
Internal I/O relocation function Wait control unit (WCU)
Switchable 8-bit boundary or 16-bit boundary relocation function Memory space: 5 divisionsNote 1 I/O space: 3 divisionsNote 2
Refresh control unit (REFU) Serial control unit (SCU)
Refresh address: 16 bits REFRQ extended timing supported Dedicated baud rate generator incorporated
DMA control unit (DMAU)
PD71071/71037 subset (either function selectable)
HALT mode, STOP mode
PD71071 subset
Standby functions
HALT mode only
Notes 1. Divided into 3 when a reset is performed. 2. Not divided when a reset is performed.
12
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
CONTENTS 1. PIN FUNCTIONS ...................................................................................................................................
1.1 1.2 LIST OF PIN FUNCTIONS ........................................................................................................................... PROCESSING OF UNUSED PINS ..............................................................................................................
15
15 17
2.
MEMORY AND I/O CONFIGURATION ................................................................................................
2.1 2.2 MEMORY SPACE ......................................................................................................................................... I/O SPACE ....................................................................................................................................................
19
19 21
3. 4. 5. 6.
CPU ........................................................................................................................................................ CG (CLOCK GENERATOR) ................................................................................................................. BIU (BUS INTERFACE UNIT) .............................................................................................................. BAU (BUS ARBITRATION UNIT) ........................................................................................................
22 24 24 25 27
27 28
7. WCU (WAIT CONTROL UNIT) ................................................................................................................
7.1 7.2 FEATURES ................................................................................................................................................... RELATION BETWEEN WCU AND READY PIN ........................................................................................
8.
REFU (REFRESH CONTROL UNIT) ....................................................................................................
8.1 8.2 FEATURES ................................................................................................................................................... REFRESH OPERATIONS ............................................................................................................................
29
29 29
9.
TCU (TIMER/COUNTER UNIT) ............................................................................................................
9.1 9.2 FEATURES ................................................................................................................................................... TCU INTERNAL BLOCK DIAGRAM ...........................................................................................................
30
30 30
10. SCU (SERIAL CONTROL UNIT) ..........................................................................................................
10.1 FEATURES ................................................................................................................................................... 10.2 SCU INTERNAL BLOCK DIAGRAM ...........................................................................................................
31
31 31
11. ICU (INTERRUPT CONTROL UNIT) ....................................................................................................
11.1 FEATURES ................................................................................................................................................... 11.2 ICU INTERNAL BLOCK DIAGRAM ............................................................................................................
32
32 32
12. DMAU (DMA CONTROL UNIT) ............................................................................................................
12.1 FEATURES ................................................................................................................................................... 12.2 DMAU INTERNAL BLOCK DIAGRAM .......................................................................................................
33
33 33
13. STANDBY FUNCTIONS ........................................................................................................................ 14. RESET OPERATION ............................................................................................................................. 15. INSTRUCTION SET ...............................................................................................................................
34 34 35
Data Sheet U13225EJ4V0DS00
13
PD70208H, 70216H
16. ELECTRICAL SPECIFICATIONS .........................................................................................................
16.1 AT 5 V OPERATION .................................................................................................................................... 16.2 AT 3 V OPERATION ....................................................................................................................................
66
66 75
17. PACKAGE DRAWINGS ........................................................................................................................ 100 18. RECOMMENDED SOLDERING CONDITIONS ................................................................................... 103
14
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
1. PIN FUNCTIONS
1.1 LIST OF PIN FUNCTIONS
Pin Name AD0 to AD0 to A8 to AD15Note 1, 3 AD7Note 2, 3 Input/Output 3-state I/O 3-state I/O 3-state output 3-state output Output Input Output Input Output Input Input 3-state output 3-state output 3-state output 3-state output Output 3-state output 3-state output 3-state output Input 3-state output 3-state output Input -- Output 3-state output Output Output Input Input Input Output Clock output Bus status Queue status Timer 2 output Timer 2 control Timer clock Maskable interrupts Interrupt acknowledge/serial reception ready/timer 1 output Time-division address/data bus Time-division address/data bus Address bus Time-division address/processor status Refresh request Bus hold request Bus hold acknowledge Reset System reset output Bus cycle end Non-maskable interrupt Memory read strobe Memory read strobe I/O read strobe I/O write strobe Address strobe Data bus upper byte enable High level output Bus lock Floating-point operation processor polling Buffer read/write Buffer enable Crystal/external clock Function
A15Note 2, 3 A19/PS3Note 3
A16/PS0 to REFRQ HLDRQ HLDAK RESET RESOUT READY NMI MRDNote 3 MWRNote 3 IORDNote 3 IOWRNote 3 ASTB
UBENote 1, 3 HighNote 2 BUSLOCKNote 3 POLL BUFR/WNote 3 BUFENNote 3 X1 X2 CLKOUT BS0 to BS2 Note 3
QS0, QS1 TOUT2 TCTL2 TCLK INTP1 to INTP7 INTAK/SRDY/TOUT1
Notes 1. V50HL only 2. V40HL only 3. These pins are provided with a latch. Therefore, when they go into a high-impedance state, they hold the status before the high-impedance state until driven by an external device. It is not necessary to pull up or down the data bus. To invert the level of the pin that goes into a high-impedance state by an external device, a drive current higher than the latch invert current (IILH, IILL) is necessary.
Data Sheet U13225EJ4V0DS00
15
PD70208H, 70216H
Pin Name DMAAK3/TXD DMARQ3/RXD DMAAK0 to DMAAK2 DMARQ0 to DMARQ2 END/TC VDD GND IC Input/Output Output Input Output Input I/O -- -- -- Function DMA acknowledge 3/serial transmit data DMA request 3/serial receive data DMA acknowledge DMA request DMA service forcible termination/DMA service completion Positive power supply pin Ground potential pin Internal connection pin (External connection impossible)
16
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
1.2 PROCESSING OF UNUSED PINS Table 1-1 shows the processing (recommended connection) of the unused pins. Use of a resistor with a resistance of 1 to 10 k is recommended to connect these pins to VDD or GND via resistor. Table 1-1. Processing of Unused Pins
Pin Name AD0 to AD0 to A8 to AD15Note 1 AD7Note 2 Input/Output 3-state I/O 3-state I/O 3-state output 3-state output Output Input Output Output Input Input 3-state output 3-state output 3-state output 3-state output Output 3-state output Output 3-state output Input 3-state output 3-state output Output 3-state output Output Output Input Input Input Output Output Input Output Input I/O Connect to GND via resistor Open Connect to GND via resistor Individually connect to VDD via resistor Open Connect to GND via resistor Open Connect to GND via resistor Open Connect to GND via resistor Open Open Connect to VDD via resistor Connect to GND via resistor Open Open Recommended Connection
A15Note 2
A16/PS0 to A19/PS3 REFRQ HLDRQ HLDAK RESOUT READY NMI MRD MWR IORD IOWR ASTB UBENote 1 HighNote 2 BUSLOCK POLL BUFR/W BUFEN CLKOUT BS0 to BS2 QS0, QS1 TOUT2 TCTL2 TCLK INTP1 to INTP7 INTAK/SRDY/TOUT1 DMAAK3/TxD DMARQ3/RxD DMAAK0 to DMAAK2 DMARQ0 to DMARQ2 END/TC
Notes 1. V50HL only 2. V40HL only
Data Sheet U13225EJ4V0DS00
17
PD70208H, 70216H
Remark The circuit configuration of the latch is as illustrated below. To invert the level of the pin with a latch, a drive current higher than the latch invert current is necessary. (1) Output pin
Output buffer
Latch Output pin address bus, control bus
Hi-Z control
(2) I/O pin
Output buffer
Latch I/O pin (data bus)
Hi-Z control
Input buffer
18
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
2. MEMORY AND I/O CONFIGURATION
2.1 MEMORY SPACE The V40HL and V50HL can access a 1M-byte (512K-word) memory space. Figure 2-1. Memory Map
FFFFFH Reserved FFFFCH FFFFBH Dedicated FFFF0H FFFEFH
General Use
00400H 003FFH Interrupt Vector Table 00000H
Figure 2-2. Interface with Memory (1/2) (a) V40HL
A0-A19 Address Bus (20)
Memory 1M Byte
8 D0-D7 Data Bus (8)
Data Sheet U13225EJ4V0DS00
19
PD70208H, 70216H
Figure 2-2. Interface with Memory (2/2) (b) V50HL
A1-A19 A0 UBE BSEL 19
Address Bus (19)
19
BSEL
Memory Upper Bank 512K Byte
Memory Lower Bank 512K Byte
8 D0-D15
D8-D15 Data Bus (16)
8 D0-D7
20
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
2.2 I/O SPACE In the V40HL and V50HL, I/Os up to 64K bytes (32K words) can be accessed in an area independent of the memory. The various on-chip peripheral LSIs are set by accessing the system I/O area. Extended functions added to those of the V40 and V50 are mapped onto unused V40 and V50 registers and the reserved area. The I/O map is shown in Figure 2-3. Figure 2-3. I/O Map
FFFFH Area used for setting of I/O boundary, WCU, REFU, baud rate generator, etc., and DMAU, ICU, TCU and SCU allocation.
System I/O Area FFE0H FFDFH
Reserved Area
FF00H FEFFH
DMAU
ICU 256 Bytes TCU The DMAU, ICU, TCU and SCU are allocated within any 256 bytes.
SCU
Internal I/O Area
External I/O Area 0000H
Data Sheet U13225EJ4V0DS00
21
PD70208H, 70216H
3. CPU
The CPU has the same functions as the V20HLTM and V30HLTM. In hardware terms, there are some changes regarding the use of the bus with on-chip peripherals, but in software terms the CPU is fully compatible. The internal block diagram of the CPU is shown in Figure 3-1. Figure 3-1. Internal Block Diagram of CPU (1/2) (a) V40HL
Internal Address/Data Bus (20) To BIU ADM
PS SS DS0 DS1 PFP DP TEMP Q0 Q1 Q2 Q3
T-STATE CONTROL
CYCLE DECISION
INTERRUPT CONTROL
NMI INT (From ICU) CLOCK (From CG)
QUEUE CONTROL
STANDBY CONTROL
BCU EXU LC PC AW BW CW DW IX IY BP SP TC TA TB
EFFECTIVE ADDRESS GENERATOR
ADDRESS REGISTER
INSTRUCTION
29 Micro Data Bus
Queue Data Bus (8)
ROM
SEQUENCE CONTROL
SHIFTER
INSTRUCTION DECODER
ALU
PSW Sub Data Bus (16) Main Data Bus (16)
22
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
Figure 3-1. Internal Block Diagram of CPU (2/2) (b) V50HL
Internal Address/Data Bus (20) To BIU ADM
PS SS DS0 DS1 PFP DP TEMP Q0 Q1 Q2 Q3 Q4 Q5
T-STATE CONTROL
CYCLE DECISION
INTERRUPT CONTROL
NMI INT (From ICU) CLOCK (From CG)
QUEUE CONTROL
STANDBY CONTROL
BCU EXU LC PC AW BW CW DW IX IY BP SP TC TA TB
EFFECTIVE ADDRESS GENERATOR
ADDRESS REGISTER
INSTRUCTION
29 Micro Data Bus
Queue Data Bus (8)
ROM
SEQUENCE CONTROL
SHIFTER
INSTRUCTION DECODER
ALU
PSW Sub Data Bus (16) Main Data Bus (16)
Data Sheet U13225EJ4V0DS00
23
PD70208H, 70216H
4. CG (CLOCK GENERATOR)
The CG generates a clock at a frequency of 1/2, 1/4, 1/8 or 1/16 that of the crystal and oscillator connected to the X1 and X2 pins, supplies it as the CPU operating clock and outputs it externally as the CLKOUT pin output. The interrupt cycle time can be changed according to the oscillator scaling factor. The scaling factor can be set by a system I/O area register. Figure 4-1. Internal Block Diagram of CG
X1 Oscillator X2
fXX
Divide-by-2 Scaler
Divide-by-1-to-8 Scaler
fX
CPU, DMAU, REFU, SCU
CLKOUT Baud Rate Counter (BRC)
Divide-by-2-to-16 Scaler
TCU
5. BIU (BUS INTERFACE UNIT)
The BIU controls the data bus, address bus and control bus pins. These buses are used by the CPU, DMAU (DMA control unit) and REFU (refresh control unit). The BIU synchronizes the RESET input signal and READY input signal using the CLOCK signal generated by the clock generator (CG). In addition to being supplied to the inside of the V40HL and V50HL, the synchronized reset signal is also output externally from the RESOUT pin. The synchronized READY signal is supplied to the internal CPU, DMAU and REFU. Figure 5-1. RESET and READY Signal Synchronization
CLOCK RESET CK
D
Q
RESOUT To Internal Units
READY
D
CK
Q
D
CK
Q
To Internal Units
24
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
6. BAU (BUS ARBITRATION UNIT)
The BAU performs bus arbitration among bus masters. A list of bus masters (units which can acquire the bus) is shown below. Table 6-1. Bus Masters
Bus Master CPU DMAU REFU External bus master (HLDRQ pin input)
Bus Cycle Program fetch, data read/write DMA cycle Refresh cycle Bus cycle driven by external device
The relative priorities of the bus masters are shown below. High CPU (when BUSLOCK prefix is used) REFU (highest priority: when given number of requests are reached) DMAU HLDRQ pin CPU (normal CPU cycle) Low REFU (lowest priority: cycle steal)
BAU bus arbitration is performed as follows. A bus master such as the CPU, DMAU, REFU, etc., incorporated in the V40HL and V50HL normally release the bus at the end of the bus cycle currently being executed, as shown in Figure 6-1. However, in the case of a bus master connected to the HLDRQ pin, or cascaded external DMA controllers, for instance, the situation is as shown in Figure 6-2. The V40HL and V50HL request return of the bus by inactivating the acknowledge signal (HLDAK), and on receiving this request, the external bus master holding the bus should release the bus by dropping the bus hold request signal (HLDRQ). The V40HL and V50HL-internal bus master with the highest priority is kept waiting until the bus hold request signal is dropped. This is called a bus wait operation.
Data Sheet U13225EJ4V0DS00
25
PD70208H, 70216H
Figure 6-1. Internal Bus Cycles
Bus Cycle
CPU
CPU
DMA
Refresh
Refresh
Refresh
Internal DMA Request
Internal Refresh Request (Highest Priority)
Figure 6-2. Bus Wait Operation
Bus Wait
Bus Cycle
Bus Release
Note
Refresh
HLDRQ Pin
HLDAK Pin
Internal Refresh Request (Highest Priority)
Note
The period in which the external bus master which has been given the bus after its release by the V40HL and V50HL can use the bus.
26
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
7. WCU (WAIT CONTROL UNIT)
The WCU has the function of automatically inserting a wait state (TW) of 0 to 3 clock cycles in a CPU, DMAU or REFU bus cycle. 7.1 FEATURES Automatic setting of 0 to 3 waits for a CPU memory bus cycle 1M-byte memory space can be divided into 5 64K-byte I/O space can be divided into 3 Automatic setting of 0 to 3 waits for an external I/O cycle Automatic setting of 0 to 3 waits for a DMA cycle Automatic setting of 0 to 3 waits for a refresh cycle Same as V40 and V50 directly after a reset (memory space divided into 3, no division of I/O space) Figure 7-1. Example of Memory Space Division
* * * * * * *
FFFFFH Upper Memory Block
Upper Sub Memory Block
1 M-Byte Memory Area
Middle Memory Block
Lower Memory Block 00000H Lower Sub Memory Block
Remark The division specification and the size of each block are set by means of a system I/O area register.
Data Sheet U13225EJ4V0DS00
27
PD70208H, 70216H
Figure 7-2. Example of I/O Space Division
FFFFH Upper I/O Block
64K-Byte I/O Area
Middle I/O Block
Lower I/O Block 0000H
Remark The division specification and the size of each block are set by means of a system I/O area register. 7.2 RELATION BETWEEN WCU AND READY PIN
When wait cycles exceeding 3 clock cycles are necessary, the WCU and the READY signal pin can be used in combination. The number of wait cycles specified by the WCU set value or the number of wait cycles under READY control, whichever is larger, is inserted. Figure 7-3. WCU and READY Control
V40HL/V50HL WCU
Bus Control READY
28
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
8. REFU (REFRESH CONTROL UNIT)
The REFU generates refresh cycles required for refreshing of external DRAM. Refresh enabling/disabling and the refresh interval can be set programmably. 8.1 FEATURES Lowest-priority refreshing/highest-priority refreshing 7-refresh queue 16-bit refresh address REFRQ extended timing supported (REFRQ active from T1 state)
* * * *
8.2 REFRESH OPERATIONS The REFU has two priorities. Normally, it has the lowest priority, and a refresh cycle cannot be started unless the bus is completely idle. However, if there are 7 or more pending refresh requests, it is given the highest priority, and it requests the bus master holding the bus to relinquish it. (See 6. BAU.) The refresh address is output on A0 to A15. Every refresh cycle the refresh address is incremented by 1 (for the V40HL) or by 2 (for the V50HL), and the next refresh address is generated. In a refresh cycle, a low-level signal is output on the low address pins (A16 to A19). This refresh address is not affected by a reset. When the device is powered on, the refresh address is undefined.
Data Sheet U13225EJ4V0DS00
29
PD70208H, 70216H
9. TCU (TIMER/COUNTER UNIT)
The TCU incorporates 3 counters, and can be used as a timer, event counter, rate generator, etc. Functionally it is a subset of the PD71054. 9.1 FEATURES 3 x 16-bit counters Six programmable count modes Binary/BCD count Multiple latch command Choice of two input clocks: internal/external TCU INTERNAL BLOCK DIAGRAM
TCLK (External) TCTL1=High TOUT1 (External) TCTL2 (External) TOUT2 (External) To INTL2/SCU
* * * * *
9.2
TCU Selection Note 2 Signal IORD IOWR Note 1
CLOCK Prescaler TCTL0=High TOUT0 (To INTL0)
SW TCT #0 Read/Write Control Control Logic
SW
SW
Status Register
Down Counter (16)
(16) H(8) L(8) Count Register (16) H(8) L(8) Count Latch
TCT #1
TCT #2
TMD (Mode Register)
(8) Status Latch (8)
(8)
(8)
Internal Data Bus
Notes 1. A0 or A1 (Set by a system I/O area register) 2. A1 or A2 (Set by a system I/O area register)
30
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
10. SCU (SERIAL CONTROL UNIT)
The SCU performs control of serial communication (asynchronous). Its functions are a subset of the PD71051 excluding synchronous communication. Also, what was the control word register in the PD71051 has been divided into two: a command register and a mode register. 10.1 FEATURES Dedicated baud rate generator incorporated (using internal clock)
* * * * * * * * * * * *
Asynchronous serial communication Clock rate: baud rate x 16, x 64 Baud rate: DC - 500 kbps Character length: 7/8 bits Transmit stop bits: 1/2 bits Break transmission Automatic break detection Full-duplex double-buffer system Parity addition/checking Error detection: parity, overrun, framing Interrupt generation maskable
10.2 SCU INTERNAL BLOCK DIAGRAM
Baud Rate Generator RESET CLOCK
From CG
From TCU (TOUT1 Output) Selector IORD
SST Status Register SCM Command Register
SCU Status Control Bus
Read/Write Control
IOWR Note 1 Note 2 SCU Selection Signal
Internal Data Bus
SRB Receive Data Buffer STB Transmit Data Buffer
Receiver (Including Receive Buffer)
SRDY (External) RXD (External)
(8)
(8) Transmitter (Including Transmit Buffer)
TXD (External)
RTCLK
SMD Mode Register
SIMK Interrupt Mask Register
Interrupt Generation Logic
SINT (To INTL1)
Notes 1. A0 or A1 (Set by a system I/O area register) 2. A1 or A2 (Set by a system I/O area register)
Data Sheet U13225EJ4V0DS00
31
PD70208H, 70216H
11. ICU (INTERRUPT CONTROL UNIT)
The ICU arbitrates among up to 8 interrupt requests (maskable interrupts) generated inside and outside the V40HL and V50HL, and transfers one of them to the CPU. The ICU functions comprise the functions of the V40HL and V50HL minus those functions not required by the V40HL and V50HL. 11.1 FEATURES 8 interrupt inputs
* * * * * *
PD71059 cascading possible Edge- or level-triggered request input (input from internally connected TCU is edge-triggered only) Interrupt requests individually maskable Programmable interrupt request priority order Polling operation capability
11.2 ICU INTERNAL BLOCK DIAGRAM
IORD IOWR Note 1 Note 2 ICU Selection Signal
Initialize & Command Word Register Group Read/Write Control
Slave Control
SA0 SA1 SA2
To BIU
A8 A9 A10
INTAK (From CPU) Control Logic INT (To CPU) TOUT0 (From TCU) SINT (From SCU) TOUT1 (From TCU) SW SW INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTP7
Interrupt In-Service Register (IIS)
Priority Determination Logic
Interrupt Mask Register (IMK)
Interrupt Request Register (IRQ)
INTL0 INTL1 INTL2 INTL3 INTL4 INTL5 INTL6 INTL7
External Pins
Internal Data Bus
Notes 1. A0 or A1 (Set by a system I/O area register) 2. A1 or A2 (Set by a system I/O area register)
32
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
12. DMAU (DMA CONTROL UNIT)
The DMAU has 4 DMA channels, and provides the functions (subset) of two LSIs, the PD71071 and PD71037. 12.1 FEATURES Two operating modes (PD71071 mode, PD71037 mode)
* * * * * * * * * * * * * *
20-bit address register 16-bit count register Four independent DMA channels Byte transfer/word transfer selectable Three transfer modes (settable on an individual channel basis) Single transfer mode, demand transfer mode, block transfer mode Two bus modes (common to all channels: in PD71037 mode, bus release mode only) Bus release mode Bus hold mode DMA requests maskable on an individual channel basis Auto initialization function Transfer address increment/decrement Two channel priority systems (fixed priority/rotating priority) TC output at end of transfer Forced termination of service by END input Cascading capability
12.2 DMAU INTERNAL BLOCK DIAGRAM
Internal Address Bus
(20)
DMAU Address Bus (20)
Address Increment/ Decrement (20)
Internal Data Bus
(8)
Internal Bus Interface
Address Registers
Current Address (20 x 4) Base Address (20 x 4)
Control Register Group Channel Note 1 Device Control (4) (10) (8) (7 x 4) (4) (4)
Internal Control Bus BUSRQ BAU BUSAK Count Registers DMARQ0DMARQ3 External DMAAK0pins DMAAK3 END/TC Priority Control Terminal Count
DMAU Data Bus
Status Mode Control
Base Count (16 x 4) Current Count (16 x 4)
Mask Request Note 2
Count Decrementer (16)
Notes 1. In PD71071 mode 2. In PD71037 mode
Data Sheet U13225EJ4V0DS00
33
PD70208H, 70216H
13. STANDBY FUNCTIONS
The V40HL and V50HL have two modes, the HALT mode and STOP mode, as standby functions. (1) HALT mode When the HALT instruction is executed, the clock to internal CPU circuitry (excluding the HALT mode release circuit) is stopped. (2) STOP mode When the HALT instruction is executed, all clocks to the CPU and internal I/Os are stopped. STOP mode should be used when a resonator is connected to the X1 and X2 pins. Remark Switching between HALT mode and STOP mode is performed by setting a system I/O area register.
14. RESET OPERATION
When the RESET pin is driven low and this level is held for 4 clock cycles or more from the fall of the signal, the CPU and on-chip peripheral LSIs are reset. When the RESET pin subsequently returns to the high level, the CPU begins an instruction prefetch from address FFFF0H. When the V40HL and V50HL are reset, its status is fully compatible with the V40 and V50. Extended functions added to those of the V40 and V50 are mapped onto unused V40 and V50 registers and the reserved area. Table 14-1 shows the main statuses of the on-chip peripheral LSIs when a reset is performed. Table 14-1. Main Statuses of On-Chip Peripheral LSIs After Reset
Memory, external I/O, DMA & refresh Upper & lower memory blocks Refresh cycle Refresh enabling/disabling Baud rate Character Parity Stop bits Break detection : : : : : x 64 7 bits None 1 bit None : 3-wait insertion : set to 512 KB
WCU REFU
: set to 72 clock cycles : not affected by reset
SCU
DMAU
PD71071 mode Demand mode Auto initialization disabled Verify transfer, byte transfer Bus release mode DMA enabled
Caution When a reset is performed, the SCU, TCU, ICU and DMAU cannot be used.
34
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
15. INSTRUCTION SET
Table 15-1. Operand Type Legend
Identifier reg 8/16-bit general register (destination register in an instruction using two 8/16-bit general registers) reg' reg8 Source register in an instruction using two 8/16-bit general registers 8-bit general register (destination register in an instruction using two 8-bit general registers) reg8' reg16 Source register in an instruction using two 8-bit general registers 16-bit general register (destination register in an instruction using two 16-bit general registers) reg16' dmem mem mem8 mem16 mem32 imm imm3 imm4 imm8 imm16 acc sreg src-table src-block dst-block near-proc far-proc near-label short-label far-label memptr16 memptr32 regptr16 pop-value fp-op R Source register in an instruction using two 16-bit general registers 8/16-bit memory location 8/16-bit memory location 8-bit memory location 16-bit memory location 32-bit memory location Constant in range 0 to FFFFH Constant in range 0 to 7 Constant in range 0 to FH Constant in range 0 to FFH Constant in range 0 to FFFFH Accumulator AW or AL Segment register Name of 256-byte conversion translation table Name of block addressed by register IX Name of block addressed by register IY Procedure in current program segment Procedure in a different program segment Label in current program segment Label in range -128 to +127 bytes from end of instruction Label in a different program segment Word containing location offset in a different program segment to which control is to be shifted and segment base address Doubleword containing location offset in a different program segment to which control is to be shifted and segment base address General register containing location offset in a different program segment to which control is to be shifted Number of bytes to be removed from stack (0 to 64K, normally an even number) Immediate value which identifies external floating-point operation coprocessor operation code Register set Description
Data Sheet U13225EJ4V0DS00
35
PD70208H, 70216H
Table 15-2. Operation Code Legend
Identifier W reg reg' mem mod s X, XXX, YYY, ZZZ Description Byte/word specification bit (0: byte, 1: word). However, when s =1, byte data of sign extension is 16-bit operand if W = 1. Register field (000 to 111) Register field (000 to 111) (source register in instruction which uses two registers) Memory field (000 to 111) Mode field (00 to 10) Sign-extended specification bit (0: without sign extension, 1: with sign extension) Data used to determine external floating-point coprocessor operation code
36
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
Table 15-3. Operand Description Legend
Identifier AW AH AL BW CW CL DW BP SP PC PSW IX IY PS SS DS0 DS1 AC CY P S Z DIR IE V BRK MD (...) disp ext-disp8 temp TA TB TC tmpcy seg offset + - x / % xxH xxxxH Accumulator (16-bit) Accumulator (high-order byte) Accumulator (low-order byte) Register BW (16-bit) Register CW (16-bit) Register CL (low-order byte) Register DW (16-bit) Base pointer (16-bit) Stack pointer (16-bit) Program counter (16-bit) Program status word (16-bit) Index register (source) (16-bit) Index register (destination) (16-bit) Program segment register (16-bit) Stack segment register (16-bit) Data segment 0 register (16-bit) Data segment 1 register (16-bit) Auxiliary carry flag Carry flag Parity flag Sign flag Zero flag Direction flag Interrupt enable flag Overflow flag Break flag Mode flag Contents of memory indicated by contents of ( ) Displacement (8/16-bit) 16 bits with 8-bit displacement sign-extended Temporary register (8/16/32-bit) Temporary register A (16-bit) Temporary register B (16-bit) Temporary register C (16-bit) Temporary carry flag (1-bit) Immediate segment data (16-bit) Immediate offset data (16-bit) Transfer direction Addition Subtraction Multiplication Division Modulo Logical product Logical sum Exclusive logical sum Two-digit hexadecimal number Four-digit hexadecimal number Description
Data Sheet U13225EJ4V0DS00
37
PD70208H, 70216H
Table 15-4. Flag Operation Legend
Identifier (Blank) 0 1 x U R No change Cleared to 0 Set to 1 Set or cleared depending upon result Undefined Previously saved value is restored Description
Table 15-5. Memory Addressing
mod mem 000 001 010 011 100 101 110 111 BW + IX BW + IY BP + IX BP + IY IX IY DIRECT ADDRESS BW
00
01 BW + IX + disp 8 BW + IY + disp 8 BP + IX + disp 8 BP + IY + disp 8 IX + disp 8 IY + disp 8 BP + disp 8 BW + disp 8
10 BW + IX + disp 16 BW + IY + disp 16 BP + IX + disp 16 BP + IY + disp 16 IX + disp 16 IY + disp 16 BP + disp 16 BW + disp 16
Table 15-6. 8/16-Bit General Register Selection
Table 15-7. Segment Register Selection
sreg 00 01 10 11 DS1 PS SS DS0
reg, reg' 000 001 010 011 100 101 110 111
W=0 AL CL DL BL AH CH DH BH
W=1 AW CW DW BW SP BP IX IY
38
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
The instruction set is shown in tabular form on the following pages. Clock cycle shown in table is the time required for execution of instruction by the execution unit and is based on the following conditions. * Prefetch time and wait time for using bus, etc. are not included. * 0 wait is assumed for memory access. That is, the clock number of one bus cycle is four clock cycle. * 0 wait is assumed for I/O access. * Primitive block transfer instruction and primitive input/output instruction is included repeat prefixes. The number of clock cycle of instruction with byte processing and word processing (with W bit) is shown as the followings. (1) V40HL On the left of "/" : The value corresponding to byte processing (W= 0) or word processing (W = 1) of even address
On the right of "/": The value corresponding to word processing (W =1) of odd address For the clock of block transfer related instruction of V40HL, see Table 15-8. Table 15-8. Number of Clock Cycles in Block Transfer Related Instruction (V40HL)
Number of Clock Cycles Byte Processing (W = 0) MOVBK 9 + 8 x rep (9) 7 + 14 x rep (13) CMPM 7 + 10 x rep (7) 7 + 9 x rep (7) 5 + 4 x rep (5) INM 9 + 8 x rep (10) 9 + 8 x rep (10) Word Processing (W = 1) 9 + 16 x rep (17) 7 + 22 x rep (21) 7 + 14 x rep (11) 7 + 13 x rep (11) 5 + 8 x rep (9) 9 + 16 x rep (18) 9 + 16 x rep (18)
Instruction
CMPBK
LDM
STM
OUTM
Remark
The figures in parentheses apply to one-time processing only.
Data Sheet U13225EJ4V0DS00
39
PD70208H, 70216H
(2) V50HL On the left of "/" : The value corresponding to byte processing (W= 0) or word processing (W = 1) of even address The value corresponding to word processing (W =1) of odd address
On the right of "/" :
For the clock of block transfer related instruction of V50HL, see Table 15-9. Table 15-9. Number of Clock Cycles in Block Transfer Related Instruction V50HL (1/2)
Number of Clock Cycles Instruction Byte Processing (W = 0) MOVBK 9 + 8 x rep (9) 7 + 14 x rep (13) 9 + 8 x rep (10) OUTM 9 + 8 x rep (10) Odd/Odd Address 9 + 16 x rep (17) 7 + 22 x rep (21) 9 + 16 x rep (18) 9 + 16 x rep (18) Word Processing (W = 1) Odd/Even Address 9 + 12 x rep (13) 7 + 18 x rep (17) 9 + 12 x rep (14) 9 + 12 x rep (14) Even/Even Address 9 + 8 x rep (9) 7 + 14 x rep (13) 9 + 8 x rep (10) 9 + 8 x rep (10)
CMPBK
INM
Remark The figures in parentheses apply to one-time processing only. Table 15-9. Number of Clock Cycles in Block Transfer Related Instruction (V50HL) (2/2)
Number of Clock Cycles Instruction Byte Processing (W = 0) CMPM 7 + 10 x rep (7) LDM 7 + 9 x rep (7) 5 + 4 x rep (5) Word Processing (W = 1) Odd Address 7 + 14 x rep (11) 7 + 13 x rep (11) 5 + 8 x rep (9) Even Address 7 + 10 x rep (7) 7 + 9 x rep (7) 5 + 4 x rep (5)
STM
Remark The figures in parentheses apply to one-time processing only.
40
Data Sheet U13225EJ4V0DS00
Instruction Group
Mnemonic MOV
Operand(s) reg, reg' mem, reg reg, mem mem, imm reg, imm acc, dmem
Operation Code 76543210 1000101W 1000100W 1000101W 1100011W 1 0 1 1 W reg 1010000W 76543210 11 reg reg'
Bytes 2 2-4 2-4 3-6 2-3 3
Clock Cycles V40HL V50HL 2 7/11 10/14 9/13 4 10/14 2 7/11 10/14 9/13 4 10/14 reg reg' (mem) reg reg (mem) (mem) imm reg imm
Operation
Flags AC CY V P S Z
mod reg mem mod reg mem mod 0 0 0 mem
If W=0: AL (dmem) If W=1: AH (dmem + 1), AL (dmem) If W=0: (dmem) AL If W=1: (dmem + 1) AH, (dmem) AL sreg reg16 sreg (mem16) reg16 sreg (mem16) sreg reg16 (mem32) DS0 (mem32 + 2) reg16 (mem32) DS1 (mem32 + 2) AH S, Z, x, AC, x, P, x, CY S, Z, x, AC, x, P, x, CY AH reg16 mem16 AL (BW + AL) reg reg' (mem) reg AW reg16 x x x x x sreg:SS, DS0, DS1 sreg:SS, DS0, DS1
dmem, acc
1010001W
3
9/13
9/13
sreg, reg16 Data transfer instructions
Data Sheet U13225EJ4V0DS00
1000111 0 1000111 0 1000110 0 1000110 0 1100010 1
1 1 0 sreg reg mod 0 sreg mem 1 1 0 sreg reg mod 0 sreg mem mod reg mem
2 2-4 2 2-4 2-4
2 14 2 12 25
2 10/14 2 8/12 17/25
sreg, mem16 reg16, sreg mem16, sreg DS0, reg16, mem32 DS1, reg16, mem32 AH, PSW PSW, AH LDEA TRANS XCH
1100010 0
mod reg mem
2-4
25
17/25
1001111 1 1001111 0 mod reg mem
1 1 2-4 1 1 1 reg reg' mod reg mem 2 2-4
2 3 4 9 3 13/21
2 3 4 9 3 13/21
reg16, mem16 1 0 0 0 1 1 0 1 src-table reg, reg' mem, reg reg, mem AW, reg16 reg16, AW 1101011 1 1000011W 1000011W
PD70208H, 70216H
1 0 0 1 0 reg
1
3
3
41
Repeat prefixes
Primitive block transfer instructions
42
Data Sheet U13225EJ4V0DS00
Instruction Group
Mnemonic REPC
Operand(s)
Operation Code 76543210 01100101 76543210
Bytes 1
Clock Cycles V40HL V50HL 2 2
Operation While CW 0, the following byte primitive block transfer instruction is executed and CW is decremented (-1). If there is a pending interrupt, it is serviced. If CY 1 the loop is exited. Same as above If CY 0 the loop is exited. While CW 0, the following byte primitive block transfer instruction is executed and CW is decremented (-1). If there is a pending interrupt, it is serviced. If the primitive block transfer instruction is CMPBK or CMPM and Z 1 the loop is exited. Same as above If Z 0 the loop is exited. If W = 0: (IY) (IX) DIR = 0 : IX IX + 1, IY IY + 1 DIR = 1 : IX IX - 1, IY IY - 1 If W = 1: (IY + 1, IY) (IX + 1, IX) DIR = 0 : IX IX + 2, IY IY + 2 DIR = 1 : IX IX - 2, IY IY - 2
Flags AC CY V P S Z
REPNC REP REPE REPZ REPNE REPNZ MOVBK dst-block, src-block
01100100 11110011
1 1
2 2
2 2
11110010 1010010W
1 1
2 See Table 15-8
2 See Table 15-9
CMPBK
src-block, dst-block
1010011W
1
See Table 15-8
See Table 15-9
If W = 0: (IX) - (IY) DIR = 0 : IX IX + 1, IY IY + 1 DIR = 1 : IX IX - 1, IY IY - 1 If W = 1: (IX + 1, IX) - (IY + 1, IY) DIR = 0 : IX IX + 2, IY IY + 2 DIR = 1 : IX IX - 2, IY IY - 2
x
x
x
x
x
x
CMPM
dst-block
1010111W
1
See Table 15-8 See Table 15-8
See Table 15-9 See Table 15-9
If W = 0: AL - (IY) DIR = 0 : IY IY + 1; DIR = 1 : IY IY - 1 If W = 1: AW - (IY + 1, IY) DIR = 0 : IY IY + 2; DIR = 1 : IY IY - 2 If W = 0: AL (IX) DIR = 0 : IX IX + 1; DIR = 1 : IX IX - 1 If W = 1: AW (IX + 1, IX) DIR = 0 : IX + 2; DIR = 1 : IX IX - 2 If W = 0: (IY) AL DIR = 0 : IY IY + 1; DIR = 1 : IY IY - 1 If W = 1: (IY + 1, IY) AW DIR = 0 : IY IY + 2; DIR = 1 : IY IY - 2
x
x
x
x
x
x
PD70208H, 70216H
LDM
src-block
1010110W
1
STM
dst-block
1010101W
1
See Table 15-8
See Table 15-9
Instruction Group
Mnemonic INS
Operand(s) reg8, reg8'
Operation Code 76543210 00001111 1 1 reg' reg 76543210 00110001
Bytes 3
Clock Cycles V40HL V50HL 35-133 31-117/ 16-bit field AW 35-133
Operation
Flags AC CY V P S Z
Bit field manipulation instructions
reg8, imm4
00001111 1 1 0 0 0 reg
00111001
4
35-133 31-117/ 16-bit field AW 35-133
EXT
reg8, reg8'
00001111 1 1 reg' reg
00110011
3
34-59
26-55/ AW 16-bit field 34-59
reg8, imm4
00001111 1 1 0 0 0 reg
00111011
4
34-59
26-55/ AW 16-bit field 34-59
Input/output instructions
IN
acc, imm8
1110010W
2
9/13
9/13Note If W = 0: AL (imm8) If W = 1: AH (imm8 + 1), AL (imm8) 8/12Note If W = 0: AL (DW) If W = 1: AH (DW + 1), AL (DW) 8/12Note If W = 0: (imm8) AL If W = 1: (imm8 + 1) AH, (imm8) AL 8/12Note If W = 0: (DW) AL If W = 1: (DW + 1) AH, (DW) AL If W = 0: (IY) (DW) DIR = 0 : IY IY + 1 ; DIR = 1 : IY IY - 1 If W = 1: (IY + 1, IY) (DW + 1, DW) DIR = 0 : IY IY + 2 ; DIR = 1 : IY IY - 2 If W = 0: (DW) (IX ) DIR = 0 : IX IX + 1 ; DIR = 1 : IX IX - 1 If W = 1: (DW + 1, DW) (IX + 1, IX) DIR = 0 : IX IX + 2 ; DIR = 1 : IX IX - 2
Primitive input/output instructions
Data Sheet U13225EJ4V0DS00
acc, DW
1110110W
1
8/12
OUT
imm8, acc
1110011W
2
8/12
DW, acc
1110111W
1
8/12
INM
dst-block, DW
0110110W
1
See See Table Table 15-8 15-9
OUTM
DW, src-block
0110111W
1
See See Table Table 15-8 15-9
PD70208H, 70216H
Note
In case of IN/OUT instruction to internal DMAU, the number of word processing clock cycles applied is always that to the right of "/".
43
Addition/subtraction instructions
44
Data Sheet U13225EJ4V0DS00
Instruction Group
Mnemonic ADD
Operand(s) reg, reg' mem, reg reg, mem reg, imm mem, imm acc, imm
Operation Code 76543210 0000001W 0000000W 0000001W 100000sW 100000sW 0000010W 76543210 1 1 reg reg' mod reg mem mod reg mem 1 1 0 0 0 reg mod 0 0 0 mem
Bytes 2 2-4 2-4 3-4 3-6 2-3
Clock Cycles V40HL V50HL 2 13/21 10/14 4 15/23 4 2 13/21 10/14 4 15/23 4 reg reg + reg' (mem) (mem) + reg reg reg + (mem) reg reg + imm (mem) (mem) + imm
Operation x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
Flags AC CY V x x x x x x x x x x x x x x x x x x x x x x x x P x x x x x x x x x x x x x x x x x x x x x x x x S x x x x x x x x x x x x x x x x x x x x x x x x Z x x x x x x x x x x x x x x x x x x
If W = 0: AL AL + imm If W = 1: AW AW + imm reg reg + reg'+ CY (mem) (mem) + reg + CY reg reg + (mem) + CY reg reg + imm + CY (mem) (mem) + imm + CY If W = 0: AL AL + imm + CY If W = 1: AW AW + imm + CY reg reg - reg' (mem) (mem) - reg reg reg - (mem) reg reg - imm (mem) (mem) - imm If W = 0: AL AL - imm If W = 1: AW AW - imm reg reg - reg'- CY (mem) (mem) - reg - CY reg reg - (mem) - CY reg reg - imm - CY (mem) (mem) - imm - CY If W = 0: AL AL - imm - CY If W = 1: AW AW imm- CY
ADDC
reg, reg' mem, reg reg, mem reg, imm mem, imm acc, imm
0001001W 0001000W 0001001W 100000s W 100000sW 0001010W
1 1 reg reg' mod reg mem mod reg mem 1 1 0 1 0 reg mod 0 1 0 mem
2 2-4 2-4 3-4 3-6 2-3
2 13/21 10/14 4 15/23 4
2 13/21 10/14 4 15/23 4
SUB
reg, reg' mem, reg reg, mem reg, imm mem, imm acc, imm
0010101W 0010100W 0010101W 100000sW 100000sW 0010110W
1 1 reg reg' mod reg mem mod reg mem 1 1 1 0 1 reg mod 1 0 1 mem
2 2-4 2-4 3-4 3-6 2-3
2 13/21 10/14 4 15/23 4
2 13/21 10/14 4 15/23 4
PD70208H, 70216H
SUBC
reg, reg' mem, reg reg, mem reg, imm mem, imm acc, imm
0001101W 0001100W 0001101W 100000sW 100000sW 0001110W
1 1 reg reg' mod reg mem mod reg mem 1 1 0 1 1 reg mod 0 1 1 mem
2 2-4 2-4 3-4 3-6 2-3
2 13/21 10/14 4 15/23 4
2 13/21 10/14 4 15/23 4
x x x x x x
Instruction Group
Mnemonic ADD4S
Operand(s)
Operation Code 76543210 00001111 76543210 00100000
Bytes 2
Clock Cycles V40HL V50HL
Operation U x x x
Flags AC CY V U P U S U Z x x x
19 x n 19 x n dst BCD string dst BCD string + src BCD string* +7 +7 19 x n 19 x n dst BCD string dst BCD string - src BCD string* +7 +7 19 x n 19 x n dst BCD string - src BCD string* +7 +7 13 13 ALL reg Upper Lower mem Upper Lower reg Upper Lower mem Upper Lower
SUB4S BCD operation instructions
00001111
00100010
2
U
U
U
U
CMP4S
00001111
00100110
2
U
U
U
U
ROL4
reg8
00001111 1 1 0 0 0 reg
00101000
3
mem8
00001111 mod 0 0 0 mem
00101000
3-5
25
25 ALL
ROR4
reg8
00001111 1 1 0 0 0 reg
00101010
3
17
17 ALL
Increment/decrement instructions
Data Sheet U13225EJ4V0DS00
mem8
00001111 mod 0 0 0 mem
00101010
3-5
29
29 ALL
INC
reg8 mem reg16
11111110 1111111W 0 1 0 0 0 reg 11111110 1111111W 0 1 0 0 1 reg
1 1 0 0 0 reg mod 0 0 0 mem
2 2-4 1
2 13/21 2 2 13/21 2
2 13/21 2 2 13/21 2
reg8 reg8 + 1 (mem) (mem) + 1 reg16 reg16 + 1 reg8 reg8 - 1 (mem) (mem) - 1 reg16 reg16 - 1
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
DEC
reg8 mem reg16
1 1 0 0 1 reg mod 0 0 1 mem
2 2-4 1
PD70208H, 70216H
n: 1/2 the number of BCD digits * The number of BCD digits is given by the CL register: a value between 1 and 254 can be set.
45
Multiplication instructions
46
Data Sheet U13225EJ4V0DS00
Instruction Group
Mnemonic MULU
Operand(s) reg8
Operation Code 76543210 11110110 76543210 1 1 1 0 0 reg
Bytes 2
Clock Cycles V40HL V50HL 21-22 21-22
Operation AW AL x reg8 AH = 0: CY 0, V 0 AH 0: CY 1, V 1 AW AL x (mem8) AH = 0: CY 0, V 0 AH 0: CY 1, V 1 DW, AW AW x reg16 DW = 0: CY 0, V 0 DW 0: CY 1, V 1 DW, AW AW x (mem16) DW = 0: CY 0, V 0 DW 0: CY 1, V 1 AW AL x reg8 AH = AL sign extension: CY 0, V 0 AH AL sign extension: CY 1, V 1 AW AL x (mem8) AH = AL sign extension: CY 0, V 0 AH AL sign extension: CY 1, V 1 DW, AW AW x reg16 DW = AW sign extension: CY 0, V 0 DW AW sign extension: CY 1, V 1 DW, AW AW x (mem16) DW = AW sign extension: CY 0, V 0 DW AW sign extension: CY 1, V 1 reg16 reg16' x imm8 Product 16 bits : CY 0, V 0 Product > 16 bits : CY 1, V 1 reg16 (mem16) x imm8 Product 16 bits : CY 0, V 0 Product > 16 bits : CY 1, V 1 reg16 reg16' x imm16 Product 16 bits : CY 0, V 0 Product > 16 bits : CY 1, V 1 reg16 (mem16) x imm16 Product 16 bits : CY 0, V 0 Product > 16 bits : CY 1, V 1 U x
Flags AC CY V x P U S U Z U
mem8
11110110
mod 1 0 0 mem
2-4
26-27
26-27
U
x
x
U
U
U
reg16
11110111
1 1 1 0 0 reg
2
29-30
29-30
U
x
x
U
U
U
mem16
11110111
mod 1 0 0 mem
2-4
38-39 34-35/ 38-39 33-39 33-39
U
x
x
U
U
U
MUL
reg8
11110110
1 1 1 0 1 reg
2
U
x
x
U
U
U
mem8
11110110
mod 1 0 1 mem
2-4
38-44
38-44
U
x
x
U
U
U
reg16
11110111
1 1 1 0 1 reg
2
41-47
41-47
U
x
x
U
U
U
mem16
11110111
mod 1 0 1 mem
2-4
50-56 46-52/ 50-56 28-34 28-34
U
x
x
U
U
U
reg16, (reg16',)Note imm8 reg16, mem16, imm8 reg16, (reg16',)Note imm16 reg16, mem16, imm16
01101011
11
reg reg'
3
U
x
x
U
U
U
PD70208H, 70216H
01101011
mod reg mem
3-5
37-43 33-39/ 37-43 36-42 36-42
U
x
x
U
U
U
01101001
11
reg reg'
4
U
x
x
U
U
U
01101001
mod reg mem
4-6
45-51 41-47/ 45-51
U
x
x
U
U
U
Note The 2nd operand can be omitted, in which case the same register as the 1st operand is taken as being specified.
Instruction Group
Mnemonic DIVU
Operand(s) reg8
Operation Code 76543210 11110110 76543210 1 1 1 1 0 reg
Bytes 2
Clock Cycles V40HL V50HL 19 19
Operation temp AW If temp / reg8 FFH AH temp%reg8, AL temp / reg8 If temp / reg8 > FFH TA (001H, 000H), TC (003H, 002H) SP SP - 2, (SP + 1, SP) PSW, IE 0, BRK 0 SP SP - 2, (SP + 1, SP) PS, PS TC SP SP - 2, (SP + 1, SP) PC, PC TA temp AW If temp / (mem8) FFH AH temp%(mem8), AL temp / (mem8) If temp / (mem8) > FFH TA (001H, 000H), TC (003H, 002H) SP SP - 2, (SP + 1, SP) PSW, IE 0, BRK 0 SP SP - 2, (SP + 1, SP) PS, PS TC SP SP - 2, (SP + 1, SP) PC, PC TA temp DW, AW If temp / reg16 FFFFH DW temp%reg16, AW temp / reg16 If temp / reg16 > FFFFH TA (001H, 000H), TC (003H, 002H) SP SP - 2, (SP + 1, SP) PSW, IE 0, BRK 0 SP SP - 2, (SP + 1, SP) PS, PS TC SP SP - 2, (SP + 1, SP) PC, PC TA temp DW, AW If temp / (mem16) FFFFH DW temp%(mem16), AW temp / (mem16) If temp / (mem16) > FFFFH TA (001H, 000H), TC (003H, 002H) SP SP - 2, (SP + 1, SP) PSW, IE 0, BRK 0 SP SP - 2, (SP + 1, SP) PS, PS TC SP SP - 2, (SP + 1, SP) PC, PC TA U U
Flags AC CY V U P U S U Z U
mem8
11110110
mod 1 1 0 mem
2-4
24
24
U
U
U
U
U
U
Unsigned division instructions
Data Sheet U13225EJ4V0DS00
reg16
11110111
1 1 1 1 0 reg
2
25
25
U
U
U
U
U
U
mem16
11110111
mod 1 1 0 mem
2-4
34
30/34
U
U
U
U
U
U
PD70208H, 70216H
47
Signed division instructions
48
Data Sheet U13225EJ4V0DS00
Instruction Group
Mnemonic DIV
Operand(s) reg8
Operation Code 76543210 11110110 76543210 1 1 1 1 1 reg
Bytes 2
Clock Cycles V40HL V50HL 29-34 29-34
Operation temp AW If temp / reg8 > 0 and temp / reg8 7FH or temp / reg8 < 0 and temp / reg8 > 0 - 7FH -1 AH temp%reg8, AL temp / reg8 If temp / reg8 > 0 and temp / reg8 > 7FH or temp / reg8 < 0 and temp / reg8 0 - 7FH -1 TA (001H, 000H), TC (003H, 002H) SP SP - 2, (SP + 1, SP) PSW, IE 0, BRK 0 SP SP - 2, (SP + 1, SP) PS, PS TC SP SP - 2, (SP + 1, SP) PC, PC TA temp AW If temp / (mem8) > 0 and temp / (mem8) 7FH or temp / (mem8) < 0 and temp / (mem8) > 0 - 7FH -1 AH temp%(mem8), AL temp /(mem8) If temp / (mem8) > 0 and temp / (mem8) > 7FH or temp / (mem8) < 0 and temp / (mem8) 0 - 7FH -1 TA (001H, 000H), TC (003H, 002H) SP SP - 2, (SP + 1, SP) PSW, IE 0, BRK 0 SP SP - 2, (SP + 1, SP) PS, PS TC SP SP - 2, (SP + 1, SP) PC, PC TA temp DW, AW If temp / reg16 > 0 and temp / reg16 7FFFH or temp / reg16 < 0 and temp / reg16 > 0 - 7FFFH -1 DW temp%reg16, AW temp / reg16 If temp / reg16 > 0 and temp / reg16 > 7FFFH or temp / reg16 < 0 and temp / reg16 0 - 7FFFH -1 TA (001H, 000H), TC (003H, 002H) SP SP - 2, (SP + 1, SP) PSW, IE 0, BRK 0 SP SP - 2, (SP + 1, SP) PS, PS TC SP SP - 2, (SP + 1, SP) PC, PC TA U U
Flags AC CY V U P U S U Z U
mem8
11110110
mod 1 1 1 mem
2-4
34-39
34-39
U
U
U
U
U
U
reg16
11110111
1 1 1 1 1 reg
2
38-43
38-43
U
U
U
U
U
U
PD70208H, 70216H
mem16
11110111
mod 1 1 1 mem
2-4
47-52
43-48/ temp DW, AW 47-52 If temp / (mem16) > 0 and temp / (mem16) 7FFFH or temp / (mem16) < 0 and temp / (mem16) > 0 - 7FFFH -1 DW temp%(mem16), AW temp / (mem16) If temp / (mem16) > 0 and temp / (mem16) > 7FFFH or temp / (mem16) < 0 and temp / (mem16) 0 - 7FFFH -1 TA (001H, 000H), TC (003H, 002H) SP SP - 2, (SP + 1, SP) PSW, IE 0, BRK 0
U
U
U
U
U
U
Instruction Group
Mnemonic ADJBA
Operand(s)
Operation Code 76543210 00110111 76543210
Bytes 1
Clock Cycles V40HL V50HL 7 7
Operation If AL 0FH > 9 or AC = 1: AL AL + 6 AH AH + 1, AC 1, CY AC, AL AL If AL 0FH > 9 or AC = 1 AL AL + 6, CY CY AC , AC 1 If AL > 9FH or CY = 1 AL AL + 60H, CY 1 If AL 0FH > 9 or AC = 1 AL AL - 6, AH AH - 1 , AC 1 CY AC, AL AL 0FH If AL 0FH > 9 or AC = 1 AL AL -6, CY CY AC , AC 1 If AL > 9FH or CY = 1 AL AL - 60H, CY 1 AH AL / 0AH, AL AL%0AH AL AH x 0AH + AL, AH 0 If AL < 80H: AH 0, otherwise: AH FFH If AW < 8000H: DW 0, otherwise: DW FFFFH reg - reg' (mem) - reg reg - (mem) reg - imm (mem) - imm If W = 0: AL - imm If W = 1: AW - imm reg reg (mem) (mem) reg reg + 1 (mem) (mem) + 1 x x x x x x x x x x x x x x x x x 0FH x x x
Flags AC CY V U P U x S U x Z U x
BCD adjustment instructions
ADJ4A
00100111
1
3
3
U
ADJBS
00111111
1
7
7
x
x
U
U
U
U
ADJ4S
00101111
1
3
3
x
x
U
x
x
x
Comparison instructions
Complement operation instructions
Data Sheet U13225EJ4V0DS00
Data conversion instructions
CVTBD CVTDB CVTBW CVTWL CMP reg, reg' mem, reg reg, mem reg, imm mem, imm acc, imm
11010100 11010101 10011000 10011001 0011101W 0011100W 0011101W 100000sW 100000sW 0011110W
0 0 00 1 0 1 0 0 0 00 1 0 1 0
2 2 1 1
15 7 2 4-5 2 10/14 10/14 4 12/16 4
15 7 2 4-5 2 10/14 10/14 4 12/16 4
U U
U U
U U
x x
x x
x x
11
reg reg'
2 2-4 2-4 3-4 3-6 2-3
x x x x x x
x x x x x x
x x x x x x
x x x x x
mod reg mem mod reg mem 1 1 1 1 1 reg mod 1 1 1 mem
PD70208H, 70216H
x
NOT
reg mem
1111011W 1111011W 1111011W 1111011W
1 1 0 1 0 reg mod 0 1 0 mem 1 1 0 1 1 reg mod 0 1 mem
2 2-4 2 2-4
2 13/21 2 13/21
2 13/21 2 13/21
NEG
reg mem
x x
x x
x x
x x
49
TEST
reg, reg' mem, reg reg, mem reg, imm mem, imm acc, imm
1000010W 1000010W
11
reg' reg
2 2-4
reg
mod reg mem
9/13
9/13
(mem)
1111011W 1111011W 1010100W
11000 mod 0 0 0
reg mem
3-4 3-6 2-3
4 10/14 4
4 10/14 4
reg
imm imm
(mem)
If W = 0: AL imm8 If W = 1: AW imm16 reg reg reg' reg
AND
reg, reg' mem, reg reg, mem
0010001W 0010000W 0010001W 1000000W 1000000W 0010010W
11
reg
reg' mem mem reg mem
2 2-4 2-4 3-4 3-6 2-3
2 13/21 10/14 4 15/23 4
2 13/21 10/14 4 15/23 4
mod reg mod reg 11100 mod 1 0 0
(mem) (mem) reg reg reg reg
Logical operation instructions
reg, imm mem, imm acc, imm
(mem) (mem)
If W = 0: AL AL imm8 If W = 1: AW AW imm16 reg reg reg' (mem) (mem) reg reg reg (mem) reg reg imm (mem) (mem) imm If W = 0: AL AL imm8 If W = 1: AW AW imm16 reg reg reg' (mem) (mem) reg reg reg (mem) reg reg imm (mem) (mem) imm If W = 0: AL AL imm8 If W = 1: AW AW imm16
OR
reg, reg' mem, reg reg, mem reg, imm mem, imm acc, imm
0000101W 0000100W 0000101W 1000000W 1000000W 0000110W
11
reg
reg' mem mem reg mem
2 2-4 2-4 3-4 3-6 2-3
2 13/21 10/14 4 15/23 4
2 13/21 10/14 4 15/23 4
mod reg mod reg 11001 mod 0 0 1
XOR
reg, reg' mem, reg reg, mem reg, imm mem, imm acc, imm
0011001W 0011000W 0011001W 1000000W 1000000W 0011010W
11
reg
reg' mem mem reg mem
2 2-4 2-4 3-4 3-6 2-3
2 13/21 10/14 4 15/23 4
2 13/21 10/14 4 15/23 4
mod reg mod reg 11110 mod 1 1 0

50
Data Sheet U13225EJ4V0DS00
Instruction Group
Mnemonic
Operand(s)
Operation Code 76543210 76543210
Bytes
Clock Cycles V40HL V50HL 2 2 reg' reg
Operation U0 U 0
Flags AC CY V 0 0 P x x x x x x x x x x x x x x x x x x x x x x x S x x x x x x x x x x x x x x x x x x x x x x x Z x x x x x x x x x x x x x x x x x
U U U
0 0 0
0 0 0
U U U U imm U U
0 0 0 0 0 0
0 0 0 0 0 0
(mem) imm
U U U U U U
0 0 0 0 0 0
0 0 0 0 0 0
PD70208H, 70216H
U U U U U U
0 0 0 0 0 0
0 0 0 0 0 0
x x x x x x
Instruction Group
Mnemonic TEST1
Operand(s) reg8, CL
Operation Code 76543210 00010000 76543210 1 1 0 0 0 reg
Bytes 3
Clock Cycles V40HL V50HL 3 3
Operation reg8 bit NO.CL = 0 : Z 1 reg8 bit NO.CL = 1 : Z 0 (mem8) bit NO.CL = 0 : Z 1 (mem8) bit NO.CL = 1 : Z 0 reg16 bit NO.CL = 0 : Z 1 reg16 bit NO.CL = 1 : Z 0 (mem16) bit NO.CL = 0 : Z 1 (mem16) bit NO.CL = 1 : Z 0 reg8 bit NO.imm3 = 0 : Z 1 reg8 bit NO.imm3 = 1 : Z 0 (mem8) bit NO.imm3 = 0 : Z 1 (mem8) bit NO.imm3 = 1 : Z 0 reg16 bit NO.imm4 = 0 : Z 1 reg16 bit NO.imm4 = 1 : Z 0 (mem16) bit NO.imm4 = 0 : Z 1 (mem16) bit NO.imm4 = 1 : Z 0 reg8 bit NO.CL reg8 bit NO.CL (mem8) bit NO.CL (mem8) bit NO.CL reg16 bit NO.CL reg16 bit NO.CL (mem16) bit NO.CL (mem16) bit NO.CL reg8 bit NO.imm3 reg8 bit NO.imm3 (mem8) bit NO.imm3 (mem8) bit NO.imm3 reg16 bit NO.imm4 reg16 bit NO.imm4 (mem16) bit NO.imm4 (mem16) bit NO.imm4 U 0
Flags AC CY V 0 P U S U Z x x x x x x x x
mem8, CL
0000
mod 0 0 0 mem
3-5
7
7
U
0
0
U
U
reg16, CL
0001
1 1 0 0 0 mem
3
3
3
U
0
0
U
U
mem16, CL
0001
mod 0 0 0 mem
3-5
11
7/11
U
0
0
U
U
reg8, imm3 Bit manipulation instructions
1000
1 1 0 0 0 reg
4
4
4
U
0
0
U
U
mem8, imm3
1000
mod 0 0 0 mem
4-6
8
8
U
0
0
U
U
Data Sheet U13225EJ4V0DS00
reg16, imm4
1001
1 1 0 0 0 reg
4
4
4
U
0
0
U
U
mem16, imm4
1001
mod 0 0 0 mem
4-6
12
8/12
U
0
0
U
U
NOT1
reg8, CL mem8, CL reg16, CL mem16, CL reg8, imm3 mem8, imm3 reg16, imm4 mem16, imm4
0110 0110 0111 0111 1110 1110 1111 1111
1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem
3 3-5 3 3-5 4 4-6 4 4-6
4 10 4 18 5 11 5 19
4 10 4 10/18 5 11 5 11/19
PD70208H, 70216H
2nd byte*
3rd byte*
* 1st byte = 0FH
NOT1
CY
11110101
1
2
2
CY CY
x
51
Bit manipulation instructions
52
Data Sheet U13225EJ4V0DS00
Instruction Group
Mnemonic CLR1
Operand(s) reg8, CL mem8, CL reg16, CL mem16, CL reg8, imm3 mem8, imm3 reg16, imm4 mem16, imm4
Operation Code 76543210 00010010 0010 0011 0011 1010 1010 1011 1011 0100 0100 0101 0101 1100 1100 1101 1101 76543210 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 mem mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem 1 1 0 0 0 reg mod 0 0 0 mem
Bytes 3 3-5 3 3-5 4 4-6 4 4-6 3 3-5 3 3-5 4 4-6 4 4-6
Clock Cycles V40HL V50HL 5 11 5 19 6 12 6 20 4 10 4 18 5 11 5 19 5 11 5 11/19 6 12 6 12/20 4 10 4 10/18 5 11 5 11/19 reg8 bit NO.CL 0 (mem8) bit NO.CL 0 reg16 bit NO.CL 0 (mem16) bit NO.CL 0 reg8 bit NO.imm3 0
Operation
Flags AC CY V P S Z
(mem8) bit NO.imm3 0 reg16 bit NO.imm4 0 (mem16) bit NO.imm4 0 reg8 bit NO.CL 1 (mem8) bit NO.CL 1 reg16 bit NO.CL 1 (mem16) bit NO.CL 1 reg8 bit NO.imm3 1 (mem8) bit NO.imm3 1 reg16 bit NO.imm4 1 (mem16) bit NO.imm4 1
SET1
reg8, CL mem8, CL reg16, CL mem16, CL reg8, imm3 mem8, imm3 reg16, imm4 mem16, imm4
2nd byte*
3rd byte*
* 1st byte = 0FH
CLR1
CY DIR
11111000 11111100 11111001 11111101
1 1 1 1
2 2 2 2
2 2 2 2
CY 0 DIR 0 CY 1 DIR 1
PD70208H, 70216H
0
SET1
CY DIR
1
Instruction Group
Mnemonic SHL
Operand(s) reg, 1
Operation Code 76543210 1101000W 76543210 1 1 1 0 0 reg
Bytes 2
Clock Cycles V40HL V50HL 6 6
Operation CY reg MSB, reg reg x 2 If reg MSB CY: V 1 If reg MSB = CY: V 0 CY (mem) MSB, (mem) (mem) x 2 If (mem) MSB CY: V 1 If (mem) MSB = CY: V 0 temp CL, while temp 0 the following operation are repeated: CY reg MSB, reg reg x 2 temp temp - 1 temp CL, while temp 0 the following operation are repeated: CY (mem) MSB, (mem) (mem) x 2 temp temp - 1 temp imm8, while temp 0 the following operations are repeated: CY reg MSB, reg reg x 2 temp temp - 1 temp imm8, while temp 0 the following operations are repeated: CY (mem) MSB, (mem) (mem) x 2 temp temp - 1 U x
Flags AC CY V x P x S x Z x
mem, 1
1101000W
mod 1 0 0 mem
2-4
13/21
13/21
U
x
x
x
x
x
reg, CL Shift instructions
1101001W
1 1 1 0 0 reg
2
7+n
7+n
U
x
U
x
x
x
mem, CL
1101001W
mod 1 0 0 mem
2-4
16/24 +n
16/24 +n
U
x
U
x
x
x
Data Sheet U13225EJ4V0DS00
reg, imm8
1100000W
1 1 1 0 0 reg
3
7+n
7+n
U
x
U
x
x
x
mem, imm8
1100000W
mod 1 0 0 mem
3-5
16/24 +n
16/24 +n
U
x
U
x
x
x
n: Number of shifts
PD70208H, 70216H
53
Shift instructions
54
Data Sheet U13225EJ4V0DS00
Instruction Group
Mnemonic SHR
Operand(s) reg, 1
Operation Code 76543210 1101000W 76543210 1 1 1 0 1 reg
Bytes 2
Clock Cycles V40HL V50HL 6 6
Operation CY reg LSB, reg reg / 2 If reg MSB bit after reg MSB : V 1 If reg MSB = bit after reg MSB : V 0 CY (mem) LSB, (mem) (mem) / 2 If (mem) MSB bit after (mem) MSB : V 1 If (mem) MSB = bit after (mem) MSB : V 0 temp CL, while temp 0 the following operations are repeated: CY reg LSB, reg reg / 2 temp temp - 1 temp CL, while temp 0 the following operations are repeated: CY (mem) LSB, (mem) (mem) / 2 temp temp - 1 temp imm8, while temp 0 the following operations are repeated: CY reg LSB, reg reg / 2 temp temp - 1 temp imm8, while temp 0 the following operations are repeated: CY (mem) LSB,(mem) (mem) / 2 temp temp - 1 U x
Flags AC CY V x P x S x Z x
mem, 1
1101000W
mod 1 0 1 mem
2-4
13/21
13/21
U
x
x
x
x
x
reg, CL
1101001W
1 1 1 0 1 reg
2
7+n
7+n
U
x
U
x
x
x
mem, CL
1101001W
mod 1 0 1 mem
2-4
16/24 +n
16/24 +n
U
x
U
x
x
x
reg, imm8
1100000W
1 1 1 0 1 reg
3
7+n
7+n
U
x
U
x
x
x
mem, imm8
1100000W
mod 1 0 1 mem
3-5
16/24 +n
16/24 +n
U
x
U
x
x
x
PD70208H, 70216H
n: Number of shifts
Instruction Group
Mnemonic SHRA
Operand(s) reg, 1
Operation Code 76543210 1101000W 76543210 1 1 1 1 1 reg
Bytes 2
Clock Cycles V40HL V50HL 6 6
Operation CY reg LSB, reg reg / 2, V 0 MSB of operand is unchanged. CY (mem) LSB,(mem) (mem) / 2, V 0 MSB of operand is unchanged. temp CL, while temp 0 the following operations are repeated: CY reg LSB, reg reg / 2 temp temp - 1, MSB of operand is unchanged. temp CL, while temp 0 the following operations are repeated: CY (mem) LSB, (mem) (mem) / 2 temp temp - 1, MSB of operand is unchanged. temp imm8, while temp 0 the following operations are repeated: CY reg LSB, reg reg / 2 temp temp - 1, MSB of operand is unchanged. temp imm8, while temp 0 the following operations are repeated: CY (mem) LSB,(mem) (mem) / 2 temp temp - 1, MSB of operand is unchanged. U x
Flags AC CY V 0 P x S x Z x
mem, 1
1101000W
mod 1 1 1 mem
2-4
13/21
13/21
U
x
0
x
x
x
reg, CL
1101001W
1 1 1 1 1 reg
2
7+n
7+n
U
x
U
x
x
x
mem, CL
1101001W
mod 1 1 1 mem
2-4
16/24 +n
16/24 +n
U
x
U
x
x
x
Data Sheet U13225EJ4V0DS00
reg, imm8
1100000W
1 1 1 1 1 reg
3
7+n
7+n
U
x
U
x
x
x
mem, imm8
1100000W
mod 1 1 1 mem
3-5
16/24 +n
16/24 +n
U
x
U
x
x
x
n: Number of shifts
PD70208H, 70216H
55
Rotate instructions
56
Data Sheet U13225EJ4V0DS00
Instruction Group
Mnemonic ROL
Operand(s) reg, 1
Operation Code 76543210 1101000W 76543210 1 1 0 0 0 reg
Bytes 2
Clock Cycles V40HL V50HL 6 6
Operation CY reg MSB, reg reg x 2 + CY reg MSB CY : V 1 reg MSB = CY : V 0 CY (mem) MSB, (mem) (mem) x 2 + CY (mem) MSB CY : V 1 (mem) MSB = CY : V 0 temp CL, while temp 0 the following operations are repeated: CY reg MSB, reg reg x 2 + CY temp temp - 1 temp CL, while temp 0 the following operations are repeated: CY (mem) MSB, (mem) (mem) x 2 + CY temp temp - 1 temp imm8, while temp 0 the following operations are repeated: CY reg MSB, reg reg x 2 + CY temp temp - 1 temp imm8, while temp 0 the following operations are repeated: CY (mem) MSB, (mem) (mem) x 2 + CY temp temp - 1 x
Flags AC CY V x P S Z
mem, 1
1101000W
mod 0 0 0 mem
2-4
13/21
13/21
x
x
reg, CL
1101001W
1 1 0 0 0 reg
2
7+n
7+n
x
U
mem, CL
1101001W
mod 0 0 0 mem
2-4
16/24 +n
16/24 +n
x
U
reg, imm8
1100000W
1 1 0 0 0 reg
3
7+n
7+n
x
U
mem, imm8
1100000W
mod 0 0 0 mem
3-5
16/24 +n
16/24 +n
x
U
n: Number of shifts
PD70208H, 70216H
Instruction Group
Mnemonic ROR
Operand(s) reg, 1
Operation Code 76543210 1101000W 76543210 1 1 0 0 1 reg
Bytes 2
Clock Cycles V40HL V50HL 6 6
Operation CY reg LSB, reg reg / 2 reg MSB CY reg MSB bit after reg MSB : V 1 reg MSB = bit after reg MSB : V 0 CY (mem) LSB, (mem) (mem) / 2 (mem) MSB CY (mem) MSB bit after (mem) MSB : V 1 (mem) MSB = bit after (mem) MSB : V 0 temp CL, while CL 0 the following operations are repeated: CY reg LSB, reg reg / 2 reg MSB CY temp temp - 1 temp CL, while CL 0 the following operations are repeated: CY (mem) LSB,(mem) (mem) / 2 (mem) MSB CY temp temp - 1 temp imm8, while CL 0 the following operations are repeated: CY reg LSB,reg reg / 2 reg MSB CY temp temp - 1 temp imm8, while CL 0 the following operations are repeated: CY (mem) LSB,(mem) (mem) / 2 (mem) MSB CY temp temp - 1 x
Flags AC CY V x P S Z
mem, 1
1101000W
mod 0 0 1 mem
2-4
13/21
13/21
x
x
reg, CL
1101001W
1 1 0 0 1 reg
2
7+n
7+n
x
U
Rotate instructions
mem, CL
1101001W
mod 0 0 1 mem
2-4
16/24 +n
16/24 +n
x
U
Data Sheet U13225EJ4V0DS00
reg, imm8
1100000W
1 1 0 0 1 reg
3
7+n
7+n
x
U
mem, imm8
1100000W
mod 0 0 1 mem
3-5
16/24 +n
16/24 +n
x
U
PD70208H, 70216H
n: Number of shifts
57
Rotate instructions
58
Data Sheet U13225EJ4V0DS00
Instruction Group
Mnemonic ROLC
Operand(s) reg, 1
Operation Code 76543210 1101000W 76543210 1 1 0 1 0 reg
Bytes 2
Clock Cycles V40HL V50HL 6 6
Operation tmpcy CY, CY reg MSB reg reg x 2 + tmpcy reg MSB CY : V 1 reg MSB = CY : V 0 tmpcy CY, CY (mem) MSB (mem) (mem) x 2 + tmpcy (mem) MSB CY : V 1 (mem) MSB = CY : V 0 temp CL, while CL 0 the following operations are repeated: tmpcy CY, CY reg MSB reg reg x 2 + tmpcy temp temp - 1 temp CL, while CL 0 the following operations are repeated: tmpcy CY, CY (mem) MSB (mem) (mem) x 2 + tmpcy temp temp - 1 temp imm8, while CL 0 the following operations are repeated: tmpcy CY, CY reg MSB reg reg x 2 + tmpcy temp temp - 1 x
Flags AC CY V x P S Z
mem, 1
1101000W
mod 0 1 0 mem
2-4
13/21
13/21
x
x
reg, CL
1101001W
1 1 0 1 0 reg
2
7+n
7+n
x
U
mem, CL
1101001W
mod 0 1 0 mem
2-4
16/24 +n
16/24 +n
x
U
reg, imm8
1100000W
1 1 0 1 0 reg
3
7+n
7+n
x
U
mem, imm8
1100000W
mod 0 1 0 mem
3-5
16/24 +n
16/24 +n
temp imm8, while CL 0 the following operations are repeated: tmpcy CY, CY (mem) MSB (mem) (mem) x 2 + tmpcy temp temp - 1
x
U
PD70208H, 70216H
n: Number of shifts
Instruction Group
Mnemonic RORC
Operand(s) reg, 1
Operation Code 76543210 1101000W 76543210 1 1 0 1 1 reg
Bytes 2
Clock Cycles V40HL V50HL 6 6
Operation tmpcy CY, CY reg LSB reg reg / 2 reg MSB tmpcy reg MSB bit after reg MSB : V 1 reg MSB = bit after reg MSB : V 0 tmpcy CY, CY (mem) LSB (mem) (mem) / 2 (mem) MSB tmpcy (mem) MSB bit after (mem) MSB : V 1 (mem) MSB = bit after (mem) MSB : V 0 temp CL, while CL 0 the following operations are repeated: tmpcy CY, CY reg LSB reg reg / 2 reg MSB tmpcy temp temp - 1 temp CL, while CL 0 the following operations are repeated: tmpcy CY, CY (mem) LSB (mem) (mem) / 2 (mem) MSB tmpcy temp temp - 1 temp imm8, while CL 0 the following operations are repeated: tmpcy CY, CY reg LSB reg reg / 2 reg MSB tmpcy temp temp - 1 temp imm8, while CL 0 the following operations are repeated: tmpcy CY, CY (mem) LSB (mem) (mem) / 2 (mem) MSB tmpcy temp temp - 1 x
Flags AC CY V x P S Z
mem, 1
1101000W
mod 0 1 1 mem
2-4
13/21
13/21
x
x
reg, CL Rotate instructions
Data Sheet U13225EJ4V0DS00
1101001W
1 1 0 1 1 reg
2
7+n
7+n
x
U
mem, CL
1101001W
mod 0 1 1 mem
2-4
16/24 +n
16/24 +n
x
U
reg, imm8
1100000W
1 1 0 1 1 reg
3
7+n
7+n
x
U
PD70208H, 70216H
mem, imm8
1100000W
mod 0 1 1 mem
3-5
16/24 +n
16/24 +n
x
U
n: Number of shifts
59
Subroutine control instructions
60
Data Sheet U13225EJ4V0DS00
Instruction Group
Mnemonic CALL
Operand(s) near-proc
Operation Code 76543210 11101000 76543210
Bytes 3
Clock Cycles V40HL V50HL 20 16/20
Operation SP SP - 2, (SP + 1, SP) PC PC PC + disp SP SP - 2, (SP + 1, SP) PC PC regptr16 TA (memptr16) SP SP - 2, (SP + 1, SP) PC, PC TA SP SP - 2, (SP + 1, SP) PS, PS seg SP SP - 2, (SP + 1, SP) PC, PC offset TA (memptr32),TB (memptr32 + 2) SP SP - 2, (SP + 1, SP) PS, PS TB SP SP - 2, (SP + 1, SP) PC, PC TA PC (SP + 1, SP) SP SP + 2 PC (SP + 1, SP) SP SP + 2, SP SP + pop-value PC (SP + 1, SP) PS (SP + 3, SP + 2) PS SP + 4 PC (SP + 1, SP) PS (SP + 3, SP + 2) SP SP + 4, SP SP + pop-value
Flags AC CY V P S Z
regptr16
11111111
1 1 0 1 0 reg
2
18
14/18
memptr16
11111111
mod 0 1 0 mem
2-4
31
23/31
far-proc
10011010
5
29
21/29
memptr32
11111111
mod 0 1 1 mem
2-4
47
31/47
RET
11000011
1
19
15/19
pop-value
11000010
3
24
20/24
11001011
1
29
21/29
pop-value
11001010
3
32
24/32
PD70208H, 70216H
Instruction Group
Mnemonic PUSH
Operand(s) mem16 reg16 sreg PSW
Operation Code 76543210 11111111 0 1 0 1 0 reg 0 0 0 sreg 1 1 0 10011100 01100000 01101010 01101000 76543210 mod 1 1 0 mem
Bytes 2-4 1 1 1 1 2 3
Clock Cycles V40HL V50HL 23 10 10 10 65 9 15/23 6/10 6/10 6/10 33/65 5/9
Operation SP SP - 2 (SP + 1, SP) (mem16) SP SP - 2 (SP + 1, SP) reg16 SP SP - 2 (SP + 1, SP) sreg SP SP - 2 (SP + 1, SP) PSW Push registers on the stack SP SP - 2 (SP + 1, SP) imm8, sign of extension SP SP - 2 (SP + 1, SP) imm16 (mem16) (SP + 1, SP) SP SP + 2 reg16 (SP + 1, SP) SP SP + 2 sreg (SP + 1, SP) SP SP + 2 PSW (SP + 1, SP) SP SP + 2 Pop registers from the stack sreg : SS, DS0, DS1 R R
Flags AC CY V P S Z
Stack manipulation instructions
R imm8 imm16
10
6/10
Data Sheet U13225EJ4V0DS00
POP
mem16 reg16 sreg PSW R
10001111 0 1 0 1 1 reg 0 0 0 sreg 1 1 1 10011101 01100001 11001000 11001001
mod 0 0 0 mem
2-4 1 1 1 1 4 1
24 12 12 12 75
16/24 8/12 8/12 8/12 43/75
R
R
R
R
PREPARE imm16, imm8 DISPOSE
Note 1 Note 2 Prepare New Stack Frame 10 6/10 Dispose of Stack Frame
PD70208H, 70216H
Notes 1. If imm8 = 0 If imm8 1 2. If imm8 = 0 If imm8 1
16 21 + 16 (imm8 - 1) 12/16 {17 + 8 (imm8 - 1)} / {21 + 16 (imm8 - 1)}
61
Branch instructions
62
Data Sheet U13225EJ4V0DS00
Instruction Group
Mnemonic BR
Operand(s) near-label short-label regptr16 memptr16 far-label memptr32
Operation Code 76543210 11101001 11101011 11111111 11111111 11101010 11111111 mod 1 0 1 mem 1 1 1 0 0 reg mod 1 0 0 mem 76543210
Bytes 3 2 2 2-4 5 2-4
Clock Cycles V40HL V50HL 13 12 11 23 15 34 13 12 11 19/23 15 26/34 PC PC+ dsip PC PC+ ext-disp8 PC regptr16 PC (memptr16) PS seg PC offset PS (memptr32 + 2) PC (memptr32)
Operation
Flags AC CY V P S Z
PD70208H, 70216H
Instruction Group
Mnemonic BV BNV BC BL BNC BNL BE BZ BNE BNZ
Operand(s) short-label short-label short-label
Operation Code 76543210 01110000 0001 0010 76543210
Bytes 2 2 2
Clock CyclesNote V40HL V50HL 14/4 14/4 14/4 14/4 14/4 14/4 if V = 1 if V = 0 if CY = 1
Operation PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8
Flags AC CY V P S Z
short-label
0011
2
14/4
14/4
if CY = 0
short-label
0100
2
14/4
14/4
if Z = 1
short-label
0101
2
14/4
14/4
if Z = 0 if CY Z = 1 if CY Z = 0 if S = 1 if S = 0 if P = 1 if P = 0 if S V = 1 if S V = 0 if (S V) Z = 1 if (S V) Z = 0 CW = CW - 1 if Z = 0 and CW 0 CW = CW - 1 if Z = 1 and CW 0 CW = CW - 1 if CW 0 if CW = 0
Conditional branch instructions
BNH BH BN BP BPE BPO BLT BGE BLE BGT DBNZNE
short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label
0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 11100000
2 2 2 2 2 2 2 2 2 2 2
14/4 14/4 14/4 14/4 14/4 14/4 14/4 14/4 14/4 14/4 14/5
14/4 14/4 14/4 14/4 14/4 14/4 14/4 14/4 14/4 14/4 14/5
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
DBNZE
short-label
11100001
2
14/5
14/5
DBNZ
short-label
11100010
2
13/5
13/5
BCWZ
short-label
11100011
2
13/5
13/5
Note Condition determination: true/false
63
Interrupt instructions
64
Data Sheet U13225EJ4V0DS00
Instruction Group
Mnemonic BRK 3
Operand(s)
Operation Code 76543210 11001100 76543210
Bytes 1
Clock Cycles V40HL V50HL 50 38/50 TA (00DH, SP SP - 2, SP SP - 2, SP SP - 2,
Operation 00CH), TC (00FH, 00EH) (SP + 1, SP) PSW, IE 0, BRK 0 (SP + 1, SP) PS, PS TC (SP + 1, SP) PC, PC TA
Flags AC CY V P S Z
imm8 ( = 3)
11001101
2
50
38/50
TA (4 n + 1, 4n), TC (4n + 3, 4n + 2) n = imm8 SP SP - 2, (SP + 1, SP) PSW, IE 0, BRK 0 SP SP - 2, (SP + 1, SP) PS, PS TC SP SP - 2, (SP + 1, SP) PC, PC TA If V = 1 TA (011H, 010H), TC (013H, 012H) SP SP - 2, (SP + 1, SP) PSW, IE 0, BRK 0 SP SP - 2, (SP + 1, SP) PS, PS TC SP SP - 2, (SP + 1, SP) PC, PC TA PC (SP + 1, SP), PS (SP + 3, SP + 2), PSW (SP + 5, SP + 4), SP SP + 6 TA (4 n + 1, 4n), TC (4n + 3, 4n + 2) n = imm8 SP SP - 2, (SP + 1, SP) PSW, MD 0 MD is set to write enabled SP SP - 2, (SP + 1, SP) PS, PS TC SP SP - 2, (SP + 1, SP) PC, PC TA R R R R R R
BRKV
11001110
1
Note 1
Note 2
RETI
11001111
1
39
27/39
BRKEM
imm8
00001111
11111111
3
50
38/50
CHKIND
reg16, mem32
01100010
mod reg mem
2-4
Note 3
Note 4
If (mem32) > reg16 or (mem32 + 2) < reg16 TA (015H, 014H), TC (017H, 016H) SP SP - 2, (SP + 1, SP) PSW, IE 0, BRK 0 SP SP - 2, (SP + 1, SP) PS, PS TC SP SP - 2, (SP + 1, SP) PC, PC TA
PD70208H, 70216H
Notes 1. 2. 3. 4.
When V = 1: 52 When V = 0: 3 When V = 1: 40/52 When V = 0: 3 When interrupt condition is established When interrupt condition is not established When interrupt condition is established When interrupt condition is not established : 72 to 75 : 25 : (52 to 55)/(72 to 75) : 17/25
Instruction Group
Mnemonic HALT POLL
Operand(s)
Operation Code 76543210 11110100 10011011 11111010 11111011 11110000 76543210
Bytes 1 1 1 1 1
Clock Cycles V40HL V50HL 2 2 CPU Halt
Operation
Flags AC CY V P S Z
2 + 5n 2 + 5n Poll and wait 2 2 2 2 14 2 14 3 2 2 2 2 10/14 2 10/14 3 IE 0 IE 1
n: Number of times POLL pin is sampled
CPU control instructions
DI EI BUSLOCK FPO1 fp-op fp-op, mem FPO2 fp-op fp-op, mem NOP
Bus Lock Prefix No Operation data bus (mem) No Operation data bus (mem) No Operation
11011X X X 11011X X X 0110011X 0110011X 10010000
11YYYZ Z Z mod Y Y Y mem 11YYYZ Z Z mod Y Y Y mem
2 2-4 2 2-4 1
8080
Data Sheet U13225EJ4V0DS00
*
0 0 1 sreg 1 1 0
1
2
2
Segment override prefix
* DS0:, DS1:, PS:, and SS:.
Instruction Group
Mnemonic RETEM
Operand(s)
Operation Code 76543210 11101101 76543210 11111101
Bytes 2
Clock Cycles V40HL V50HL 39 27/39
Operation PC (SP + 1, SP), PS (SP + 3, SP + 2), R PSW (SP + 5, SP + 4), SP SP + 6, MD is set to write disabled TA (4n + 1, SP SP - 2, SP SP - 2, SP SP - 2, 4n), TC (4n + 3, 4n + 2) n = imm8 (SP + 1, SP) PSW, MD 1 (SP + 1, SP) PS, PS TC (SP + 1, SP) PC, PC TA R
Flags AC CY V R P R S R Z R
PD70208H, 70216H
CALLN
imm8
11101101
11101101
3
58
38/58
65
PD70208H, 70216H
16. ELECTRICAL SPECIFICATIONS
Applied standard The electrical characteristics shown below are applied to devices other than the old models conforming to K mask. Therefore, these characteristics are different from those conforming to the K mask. For the electrical characteristics of the K mask, consult NEC. "Others" in the table below means products conforming to the masks other than E, P, X, and M (but conforming to the L, F mask).
16.1 AT 5 V OPERATION OPERATING RANGE
E, P, X, M Mask Model Others
PD70208H, 70216H-10/12/16 PD70208H, 70216H-20
VDD = 5 V 10% -- VDD = 5 V 5%
ABSOLUTE MAXIMUM RATINGS (TA = 25 C)
Parameter Supply voltage Input voltage Clock input voltage Output voltage Operating ambient temperature Storage temperature Symbol VDD VI VK VO TA Tstg VDD = 5 V 10% (PD70208H, 70216H-10/12/16) VDD = 5 V 5% (PD70208H, 70216H-20) Test Conditions Rating -0.5 to +7.0 -0.5 to VDD + 0.3 -0.5 to VDD + 1.0 -0.5 to VDD + 0.3 -40 to +85 -65 to +150 Unit V V V V C C
Cautions 1. Do not directly connect the output pins of two or more IC products and do not directly connect the output pins to VDD or VCC and GND. However, open-drain pins or open-collector pins may be connected directly. Moreover, an external circuit whose timing is designed to avoid output collision can be connected to pins that go into a high-impedance state. 2. If even one of the above parameters exceeds the absolute maximum rating even momentarily, the quality of the program may be degraded. Absolute maximum ratings, therefore, are the values exceeding which the product may be physically damaged. Use the program keeping all the parameters within these rated values. The standards and conditions shown in DC and AC Characteristics below specify the range within which the normal operation of the product is guaranteed.
66
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
DC CHARACTERISTICS (TA = -40 to +85 C, VDD = 5 V 10% (PD70208H, 70216H-10/12/16), VDD = 5 V 5% (PD70208H, 70216H-20))
Parameter Input voltage high Symbol VIH Test Conditions E, P, X, M masks Others Except RESET RESET Except RESET, INTP1 to INTP7 RESET INTP1 to INTP7 Input voltage low VIL Except RESET RESET Clock input voltage high Clock input voltage low Output voltage high VKH VKL VOH IOH = -2.5 mA IOH = -100 A Output voltage low VOL Except END/TC : IOL = 2.5 mA END/TC Input leak current high Input leak current low INTP input current low Output leak current high Output leak current low Latch leak current high Latch leak current low Latch inversion current (L H) Latch inversion current (H L) Supply currentNote ILIH ILIL ILIPL ILOH ILOL ILLH ILLL IILH IILL IDD E, P, X, M masks On operation On standby (HALT) On standby (STOP) Others On operation On standby (HALT) On standby (STOP) 4.5 fX 1.5 fX 5.5 fX 1.5 fX VI = VDD Except INTP:VI = 0 V INTP input:VI = 0 V VO = VDD VO = 0 V VI = 3.0 V VI = 0.8 V -50 50 : IOL = 5.0 mA 10 -10 -300 10 -10 -300 300 400 -400 9.0 fX 2.5 fX 50 6.0 fX 2.2 fX 50 MIN. 2.2 0.8 VDD 2.2 TYP. MAX. VDD+0.3 VDD+0.3 VDD+0.3 Unit V
0.8 VDD 2.4 -0.5 -0.5 3.9 -0.5 0.7 VDD VDD - 0.4
VDD+0.3 VDD+0.3 +0.8 0.2VDD VDD+1.0 +0.6 V V V V
0.4
V
A A A A A A A A A
mA
A
mA
A
Note
The unit of constant values (1.5, 2.2, 2.5, 4.5, 5.5, 6.0 and 9.0) is mA/MHz.
CAPACITANCE (TA = 25 C, VDD = 0 V)
Parameter Input capacitance Input/output capacitance Symbol CI CIO Test Conditions fC = 1 MHz 0 V other than test pin. MIN. TYP. MAX. 10 15 Unit pF pF
Data Sheet U13225EJ4V0DS00
67
PD70208H, 70216H
AC CHARACTERISTICS (1) PD70208H, 70216H-10/12/16 (TA = -40 to +85 C, VDD = 5 V 10%) (1/3)
Output Pin Load Capacitance: CL = 100 pF
Parameter
Symbol
PD70208H-10 PD70216H-10
MIN. MAX. DC
PD70208H-12 PD70216H-12
MIN. 40 14 14 MAX. DC
PD70208H-16 PD70216H-16
MIN. 31.25 12 12 MAX. DC
Unit
External clock input cycle External clock input high-level width (VKH=3.0 V) External clock input low-level width (VKL=1.5 V) External clock input rise time (1.53.0 V) External clock input fall time (3.01.5 V) Clock output cycle Clock output high-level width (VOH=3.0 V) Clock output low-level width (VOL=1.5 V) Clock output rise time (1.53.0 V) Clock output fall time (3.01.5 V) CLKOUT delay time (vs. external clock) Input rise time (except external clock) (0.82.2 V) Input fall time (except external clock) (2.20.8 V) Output rise time (except CLKOUT) (0.82.2 V)
<1> tCYX <2> tXXH <3> tXXL <4> tXR <5> tXF <6> tCYK <7> tKKH <8> tKKL <9> tKR <10> tKF <11> tDXK <12> tIR <13> tIF
50 19 19
ns ns ns
5 5 100 0.5tCYK-5 0.5tCYK-5 5 5 40 15 10 15 10 DC 80 0.5tCYK-5 0.5tCYK-5
5 5 DC 62.5 0.5tCYK-5 0.5tCYK-5 5 5 35 15 10 15 10 10 20 25 20 15 40 5 7 15 7 15 15 20 7 5 40 5 5 40 40 5 5 tKKL-10 40 30 tHKA
5 5 DC
ns ns ns ns ns
5 5 20 15 10 15 10 10
ns ns ns ns ns ns ns ns ns ns
E, P, X, M masks <14> tOR Others <15> tOF <16> tSRESK <17> tHKRES <18> tDKRES <19> tSRYLK <20> tHKRYL <21> tSRYHK <22> tHKRYH <23> tSNMIK <24> tSPOLK <25> tSDK <26> tHKD <27> tDKA <28> tHKA <29> tDKP <30> tFKP <31> tSAST time Note 3 <32> tFKA <33> tDKSTH 20 25 5 15 20 15 20 15 20 15 5 5 5 5 5 tKKL-20 tHKA
Output fall time (except CLKOUT) (2.20.8 V) RESET setup time (vs. RESET hold time (vs. CLKOUT)Note 1
10
CLKOUT)Note 1
RESOUT output delay time (vs. CLKOUT) READY inactive setup time (vs. CLKOUT) READY inactive hold time (vs. CLKOUT) READY active setup time (vs. CLKOUT) READY active hold time (vs. CLKOUT) NMI setup time (vs. CLKOUT) POLL setup time (vs. CLKOUT) Data setup time (vs. CLKOUT) Data hold time (vs. CLKOUT) CLKOUT address delay timeNote 2 CLKOUT address hold time CLKOUT PS delay time CLKOUT PS float delay time Address setup time (vs. ASTB) CLKOUT address float delay CLKOUT ASTB delay time
50
5 10 15 10 20 15 20 10 5
30
ns ns ns ns ns ns ns ns ns
50
5 5
28
ns ns
50 50
5 5 tKKL-10
30 30
ns ns ns
50 40
tHKA
30 25
ns ns
Notes 1. When reset with the minimum pulse width or when guaranteeing the RESOUT output timing. 2. Specifications also corresponding to the QS0, QS1, and BUSLOCK signals, and A16/PS0-A19/PS3, UBE, BUFEN, BUFR/W, MRD, IORD, MWR, IOWR, and BS0-BS2 signals at HLDRQ/HLDAK timing. 3. Specifications also corresponding to the A16/PS0-A19/PS3, UBE, BUFEN, BUFR/W, MRD, IORD, MWR, IOWR, and BS0-BS2 signals at HLDRQ/HLDAK timing.
68
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
(1) PD70208H, 70216H-10/12/16 (TA = -40 to +85 C, VDD = 5 V 10%) (2/3)
Output Pin Load Capacitance: CL = 100 pF
Parameter CLKOUT ASTB delay time ASTB high-level width ASTB address hold time CLKOUT control 1Note 1 delay time CLKOUT control 2Note 2 delay time Address float RD delay time CLKOUT RD delay time CLKOUT RD delay time RD address delay time RD low-level width BUFEN BUFR/W delay time (read cycle) CLKOUT data output delay time CLKOUT data float delay time WR low-level width WR BUFEN or BUFR/W (write cycle) CLKOUT BS delay time CLKOUT BS delay time HLDRQ setup time (vs. CLKOUT) CLKOUT HLDAK delay time CLKOUT DMAAK delay time CLKOUT DMAAK delay time (cascade mode) WR low-level width (DMA cycle) DMA extended write DMA normal write
Symbol
PD70208H-10 PD70216H-10
MIN. MAX. 45 tKKL-10 tKKH-20 5 5 0 5 5 tCYK-40 2tCYK-40 tKKL-20 5 5 2tCYK-40 tKKL-20 5 5 15 5 5 5 2tCYK-40 tCYK-40 tKKH-30 tKKL-30 3 55 55 tCYK-15 Note 3 30 80 30 80 500 60 55 80 55 55 55 55 65 60 60 55
PD70208H-12 PD70216H-12
MIN. MAX. 35 tKKL-10 tKKH-10 5 5 0 5 5 tCYK-20 2tCYK-20 tKKL-10 5 5 2tCYK-20 tKKL-10 5 5 10 5 5 5 2tCYK-20 tCYK-20 tKKH-20 tKKL-20 3 45 45 tCYK-10 Note 4 25 65 20 80 500 50 45 70 40 40 40 40 50 45 50 45
PD70208H-16 PD70216H-16
MIN. MAX. 30 tKKL-10 tKKH-10 5 5 0 5 5 tCYK-10 2tCYK-20 tKKL-10 5 5 2tCYK-20 tKKL-10 5 5 7 5 5 5 2tCYK-20 tCYK-15 tKKH-15 tKKL-15 3 35 35 tCYK-10 Note 4 20 50 15 80 500 40 35 55 30 30 30 30 40 35 40 35
Unit
<34> tDKSTL <35> tSTST <36> tHSTA <37> tDKCT1 <38> tDKCT2 <39> tDAFRL <40> tDKRL <41> tDKRH <42> tDRHA <43> tRR <44> tDBECT <45> tDKD <46> tFKD <47> tWW <48> tDWCT <49> tDKBL <50> tDKBH <51> tSHQK <52> tDKHA <53> tDKHDA <54> tDKLDA <55> tWW1 <56> tWW2 <57> tDDARW <58> tDRHDAH <59> tDWHRH <60> tDKTCL <61> tDKTCF <62> tTCTCL <63> tDKTCH <64> tSEDK <65> tEDEDL <66> tSDQK <67> tIPIPL <68> tSRX
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
RD, WR delay time (vs. DMAAK) DMAAK delay time (vs. RD) RD delay time (vs. WR) TC output delay time (vs. CLKOUT) TC OFF delay time (vs. CLKOUT) TC low-level width TC pull-up delay time (vs. CLKOUT) END setup time (vs. CLKOUT) END low-level width DMARQ setup time (vs. CLKOUT) INTPn low-level width RXD setup time (vs. SCU internal clock)
Notes 1. 2. 3. 4.
MWR and IOWR signals in DMA cycle MWR and IOWR signals in CPU cycles and BUFEN, BUFR/W, INTAK and REFRQ signals. tKKH + 2tCYK - 10 (Reference value when a 1.1-k pull-up resistor is connected.) tKKH + 2tCYK - 5 (Reference value when a 1.1-k pull-up resistor is connected.)
Data Sheet U13225EJ4V0DS00
69
PD70208H, 70216H
(1) PD70208H, 70216H-10/12/16 (TA = -40 to +85 C, VDD = 5 V 10%) (3/3)
Output Pin Load Capacitance: CL = 100 pF
Parameter
Symbol
PD70208H-10 PD70216H-10
MIN. MAX.
PD70208H-12 PD70216H-12
MIN. 500 MAX.
PD70208H-16 PD70216H-16
MIN. 500 MAX.
Unit
RXD hold time (vs. SCU internal clock) CLKOUT SRDY delay time TOUT1 TXD delay time TCTL2 setup time (vs. CLKOUT) TCTL2 setup time (vs. TCLK) TCTL2 hold time (vs. CLKOUT) TCTL2 hold time (vs. TCLK) TCTL2 high-level width TCTL2 low-level width TOUT output delay time (vs. CLKOUT) TOUT output delay time (vs. TCLK) TOUT output delay time (vs. TCTL2) TCLK rise time TCLK fall time TCLK high-level width TCLK low-level width TCLK cycle Access intervalNote 1 MRD)Note 2
<69> tHRX <70> tDKSR <71> tDTX <72> tSGK <73> tSGTK <74> tHKG <75> tHTKG <76> tGGH <77> tGGL <78> tDKTO <79> tDTKTO <80> tDGTO <81> tTKR <82> tTKF <83> tTKTKH <84> tTKTKL <85> tCYTK <86> tAI <87> tDRQHRH <88> tWRESL
500 100 200 40 40 80 40 40 40 150 100 90 25 25 45 45 100 2tCYK-40 tKKL-30 4tCYK DC
ns 100 200 ns ns ns ns ns ns ns ns 150 100 90 25 25 ns ns ns ns ns ns ns DC ns ns ns ns
100 200 40 40 80 40 40 40 150 100 90 25 25 40 40 80 2tCYK-25 tKKL-15 4tCYK DC 30 30 62.5 2tCYK-20 tKKL-10 4tCYK 40 40 80 40 40 40
REFRQ delay time (vs.
RESET pulse width Note 3
Notes 1. Specification to guarantee read/write recovery time for I/O device. 2. Specification to guarantee that REFRQ is always later than MRD. Only guaranteed when the EREF bit of the SCTL register is 0. 3. When using internal clock generator by connecting a resonator to the X1 and X2 pins, the oscillation stabilization time must be added at power-ON. Because the oscillation stabilization time varies depending on the characteristics of the resonator and oscillator used, evaluate the oscillation stabilization time with the resonator and oscillator actually used.
70
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
(2) PD70208H, 70216H-20 (TA = -40 to +85 C, VDD = 5 V 5%) (1/3)
Output Pin Load Capacitance: CL = 100 pF
Parameter
Symbol
PD70208H-20 PD70216H-20
MIN. MAX. DC
Unit
External clock input cycle External clock input high-level width (VKH=3.0 V) External clock input low-level width (VKL=1.5 V) External clock input rise time (1.53.0 V) External clock input fall time (3.01.5 V) Clock output cycle Clock output high-level width (VOH=3.0 V) Clock output low-level width (VOL=1.5 V) Clock output rise time (1.53.0 V) Clock output fall time (3.01.5 V) CLKOUT delay time (vs. external clock) Input rise time (except external clock) (0.82.2 V) Input fall time (except external clock) (2.20.8 V) Output rise time (except CLKOUT) (0.82.2 V) Output fall time (except CLKOUT) (2.20.8 V) RESET setup time (vs. CLKOUT) Note 1
<1> tCYX <2> tXXH <3> tXXL <4> tXR <5> tXF <6> tCYK <7> tKKH <8> tKKL <9> tKR <10> tKF <11> tDXK <12> tIR <13> tIF <14> tOR <15> tOF <16> tSRESK <17> tHKRES <18> tDKRES <19> tSRYLK <20> tHKRYL <21> tSRYHK <22> tHKRYH <23> tSNMIK <24> tSPOLK <25> tSDK <26> tHKD <27> tDKA <28> tHKA <29> tDKP <30> tFKP <31> tSAST timeNote 3 <32> tFKA <33> tDKSTH <34> tDKSTL <35> tSTST
25 10 10
ns ns ns
5 5 50 0.5tCYK-5 0.5tCYK-5 5 5 20 15 10 10 10 20 10 5 7 10 7 10 10 20 7 5 5 5 5 5 tKKL-10 tHKA 25 20 20 tKKL-10 30 30 25 25 DC
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
RESET hold time (vs. CLKOUT) Note 1 RESOUT output delay time (vs. CLKOUT) READY inactive setup time (vs. CLKOUT) READY inactive hold time (vs. CLKOUT) READY active setup time (vs. CLKOUT) READY active hold time (vs. CLKOUT) NMI setup time (vs. CLKOUT) POLL setup time (vs. CLKOUT) Data setup time (vs. CLKOUT) Data hold time (vs. CLKOUT) CLKOUT address delay timeNote 2
CLKOUT address hold time CLKOUT PS delay time CLKOUT PS float delay time Address setup time (vs. ASTB) CLKOUT address float delay CLKOUT ASTB delay time CLKOUT ASTB delay time ASTB high-level width
Notes 1. When reset with the minimum pulse width or when guaranteeing the RESOUT output timing. 2. Specifications also corresponding to the QS0, QS1, and BUSLOCK signals, and A16/PS0-A19/PS3, UBE, BUFEN, BUFR/W, MRD, IORD, MWR, IOWR, and BS0-BS2 signals at HLDRQ/HLDAK timing. 3. Specifications also corresponding to the A16/PS0-A19/PS3, UBE, BUFEN, BUFR/W, MRD, IORD, MWR, IOWR, and BS0-BS2 signals at HLDRQ/HLDAK timing.
Data Sheet U13225EJ4V0DS00
71
PD70208H, 70216H
(2) PD70208H, 70216H-20 (TA = -40 to +85 C, VDD = 5 V 5%) (2/3)
Output Pin Load Capacitance: CL = 100 pF
Parameter ASTB address hold time CLKOUT control 1Note 1 delay time CLKOUT control 2Note 2 delay time Address float RD delay time CLKOUT RD delay time CLKOUT RD delay time RD address delay time RD low-level width BUFEN BUFR/W delay time (read cycle) CLKOUT data output delay time CLKOUT data float delay time WR low-level width WR BUFEN or BUFR/W (write cycle) CLKOUT BS delay time CLKOUT BS delay time HLDRQ setup time (vs. CLKOUT ) CLKOUT HLDAK delay time CLKOUT DMAAK delay time CLKOUT DMAAK delay time (cascade mode) WR low-level width (DMA cycle) DMA extended write DMA normal write RD , WR delay time (vs. DMAAK ) DMAAK delay time (vs. RD ) RD delay time (vs. WR ) TC output delay time (vs. CLKOUT ) TC OFF delay time (vs. CLKOUT ) TC low-level width TC pull-up delay time (vs. CLKOUT ) END setup time (vs. CLKOUT ) END low-level width DMARQ setup time (vs. CLKOUT ) INTPn low-level width RxD setup time (vs. SCU internal clock ) RxD hold time (vs. SCU internal clock ) CLKOUT SRDY delay time
Symbol
PD70208H-20 PD70216H-20
MIN. MAX.
Unit
<36> tHSTA <37> tDKCT1 <38> tDKCT2 <39> tDAFRL <40> tDKRL <41> tDKRH <42> tDRHA <43> tRR <44> tDBECT <45> tDKD <46> tFKD <47> tWW <48> tDWCT <49> tDKBL <50> tDKBH <51> tSHQK <52> tDKHA <53> tDKHDA <54> tDKLDA <55> tWW1 <56> tWW2 <57> tDDARW <58> tDRHDAH <59> tDWHRH <60> tDKTCL <61> tDKTCF <62> tTCTCL <63> tDKTCH <64> tSEDK <65> tEDEDL <66> tSDQK <67> tIPIPL <68> tSRX <69> tHRX <70> tDKSR
tKKH-10 5 5 0 5 5 tCYK-5 2tCYK-15 tKKL-10 5 5 2tCYK-15 tKKL-10 5 5 7 5 5 5 2tCYK-15 tCYK-15 tKKH-10 tKKL-10 3 25 25 tCYK-10 Note 3 20 40 10 60 500 500 100 25 25 45 30 25 25 25 25 28 25 30
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes 1. MWR and IOWR signals in DMA cycle 2. MWR and IOWR signals in BUFEN, BUFR/W, INTAK, REFRQ, and CPU cycles 3. tKKH + 2tCYK - 5 (reference value when a 1.1-k pull-up resistor is connected)
72
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
(2) PD70208H, 70216H-20 (TA = -40 to +85 C, VDD = 5 V 5%) (3/3)
Output Pin Load Capacitance: CL = 100 pF
Parameter
Symbol
PD70208H-20 PD70216H-20
MIN. MAX. 200 40 40 80 40 40 40 150 100 90 25 25 23 23 50 2tCYK-15 tKKL-10 4tCYK DC
Unit
TOUT1 TxD delay time TCTL2 setup time (vs. CLKOUT ) TCTL2 setup time (vs. TCLK ) TCTL2 hold time (vs. CLKOUT ) TCTL2 hold time (vs. TCLK ) TCTL2 high-level width TCTL2 low-level width TOUT output delay time (vs. CLKOUT ) TOUT output delay time (vs. TCLK ) TOUT output delay time (vs. TCTL2 ) TCLK rise time TCLK fall time TCLK high-level width TCLK low-level width TCLK cycle Access intervalNote 1 REFRQ delay time (vs. MRD )Note 2 RESET pulse widthNote 3
<71> tDTX <72> tSGK <73> tSGTK <74> tHKG <75> tHTKG <76> tGGH <77> tGGL <78> tDKTO <79> tDTKTO <80> tDGTO <81> tTKR <82> tTKF <83> tTKTKH <84> tTKTKL <85> tCYTK <86> tAI <87> tDRQHRH <88> tWRESL
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes 1. This rating is to guarantee the read/write recovery time for the I/O device. 2. This rating is to guarantee that REFRQ is always behind MRD , and guaranteed only when the EREF bit of the STCL register is 0. 3. When using internal clock generator by connecting a resonator to the X1 and X2 pins, the oscillation stabilization time must be added at power-ON. Because the oscillation stabilization time varies depending on the characteristics of the resonator and oscillator used, evaluate the oscillation stabilization time with the resonator and oscillator actually used.
Data Sheet U13225EJ4V0DS00
73
PD70208H, 70216H
RECOMMENDED OSCILLATOR The clock input circuits (1) and (2) shown below are recommended. (1) Ceramic resonator connection (TA = -40 to +85 C, VDD = 5 V 10% (PD70208H, 70216H-10/12/16), VDD = 5 V 5% (PD70208H, 70216H-20))
X1
X2
C1
C2
Cautions 1. The oscillator should be as close as possible to the X1 and X2 pins. 2. No other signal lines should pass through the area enclosed in dashed line. 3. For matching between V40HL, V50HL and resonator, the efficient evaluation should be carried out. 4. The values of the oscillator constants C1 and C2 depend on the characteristics of the resonator used. Evaluate them with the resonator actually used.
Manufacturer
Frequency (fXX) [MHz] 40 32 25 20
Product Name
Recommended Constant C1 [pF] C2 [pF] 3 5 5 10 5 5 10
Murata Mfg. Co., Ltd.
CSA40.00MXZ040 CSA32.00MXZ040 CSA25.00MXZ040 CSA20.00MXZ040 FCR32.0M2G FCR25.0M2G FCR20.0M2G
3 5 5 10 5 5 10
TDK Corp.
32 25 20
(2) External clock input
X1
X2
or
X1
X2 Open
High-speed CMOS Inverter External Clock
External Clock
High-speed CMOS Inverter
Caution The high-speed CMOS inverter should be as close as possible to the X1 and X2 pins.
74
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
16.2 AT 3 V OPERATION OPERATING RANGE
E, P, X, M Masks Others
PD70208H, 70216H-10/12/16 PD70208H, 70216H-20
VDD = 3 V 10% -- VDD = 3 V 10%
ABSOLUTE MAXIMUM RATINGS (TA = 25 C)
Parameter Supply voltage Input voltage Clock input voltage Output voltage Operating ambient temperature Storage temperature Symbol VDD VI VK VO TA Tstg VDD = 3 V 10% Test Conditions Rating -0.5 to +7.0 -0.5 to VDD + 0.3 -0.5 to VDD + 1.0 -0.5 to VDD + 0.3 -40 to +85 -65 to +150 Unit V V V V C C
Cautions 1. Do not directly connect the output pins of two or more IC products and do not directly connect the output pins to VDD or VCC and GND. However, open-drain pins or open-collector pins may be connected directly. Moreover, an external circuit whose timing is designed to avoid output collision can be connected to pins that go into a high-impedance state. 2. If even one of the above parameters exceeds the absolute maximum rating even momentarily, the quality of the program may be degraded. Absolute maximum ratings, therefore, are the values exceeding which the product may be physically damaged. Use the program keeping all the parameters within these rated values. The standards and conditions shown in DC and AC Characteristics below specify the range within which the normal operation of the product is guaranteed.
Data Sheet U13225EJ4V0DS00
75
PD70208H, 70216H
DC CHARACTERISTICS (TA = -40 to +85 C, VDD = 3 V 10%)
Parameter Input voltage high Symbol VIH Test Conditions Except RESET RESET Input voltage low VIL Except RESET RESET Clock input voltage high Clock input voltage low Output voltage high VKH VKL VOH IOH = -2.5 mA IOH = -100 A Output voltage low VOL Except END/TC : IOL = 2.5 mA END/TC Input leak current high Input leak current low INTP input current low Output leak current high Output leak current low Latch leak current high Latch leak current low Latch inversion current (L H) Latch inversion current (H L) Supply currentNote ILIH ILIL ILIPL ILOH ILOL ILLH ILLL IILH IILL IDD E, P, X, M masks On Operation On standby (HALT) On standby (STOP) Others On Operation On standby (HALT) On standby (STOP) 2.5 fX 0.9 fX 3.0 fX 0.9 fX VI = VDD VI = 0 V VI = 0 V VO = VDD VO = 0 V VI = 3.0 V VI = 0.8 V -50 50 : Except INTP : INTP input : IOL = 5.0 mA 10 -10 -300 10 -10 -300 300 400 -400 5.5 fX 1.5 fX 30 4.0 fX 1.5 fX 30 0.8 VDD -0.5 0.7 VDD VDD - 0.4 0.4 V VDD+0.5 0.2 VDD V V V MIN. 0.7 VDD 0.8 VDD -0.5 TYP. MAX. VDD+0.3 VDD+0.3 0.2 VDD V Unit V
A A A A A A A A A
mA
A
mA
A
Note The unit of constant values (0.9, 1.5, 2.5, 3.0, 4.0 and 5.5) is mA/MHz. CAPACITANCE (TA = 25C, VDD = 0 V)
Parameter Input capacitance Input/output capacitance Symbol CI CIO Test Conditions fC = 1 MHz 0 V other than test pin. MIN. TYP. MAX. 10 15 Unit pF pF
76
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
AC CHARACTERISTICS (1) PD70208H, 70216H-10/12/16 (TA = -40 to +85 C, VDD = 3 V 10%) (1/3)
Output Pin Load Capacitance: CL = 100 pF Parameter Symbol
PD70208H-10 PD70216H-10
MIN. MAX. DC
PD70208H-12 PD70216H-12
MIN. 83 30 30 MAX. DC
PD70208H-16 PD70216H-16
MIN. 62.5 20 20 MAX. DC
Unit
External clock input cycle External clock input high-level width (VKH=0.8 VDD) External clock input low-level width (VKL=0.2 VDD) External clock input rise time (0.2 VDD0.8 VDD) External clock input fall time (0.8 VDD0.2 VDD) Clock output cycle Clock output high-level width (VOH=0.7 VDD) Clock output low-level width (VOL=0.2 VDD) Clock output rise time (0.2 VDD0.7 VDD) Clock output fall time (0.7 VDD0.2 VDD) CLKOUT delay time (vs. external clock)
<1> tCYX <2> <3> <4> tXXH tXXL tXR
100 40 40
ns ns ns
10 10 200 0.5tCYK-7 0.5tCYK-7 7 7 75 20 12 20 12 25 35 5 20 30 20 30 15 20 20 5 5 5 5 5 tKKL-30 5 5 5 tKKL-10 80 65 70 80 80 75 80 25 35 5 20 30 20 30 15 20 20 5 5 5 5 5 tKKL-30 5 5 5 tKKL-10 DC 166 0.5tCYK-7 0.5tCYK-7
10 10 DC 125 0.5tCYK-7 0.5tCYK-7 7 7 65 20 12 20 12 25 35 70 5 15 25 15 25 15 20 15 5 65 5 5 70 70 5 5 tKKL-30 70 55 60 5 5 5 tKKL-10
10 10 DC
ns ns ns ns ns
<5> tXF <6> tCYK <7> <8> <9> tKKH tKKL tKR
7 7 55 20 12 20 12
ns ns ns ns ns ns ns ns ns
<10> tKF <11> tDXK
Input rise time (except external clock) (0.2 VDD0.7 VDD) <12> tIR Input fall time (except external clock) (0.7 VDD0.2 VDD) <13> tIF Output rise time (except CLKOUT) (0.2 VDD0.7 VDD) <14> tOR Output fall time (except CLKOUT) (0.7 VDD0.2 VDD) <15> tOF RESET setup time (vs. CLKOUT) Note 1 <16> tSRESK <17> tHKRES <18> tDKRES <19> tSRYLK <20> tHKRYL <21> tSRYHK <22> tHKRYH <23> tSNMIK <24> tSPOLK <25> tSDK <26> tHKD <27> tDKA <28> tHKA <29> tDKP <30> tFKP <31> tSAST time Note 3 <32> tFKA <33> tDKSTH <34> tDKSTL <35> tSTST
RESET hold time (vs. CLKOUT) Note 1 RESOUT output delay time (vs. CLKOUT) READY inactive setup time (vs. CLKOUT) READY inactive hold time (vs. CLKOUT) READY active setup time (vs. CLKOUT) READY active hold time (vs. CLKOUT) NMI setup time (vs. CLKOUT) POLL setup time (vs. CLKOUT) Data setup time (vs. CLKOUT) Data hold time (vs. CLKOUT) CLKOUT address delay time Note 2
60
ns ns ns ns ns ns ns ns ns
55
ns ns
CLKOUT address hold time CLKOUT PS delay time CLKOUT PS float delay time Address setup time (vs. ASTB) CLKOUT address float delay CLKOUT ASTB delay time CLKOUT ASTB delay time ASTB high-level width
60 60
ns ns ns
60 45 50
ns ns ns ns
Notes 1. When reset with the minimum pulse width or when guaranteeing the RESOUT output timing. 2. Specifications also corresponding to the QS0, QS1, and BUSLOCK signals, and A16/PS0-A19/PS3, UBE, BUFEN, BUFR/W, MRD, IORD, MWR, IOWR, and BS0-BS2 signals at HLDRQ/HLDAK timing. 3. Specifications also corresponding to the A16/PS0-A19/PS3, UBE, BUFEN, BUFR/W, MRD, IORD, MWR, IOWR, and BS0-BS2 signals at HLDRQ/HLDAK timing.
Data Sheet U13225EJ4V0DS00
77
PD70208H, 70216H
(1) PD70208H, 70216H-10/12/16 (TA = -40 to +85 C, VDD = 3 V 10%) (2/3)
Output Pin Load Capacitance: CL = 100 pF
Parameter ASTB address hold time CLKOUT control CLKOUT control 1Note 1 2Note 2 delay time delay time
Symbol
PD70208H-10 PD70216H-10
MIN. MAX.
PD70208H-12 PD70216H-12
MIN. tKKH-30 MAX.
PD70208H-16 PD70216H-16
MIN. tKKH-20 MAX.
Unit
<36> tHSTA <37> tDKCT1 <38> tDKCT2 <39> tDAFRL <40> tDKRL <41> tDKRH <42> tDRHA <43> tRR <44> tDBECT <45> tDKD <46> tFKD <47> tWW <48> tDWCT <49> tDKBL <50> tDKBH <51> tSHQK <52> tDKHA <53> tDKHDA <54> tDKLDA <55> tWW1 <56> tWW2 <57> tDDARW <58> tDRHDAH <59> tDWHRH <60> tDKTCL <61> tDKTCF <62> tTCTCL <63> tDKTCH <64> tSEDK <65> tEDEDL <66> tSDQK <67> tIPIPL <68> tSRX <69> tHRX <70> tDKSR
tKKH-30 5 5 0 5 5 tCYK-70 2tCYK-70 tKKL-30 5 5 2tCYK-50 tKKL-30 5 5 25 5 5 5 2tCYK-50 tCYK-50 tKKH-40 tKKL-40 5 5 5 tCYK-25 Note 3 45 140 45 100 1000 1000 150 80 80 90 80 110 80 80 80 80 95 90 90 80
ns 70 60 ns ns ns 75 70 ns ns ns ns ns 60 60 ns ns ns ns 60 60 ns ns ns 70 60 90 ns ns ns ns ns ns ns ns 60 60 ns ns ns Note 4 ns ns ns ns ns ns ns 150 ns
5 5 0 5 5 tCYK-60 2tCYK-60 tKKL-30 5 5 2tCYK-50 tKKL-30 5 5 25 5 5 5 2tCYK-50 tCYK-50 tKKH-40 tKKL-40 5 5 5 tCYK-25
80 70
5 5 0
Address float RD delay time CLKOUT RD delay time CLKOUT RD delay time RD address delay time RD low-level width BUFEN BUFR/W delay time (read cycle) CLKOUT data output delay time CLKOUT data float delay time WR low-level width WR BUFEN or BUFR/W (write cycle) CLKOUT BS delay time CLKOUT BS delay time HLDRQ setup time (vs. CLKOUT) CLKOUT HLDAK delay time CLKOUT DMAAK delay time CLKOUT DMAAK delay time (cascade mode) WR low-level width (DMA cycle) DMA extended write DMA normal write
85 80
5 5 tCYK-50 2tCYK-50 tKKL-20
70 70
5 5 2tCYK-40 tKKL-20
70 70
5 5 20
80 70 100
5 5 5 2tCYK-40 tCYK-40 tKKH-30 tKKL-30 5
RD WR delay time (vs. DMAAK) DMAAK delay time (vs. RD) RD delay time (vs. WR) TC output delay time (vs. CLKOUT) TC OFF delay time (vs. CLKOUT) TC low-level width TC pull-up delay time (vs. CLKOUT) END setup time (vs. CLKOUT) END low-level width DMARQ setup time (vs. CLKOUT) INTPn low-level width RXD setup time (vs. SCU internal clock) RXD hold time (vs. SCU internal clock) CLKOUT SRDY delay time
70 70
5 5 tCYK-15
Note 4 40 120 40 100 1000 1000 150 35 100 35 100 1000 1000
Notes 1. 2. 3. 4.
MWR and IOWR signals in DMA cycle MWR and IOWR signals in CPU cycles and BUFEN, BUFR/W, INTAK and REFRQ signals. tKKH + 2tCYK - 20 (Reference value when a 1.1-k pull-up resistor is connected) tKKH + 2tCYK - 10 (Reference value when a 1.1-k pull-up resistor is connected)
78
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
(1) PD70208H, 70216H-10/12/16 (TA = -40 to +85 C, VDD = 3 V 10%) (3/3)
Output Pin Load Capacitance: CL = 100 pF
Parameter
Symbol
PD70208H-10 PD70216H-10
MIN. MAX. 500 50 50 100 50 50 50 200 150 120 25 25 60 60 200 2tCYK-70 tKKL-50 4tCYK DC
PD70208H-12 PD70216H-12
MIN. MAX. 500 50 50 100 50 50 50 200 150 120 25 25 55 55 166 2tCYK-60 tKKL-40 4tCYK DC
PD70208H-16 PD70216H-16
MIN. MAX. 500 50 50 100 50 50 50 200 150 120 25 25 50 50 125 2tCYK-50 tKKL-30 4tCYK DC
Unit
TOUT1 TXD delay time TCTL2 setup time (vs. CLKOUT) TCTL2 setup time (vs. TCLK) TCTL2 hold time (vs. CLKOUT) TCTL2 hold time (vs. TCLK) TCTL2 high-level width TCTL2 low-level width TOUT output delay time (vs. CLKOUT) TOUT output delay time (vs. TCLK) TOUT output delay time (vs. TCTL2) TCLK rise time TCLK fall time TCLK high-level width TCLK low-level width TCLK cycle Access interval Note 1
<71> tDTX <72> tSGK <73> tSGTK <74> tHKG <75> tHTKG <76> tGGH <77> tGGL <78> tDKTO <79> tDTKTO <80> tDGTO <81> tTKR <82> tTKF <83> tTKTKH <84> tTKTKL <85> tCYTK <86> tAI <87> tDRQHRH <88> tWRESL
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
REFRQ delay time (vs. MRD)Note 2 RESET pulse width Note 3
Notes 1. Specification to guarantee read/write recovery time for I/O device. 2. Specification to guarantee that REFRQ is always later than MRD. Only guaranteed when the EREF bit of the SCTL register is 0. 3. When using internal clock generator by connecting a resonator to the X1 and X2 pins, the oscillation stabilization time must be added at power-ON. Because the oscillation stabilization time varies depending on the characteristics of the resonator and oscillator used, evaluate the oscillation stabilization time with the resonator and oscillator actually used.
Data Sheet U13225EJ4V0DS00
79
PD70208H, 70216H
(2) PD70208H, 70216H-20 (TA = -40 to +85 C, VDD = 3 V 10%) (1/3)
Output Pin Load Capacitance: CL = 100 pF
Parameter
Symbol
PD70208H-20 PD70216H-20
MIN. MAX. DC
Unit
External clock input cycle External clock input high-level width (VKH=0.8 VDD) External clock input low-level width (VKL=0.2 VDD) External clock input rise time (0.2 VDD0.8 VDD) External clock input fall time (0.8 VDD0.2 VDD) Clock output cycle Clock output high-level width (VOH=0.7 VDD) Clock output low-level width (VOL=0.2 VDD) Clock output rise time (0.2 VDD0.7 VDD) Clock output fall time (0.7 VDD0.2 VDD) CLKOUT delay time (vs. external clock) Input rise time (except external clock) (0.2 VDD0.7 VDD) Input fall time (except external clock) (0.7 VDD0.2 VDD) Output rise time (except CLKOUT) (0.2 VDD0.7 VDD) Output fall time (except CLKOUT) (0.7 VDD0.2 VDD) RESET setup time (vs. CLKOUT) Note 1
<1> tCYX <2> tXXH <3> tXXL <4> tXR <5> tXF <6> tCYK <7> tKKH <8> tKKL <9> tKR <10> tKF <11> tDXK <12> tIR <13> tIF <14> tOR <15> tOF <16> tSRESK <17> tHKRES <18> tDKRES <19> tSRYLK <20> tHKRYL <21> tSRYHK <22> tHKRYH <23> tSNMIK <24> tSPOLK <25> tSDK <26> tHKD <27> tDKA <28> tHKA <29> tDKP <30> tFKP <31> tSAST timeNote 3 <32> tFKA <33> tDKSTH <34> tDKSTL <35> tSTST
50 19 19
ns ns ns
5 5 100 0.5tCYK-7 0.5tCYK-7 7 7 45 15 10 15 10 25 25 5 15 20 15 20 15 20 15 5 5 5 5 5 tKKL-20 tHKA 50 40 45 tKKL-10 50 50 50 50 DC
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
RESET hold time (vs. CLKOUT) Note 1 RESOUT output delay time (vs. CLKOUT) READY inactive setup time (vs. CLKOUT) READY inactive hold time (vs. CLKOUT) READY active setup time (vs. CLKOUT) READY active hold time (vs. CLKOUT) NMI setup time (vs. CLKOUT) POLL setup time (vs. CLKOUT) Data setup time (vs. CLKOUT) Data hold time (vs. CLKOUT) CLKOUT address delay time Note 2
CLKOUT address hold time CLKOUT PS delay time CLKOUT PS float delay time Address setup time (vs. ASTB) CLKOUT address float delay CLKOUT ASTB delay time CLKOUT ASTB delay time ASTB high-level width
Notes 1. When reset with the minimum pulse width or when guaranteeing the RESOUT output timing. 2. Specifications also corresponding to the QS0, QS1, and BUSLOCK signals, and A16/PS0-A19/PS3, UBE, BUFEN, BUFR/W, MRD, IORD, MWR, IOWR, and BS0-BS2 signals at HLDRQ/HLDAK timing. 3. Specifications also corresponding to the A16/PS0-A19/PS3, UBE, BUFEN, BUFR/W, MRD, IORD, MWR, IOWR, and BS0-BS2 signals at HLDRQ/HLDAK timing.
80
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
(2) PD70208H, 70216H-20 (TA = -40 to +85 C, VDD = 3 V 10%) (2/3)
Output Pin Load Capacitance: CL = 100 pF
Parameter
Symbol
PD70208H-20 PD70216H-20
MIN. MAX.
Unit
ASTB address hold time CLKOUT control CLKOUT control 1Note 1 2Note 2 delay time delay time
<36> tHSTA <37> tDKCT1 <38> tDKCT2 <39> tDAFRL <40> tDKRL <41> tDKRH <42> tDRHA <43> tRR <44> tDBECT <45> tDKD <46> tFKD <47> tWW <48> tDWCT <49> tDKBL <50> tDKBH <51> tSHQK <52> tDKHA <53> tDKHDA <54> tDKLDA DMA extended write DMA normal write <55> tWW1 <56> tWW2 <57> tDDARW <58> tDRHDAH <59> tDWHRH <60> tDKTCL <61> tDKTCF <62> tTCTCL <63> tDKTCH <64> tSEDK <65> tEDEDL <66> tSDQK <67> tIPIPL <68> tSRX <69> tHRX <70> tDKSR
tKKH-20 5 5 0 5 5 tCYK-40 2tCYK-40 tKKL-20 5 5 2tCYK-40 tKKL-20 5 5 15 5 5 5 2tCYK-40 tCYK-40 tKKH-30 tKKL-30 3 55 55 tCYK-15 Note 3 30 80 30 80 500 500 100 60 55 80 55 55 55 55 65 60 60 55
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Address float RD delay time CLKOUT RD delay time CLKOUT RD delay time RD address delay time RD low-level width BUFEN BUFR/W delay time (read cycle) CLKOUT data output delay time CLKOUT data float delay time WR low-level width WR BUFEN or BUFR/W (write cycle) CLKOUT BS delay time CLKOUT BS delay time HLDRQ setup time (vs. CLKOUT ) CLKOUT HLDAK delay time CLKOUT DMAAK delay time CLKOUT DMAAK delay time (cascade mode) WR low-level width (DMA cycle)
RD , WR delay time (vs. DMAAK ) DMAAK delay time (vs. RD ) RD delay time (vs. WR ) TC output delay time (vs. CLKOUT ) TC OFF delay time (vs. CLKOUT ) TC low-level width TC pull-up delay time (vs. CLKOUT ) END setup time (vs. CLKOUT ) END low-level width DMARQ setup time (vs. CLKOUT ) INTPn low-level width RxD setup time (vs. SCU internal clock ) RxD hold time (vs. SCU internal clock ) CLKOUT SRDY delay time
Notes 1. MWR and IOWR signals in DMA cycle 2. MWR and IOWR signals in CPU cycles and BUFEN, BUFR/W, INTAK and REFRQ signals. 3. tKKH + 2tCYK - 10 (reference value when a 1.1-k pull-up resistor is connected)
Data Sheet U13225EJ4V0DS00
81
PD70208H, 70216H
(2) PD70208H, 70216H-20 (TA = -40 to +85 C, VDD = 3 V 10%) (3/3)
Output Pin Load Capacitance: CL = 100 pF
Parameter
Symbol
PD70208H-20 PD70216H-20
MIN. MAX. 200 40 40 80 40 40 40 150 100 90 25 25 45 45 100 2tCYK-40 tKKL-30 4tCYK DC
Unit
TOUT1 TxD delay time TCTL2 setup time (vs. CLKOUT ) TCTL2 setup time (vs. TCLK ) TCTL2 hold time (vs. CLKOUT ) TCTL2 hold time (vs. TCLK ) TCTL2 high-level width TCTL2 low-level width TOUT output delay time (vs. CLKOUT ) TOUT output delay time (vs. TCLK ) TOUT output delay time (vs. TCTL2 ) TCLK rise time TCLK fall time TCLK high-level width TCLK low-level width TCLK cycle Access intervalNote 1 REFRQ delay time (vs. MRD RESET pulse widthNote 3 )Note 2
<71> tDTX <72> tSGK <73> tSGTK <74> tHKG <75> tHTKG <76> tGGH <77> tGGL <78> tDKTO <79> tDTKTO <80> tDGTO <81> tTKR <82> tTKF <83> tTKTKH <84> tTKTKL <85> tCYTK <86> tAI <87> tDRQHRH <88> tWRESL
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes 1. This rating is to guarantee the read/write recovery time for the I/O device. 2. This rating is to guarantee that REFRQ is always behind MRD , and is guaranteed only when the EREF bit of the STCL register is 0. 3. When using internal clock generator by connecting a resonator to the X1 and X2 pins, the oscillation stabilization time must be added at power-ON. Because the oscillation stabilization time varies depending on the characteristics of the resonator and oscillator used, evaluate the oscillation stabilization time with the resonator and oscillator actually used.
82
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
RECOMMENDED OSCILLATOR The clock input circuits (1) and (2) shown below are recommended. (1) Ceramic resonator connection (TA = -40 to +85 C, VDD = 3 V 10%Note)
X1
X2
C1
C2
Cautions 1. The oscillator should be as close as possible to the X1 and X2 pins. 2. No other signal lines should pass through the area enclosed in dashed line. 3. V40HL, V50HL and resonator matching requires careful evaluation. 4. The values of the oscillator constants C1 and C2 depend on the characteristics of the resonator used. Evaluate them with the resonator actually used.
Manufacturer
Frequency (fXX) [MHz] 20 16
Product Name
Recommended Constant C1 [pF] C2 [pF] 10 15 - 30 - 30 - 10 15 -
Murata Mfg. Co., Ltd.
CSA20.00MXZ040Note CSA16.00MXZ040 CSA16.00MXW0C3 CSA12.5MTZ
10 15 - 30 - 30 - 10 15 -
12.5 CSA12.5MTW CSA10.0MTZ 10 CST10.0MXW TDK Corp. 20 16 10 FCR20.0M2G FCR16.0M2G FCR10.0MC
Note (2) External clock input
Use the CAS20.00MXZ040 within the range of VDD = 2.9 to 3.3 V.
X1
X2
X1
or
High-speed CMOS Inverter
X2 Open
High-speed CMOS Inverter External Clock
External Clock
Caution The high-speed CMOS inverter should be as close as possible to the X1 and X2 pins.
Data Sheet U13225EJ4V0DS00
83
PD70208H, 70216H
AC Test Input Waveform (Except X1 and X2) (at 5 V operation)
2.4 V 2.2 V 0.4 V 0.8 V Test points 2.2 V 0.8 V
AC Test Output Test Points (at 5 V operation)
2.2 V 0.8 V
Test points
2.2 V 0.8 V
AC Test Input Waveform (Except X1 and X2) (at 3 V operation)
0.8 VDD 0.7 VDD 0.4 V 0.2 VDD Test points 0.7 VDD 0.2 VDD
AC Test Output Waveform (at 3 V operation)
0.7 VDD 0.2 VDD
Test points
0.7 VDD 0.2 VDD
Load Conditions
DUT C L = 100pF
Caution If the load capacitance exceeds 100 pF due to the configuration of the circuit, the load capacitance of this device should be reduced to 100 pF or less by insertion of a buffer, etc.
84
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
Clock Timing
<4> <5>
<1> <2>
External Clock (Input) (X1)
<11> <11> <6> <7> <10> <9> <3>
CLKOUT (Output)
<8>
Reset Timing
CLKOUT (Output)
<17> <88> <16>
<16>
RESET (Input)
Note
<18>
<18>
RESOUT (Output)
Ready Timing (1)
T1 T2 T3 T4 T1
CLKOUT (Output)
<22> <21>
READY (Input)
Variation Range
Variation Range
Ready Timing (2)
T1 T2 T3 TW T4
CLKOUT (Output)
<22> <21>
<19>
READY (Input)
Variation Range
<20>
Note
Variation Range
Note Variation range
Data Sheet U13225EJ4V0DS00
85
PD70208H, 70216H
Read Timing
T4 CLKOUT (Output) <27> A16/PS0A19/PS3 (Output) <27> A16-A19 <31> <29> <28> PS0-PS3 <30> T1 T2 T3 T4
A8-A15 (Output): V40HL UBE (Output): V50HL <27> AD0-AD7 (I/O): V40HL AD0-AD15 (I/O): V50HL <33> <31> A0-A7(Output) : V40HL A0-A15(Output) : V50HL <35> <36> <28> <32> <25> D0-D7(Intput) : V40HL D0-D15(Intput): V50HL <26>
ASTB (Output) <34>
<38> Note
<38>
BUFEN (Output)
<38> <38> BUFR/W (Output) <40> MRD (Output) IORD (Output) Note <43> <42> <41> <39> <44>
BS0-BS2 (Output) <49>
Bus Status <50>
Note High-level signal is output in case of internal access. Remark A dashed line indicates high impedance.
86
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
Write Timing
T4 CLKOUT (Output) <27> A16/PS0A19/PS3 (Output)
T1
T2
T3
T4
<28> A16-A19 PS0-PS3 <29> <31>
<30>
<27>
A8-A15 (Output): V40HL UBE (Output): V50HL <27> AD0-AD7 (I/O): V40HL AD0-AD15 (I/O): V50HL A0-A7 (Output) : V40HL A0-A15 (Output) : V50HL <31> <35> ASTB (Output) <33> <38> BUFEN (Output) Note <48> <38> BUFR/W (Output) <38> <34> <36> <38> <28> <45> D0-D7 (Output) : V40HL D0-D15 (Output) : V50HL <46>
<38> MWR (Output) IOWR (Output) Note <47>
<38>
BS0-BS2 (Output) <49>
Bus Status <50>
Note High-level signal is output in case of internal access. Remark A dashed line indicates high impedance.
Data Sheet U13225EJ4V0DS00
87
PD70208H, 70216H
Status Timing
T4 CLKOUT (Output)
T1
T2
T3
T4
<27> A16/PS0A19/PS3 (Output) <27> A8-A15 (Output): V40HL UBE (Output): V50HL
<28> <29> A16-A19 PS0-PS3
<30>
<31>
<25> <27> AD0-AD7 (I/O): V40HL AD0-AD15 (I/O): V50HL <33> <31> A0-A7 (Output) : V40HL A0-A15 (Output): V50HL <36> <35> <28> <32> <26> D0-D7 (Input) : V40HL D0-D15 (Input): V50HL <42>
ASTB (Output) <34> <50>
BS0-BS2 (Output)
Bus Status
<49> Note 1 <27> <40>
<39> Note 2 <43>
<41>
QS0, QS1 (Output)
Notes 1. MRD, IORD, MWR, IOWR (all output) 2. High-level signal is output in case of internal access. Remark A dashed line indicates high impedance.
88
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
Interrupt Acknowledge Timing (V40HL)
T1 CLKOUT (Output) T2 T3 T4 T1 T2 T3 TI
A8-A15 (Output)
<32> <27> <32>
Note 1
<25> <26>
AD0-AD7 (I/O)
Note 1
Note 2 Vector Number
ASTB (Output)
<38>
INTAK (Output)
<38> <38>
BUFEN (Output)
Note 3
Note 3
BUFR/W (Output)
<27>
BUSLOCK (Output)
Notes 1. Slave address in case of interrupt from external PD71059. Invalid data in case of interrupt from internal ICU. 2. Data read as vector address in case of interrupt from external PD71059. High impedance in case of interrupt from internal ICU. * 3. Low-level output in case of interrupt from external PD71059. High-level output in case of interrupt from internal ICU. A dashed line indicates high impedance.
Remark
Data Sheet U13225EJ4V0DS00
89
PD70208H, 70216H
Interrupt Acknowledge Timing (V50HL)
T1 CLKOUT (Output)
<32>
T2
T3
TIx3
T4
<27>
T1
T2
<32>
T3
<25>
TI
<26>
AD0-AD15 (I/O)
Note 1
Note 2 Vector Number
ASTB (Output)
<38>
INTAK (Output)
<38> <38>
BUFEN (Output)
Note 3
Note 3
BUFR/W (Output)
<27>
BUSLOCK (Output)
Notes 1. Slave address in case of interrupt from external PD71059. Invalid data in case of interrupt from internal ICU. 2. Data read as vector address in case of interrupt from external PD71059. High impedance in case of interrupt from internal ICU. * 3. Low-level output in case of interrupt from external PD71059. High-level output in case of interrupt from internal ICU.
Remark A dashed line indicates high impedance.
90
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
HLDRQ/HLDAK Timing (1)
TI CLKOUT (Output) TI T4 T1
<51>
<51>
HLDRQ (Input)
<52> <52>
HLDAK (Output)
<32> <27>
Note
<32> <27>
BS0-BS2 (Output)
Note
A16/PS0 to A19/PS3, UBE, BUFEN, BUFR/W, MRD, IORD, MWR, IOWR (all output): V40HL, V50HL A8-A15 (output): V40HL AD0-AD7 (input/output): V40HL AD0-AD15 (input/output) V50HL
Remark A dashed line indicates high impedance. HLDRQ/HLDAK Timing (2)
TI CLKOUT (Output)
TI
TI
TI
T4
T1
T2
<51>
HLDRQ (Input)
<52> <6> or longer
Variation Range
HLDAK (Output)
<27>
Note
<49>
Highest-Priority Refresh Cycle or DMA Cycle
BS0-BS2 (Output)
Highest-Priority Refresh Cycle or DMA Cycle
Note
A16/PS0 to A19/PS3, UBE, BUFEN, BUFR/W, MRD, IORD, MWR, IOWR (all output): V40HL, V50HL A8-A15 (output): V40HL AD0-AD7 (input/output): V40HL AD0-AD15 (input/output) V50HL
Remark A dashed line indicates high impedance.
Data Sheet U13225EJ4V0DS00
91
PD70208H, 70216H
POLL, NMI Input Timing
Tn
CLKOUT (Output)
<24>
POLL (Input)
<23>
NMI (Input)
BUSLOCK Output Timing
CLKOUT (Output)
<27>
<27>
BUSLOCK (Output)
Access Interval
<86>
MRD (Output) IORD (Output)
<86>
<86>
MWR (Output) IOWR (Output)
<86>
92
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
Refresh Timing (V40HL)
T4 CLKOUT (Output) <27> A16/PS0A19/PS3 (Output) <27>
T1
T2
T3
T4
<28> <29> Invalid
A8-A15 (Output) <27> <28> <32>
Refresh Address
<31> Refresh Address
AD0-AD7 (I/O) <33>
<36> <35>
ASTB (Output) <34>
BUFEN (Output) <39> <40> MRD (Output) <38> <43> <38> <41>
REFRQ (Output) <49> <50>
BS0-BS2 (Output)
BS2 = 1, BS1 = 0, BS0 = 1
Remark A dashed line indicates high impedance.
Data Sheet U13225EJ4V0DS00
93
PD70208H, 70216H
Refresh Timing (V50HL)
T4 CLKOUT (Output)
<27> <28> <29> Invalid <27>
T1
T2
T3
T4
A16/PS0A19/PS3 (Output)
UBE (Output)
<27> <28> <32>
<31> Refresh Address
AD0-AD15 (I/O)
<33>
<35>
<36>
ASTB (Output)
<34>
BUFEN (Output)
<39> <40> <41>
MRD (Output)
<38> <43> <38>
REFRQ (Output)
<49> <50>
BS0-BS2 (Output)
BS2 = 1, BS1 = 0, BS0 = 1
Remark A dashed line indicates high impedance.
94
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
TCU Timing (1)
CLKOUT (Output)
<72> <74> <77> <76> <72> <74>
TCTL2 (Input)
<80>
Note
<78>
TOUTn (Output) (n=1, 2)
Note Applies to TOUT2 output.
TCU Timing (2)
<81> <82> <83> <85>
TCLK (Input)
<84>
<75> <76>
<73> <75>
<73>
TCTL2 (Input)
<77>
Note
<80>
<79>
TOUTn (Output) (n=1, 2)
Note Applies to TOUT2 output.
Data Sheet U13225EJ4V0DS00
95
PD70208H, 70216H
SCU Timing
RxD (Input)
<68> <69>
TOUT1 (Output) 16 Cycles or 64 Cycles 16 Cycles or 64 Cycles
TxD (Output)
<71>
CLKOUT (Output)
<70>
SRDY (Output)
96
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
DMAU Timing (1)
T4 CLKOUT (Output) <49> BS0-BS2 (Output) <33> <35> ASTB (Output) <27> A16/PS0A19/PS3 (Output) <27> A8-A15 (Output): V40HL UBE (Output): V50HL <27> AD0-AD7 (I/O): V40HL AD0-AD15 (I/O): V50HL <53> DMAAK (Output) <39> <40> <57> MRD (Output) IORD (Output) <37> <57> <43> <41> <58> <53> <28> <32> <34> <29> <28> Bus Status <36> <50> T1 T2 T3 T4
<37>
<37> <55> <56> <59>
MWR (Output) IOWR (Output)
Note
Note Low-level signal is output in extended write mode. Remark A dashed line indicates high impedance.
Data Sheet U13225EJ4V0DS00
97
PD70208H, 70216H
DMAU Timing (2)
T1 CLKOUT (Output)
<60> <61> <63>
T2
T3
T4
TC (Input/Output)
<64> <65>
<62>
END (Input/Output)
CLKOUT (Output)
<66>
DMARQn (Input) (n=0-3)
98
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
DMAU Timing (3) (Cascade Mode) In Normal Operation:
T1 CLKOUT (Output)
<66> <66>
T4
DMARQ (Input)
<54> <54>
DMAAK (Output)
When Refresh Cycle is Inserted:
CLKOUT (Output)
DMARQ (Input)
<54> <54>
DMAAK (Output)
ICU Timing
<67>
INTPn (Input) (n=1-7)
Data Sheet U13225EJ4V0DS00
99
PD70208H, 70216H
17. PACKAGE DRAWINGS
80 PIN PLASTIC QFP (14x20)
A B
64 65
41 40
detail of lead end S CD Q R
80 1
25 24
F G H P I
M
J
K M N S L S
ITEM A MILLIMETERS 23.60.4 20.00.2 14.00.2 17.60.4 1.0 0.8 0.37 +0.08 -0.07 0.15 0.8 (T.P.) 1.80.2 0.80.2 0.17 +0.08 -0.07 0.10 2.70.1 0.10.1 55 3.0 MAX. INCHES 0.9290.016 0.795 +0.009 -0.008 0.551 +0.009 -0.008 0.6930.016 0.039 0.031 0.015 +0.003 -0.004 0.006 0.031 (T.P.) 0.071 +0.008 -0.009 0.031 +0.009 -0.008 0.007 +0.003 -0.004 0.004 0.106 +0.005 -0.004 0.0040.004 55 0.119 MAX. P80GF-80-3B9-4
NOTE 1. Controlling dimension millimeter.
2. Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
B C D F G H I J K L M N P Q R S
100
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
80 PIN PLASTIC TQFP (FINE PITCH) ( 12)
A B
60 61
41 40
detail of lead end
C
D
S
80 F 1 20
21
G
H
I
M
J K
P
N
L
NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition.
M
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 14.00.2 12.00.2 12.00.2 14.00.2 1.25 1.25 0.220.05 0.10 0.5 (T.P.) 1.00.2 0.50.2 0.1450.05 0.10 1.00.05 0.10.05 3 +7 -3 1.2 MAX.
Q
R
INCHES 0.5510.008 0.472 +0.009 -0.008 0.472 +0.009 -0.008 0.5510.008 0.049 0.049 0.009+0.002 -0.003 0.004 0.020 (T.P.) 0.039+0.009 -0.008 0.020+0.008 -0.009 0.006 +0.002 -0.003 0.004 0.040 +0.002 -0.003 0.0040.002 3 +7 -3 0.048 MAX. S80GK-50-9EU
Data Sheet U13225EJ4V0DS00
101
PD70208H, 70216H
68 PIN PLASTIC QFJ (950 x 950 mil)
A B
68 1
CD
G
H
J
F
E U K M N P
M
S Q S T
ITEM A B C D
MILLIMETERS 25.20.2 24.200.1 24.200.1 25.20.2 1.940.15 0.6 4.40.2 2.80.2 0.9 MIN. 3.40.1 1.27 (T.P.) 0.420.08 0.12 23.120.2 0.15 R 0.8 0.22 +0.08 -0.07
INCHES 0.9920.008 0.953 +0.004 -0.005 0.953 +0.004 -0.005 0.9920.008 0.076 +0.007 -0.006 0.024 0.173 +0.009 -0.008 0.110 +0.009 -0.008 0.035 MIN. 0.134 +0.004 -0.005 0.050 (T.P.) 0.017 +0.003 -0.004 0.005 0.910 +0.009 -0.008 0.006 R 0.031 0.009 +0.003 -0.004 P68L-50A1-3
I
NOTES 1. Controlling dimension millimeter.
E F
2. Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition.
G H I J K M N P Q T U
102
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
18. RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the conditions recommended in the table below. For the details of recommended soldering conditions for the surface mounting type, refer to the information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact our salesman. Table 18-1. Soldering Conditions (1) PD70208HGF-x-3B9 : 80-pin plastic QFP (14 x 20 mm) PD70216HGF-x-3B9 : 80-pin plastic QFP (14 x 20 mm) (a) K, E, X masks
Recommended Conditions Symbol IR30-107-1
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature : 230 C, Time: 30 sec. max. (210 C min.), Number of times: 1, Number of daysNote : 7 days (after this, prebaking is necessary at 125 C for 10 hours) Package peak temperature: 215 C, Time: 40 sec. max. (200 C min.), Number of times: 1, Number of daysNote: 7 days (after this, prebaking is necessary at 125 C for 10 hours) Solder bath temperature: 260 C max. Time: 10 sec. max., Number of times: 1, Preheating temperature: 120 C max. (Package surface temperature), Number of days Note: 7 days (after this, prebaking is necessary at 125 C for 10 hours). Pin temperature: 300 C max., Time: 3 sec. max. (per device side)
VPS
VP15-107-1
Wave soldering
WS60-107-1
Partial pin heating
--
(b) P, M masks
Recommended Conditions Symbol IR35-207-2
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 235 C, Time: 30 sec. max. (210 C min.), Number of times: 2 max., Number of daysNote: 7 days (after this, prebaking is necessary at 125 C for 20 hours). Package peak temperature: 215 C, Time: 40 sec. (200 C min.) Number of times: 2 max., Number of daysNote: 7 days (after this prebaking is necessary at 125 C for 20 hours). Solder bath temperature: 260 C max., Time: 10 sec. max., Number of times: 1, Preheating temperature: 120 C max. (Package surface temperature). Number of daysNote: 7 days (after this, prebaking is necessary at 125 C for 20 hours). Pin temperature: 300 C max., Time: 3 sec. max. (per device side)
VPS
VP15-207-2
Wave soldering
WS60-207-1
Partial pin heating
--
Note
This means the number of days after unpacking the dry pack. Storage conditions are 25 C and 65% RH max.
Data Sheet U13225EJ4V0DS00
103
PD70208H, 70216H
(c) L, F masks
Recommended Conditions Symbol IR35-00-3
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 235 C, Time: 30 sec. max. (210 C min.), Number of times: 3 max. Package peak temperature: 215 C, Time: 40 sec. (200 C min.) Number of times: 3 max. Solder bath temperature: 260 C max., Time: 10 sec. max., Number of times: 1, Preheating temperature: 120 C max. (Package surface temperature) Pin temperature: 300 C max., Time: 3 sec. max. (per device side)
VPS
VP15-00-3
Wave soldering
WS60-00-1
Partial pin heating
--
Caution Do not use one soldering method in combination with another. (however, partial pin heating can be performed with other soldering methods).
104
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
(2) PD70208HGK-x-9EU : 80-pin plastic TQFP (fine pitch) (12 x 12 mm) PD70216HGK-x-9EU : 80-pin plastic TQFP (fine pitch) (12 x 12 mm) (a) K, E, X masks
Recommended Conditions Symbol IR30-101-1
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature : 230 C, Time: 30 sec. max. (210 C min.), Number of timers: 1, Number of daysNote: 1 day (after this, prebaking is necessary at 125 C for 10 hours) Package peak temperature: 215 C, Time: 40 sec. max. (200 C min.), Number of times: 1, Number of daysNote: 1 day (after this, prebaking is necessary at 125 C for 10 hours) Pin temperature: 300 C max., Time: 3 sec. max. (per device side)
VPS
VP15-101-1
Partial pin heating
--
(b) P, M, L, F masks
Recommended Conditions Symbol IR35-107-2
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 235 C, Time: 30 sec. max. (210 C min.), Number of times: 2 max., Number of daysNote: 7 days (after this, prebaking is necessary at 125 C for 10 hours). Package peak temperature: 215 C, Time: 40 sec. (200 C min.), Number of times: 2 max., Number of daysNote: 7 days (after this prebaking is necessary at 125 C for 10 hours). Pin temperature: 300 C max., Time: 3 sec. max. (per device side)
VPS
VP15-107-2
Partial heating
--
Note
This means the number of days after unpacking the dry pack. Storage conditions are 25 C and 65% RH max.
Caution Do not use one soldering method in combination with another. (however, partial pin heating can be performed with other soldering methods).
Data Sheet U13225EJ4V0DS00
105
PD70208H, 70216H
(3) PD70208HLP-x : 68-pin plastic QFJ (950 x 950 mil) PD70216HLP-x : 68-pin plastic QFJ (950 x 950 mil) (a) K, E, X masks
Recommended Conditions Symbol IR30-367-1
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature : 230 C, Time: 30 sec. max. (210 C min.), Number of timers: 1, Number of daysNote: 7 days (after this, prebaking is necessary at 125 C for 36 hours) Package peak temperature: 215 C, Time: 40 sec. max. (200 C min.), Number of times: 1, Number of daysNote: 7 days (after this, prebaking is necessary at 125 C for 36 hours) Pin temperature: 300 C max., Time: 3 sec. max. (per device side)
VPS
VP15-367-1
Partial pin heating
--
(b) P, M, L, F masks
Recommended Conditions Symbol IR35-367-3
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 235 C, Time: 30 sec. max. (210 C min.), Number of times: 3 max., Number of daysNote: 7 days (after this, prebaking is necessary at 125 C for 36 hours). Package peak temperature: 215 C, Time: 40 sec. (200 C min.), Number of times: 3 max., Number of daysNote: 7 days (after this prebaking is necessary at 125 C for 36 hours). Pin temperature: 300 C max., Time: 3 sec. max. (per device side)
VPS
VP15-367-3
Partial pin heating
--
Note
This means the number of days after unpacking the dry pack. Storage conditions are 25 C and 65% RH max.
Caution Do not use one soldering method in combination with another. (however, partial pin heating can be performed with other soldering methods).
106
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
[MEMO]
Data Sheet U13225EJ4V0DS00
107
PD70208H, 70216H
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
108
Data Sheet U13225EJ4V0DS00
PD70208H, 70216H
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
Data Sheet U13225EJ4V0DS00
109
PD70208H, 70216H
[MEMO]
V20, V20HL, V30, V30HL, V40, V40HL, V50, V50HL and V series are trademarks of NEC Corporation. * The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98.8

▲Up To Search▲

Price & Availability of UPD70208H

	To Download UPD70208H Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .