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DATA SHEET
MOS INTEGRATED CIRCUIT
PD16647
402/384-OUTPUT TFT-LCD SOURCE DRIVER (64 GRAY SCALE)
DESCRIPTION
The PD16647 is a source driver for TFT-LCD 64 gray scale displays. Its logic circuit operates at 3.3 V and the driver circuit operates at 5.0 V. The input data is digital data at 6 bits x 3 dots, and 260,000 colors can be displayed in 64-value outputs -corrected by the internal D/A converter and 10 external power supplies. The clock frequency is 50 MHz MIN. PD16647 can be used in TFT-LCD panels conforming to the SVGA standards.
FEATURES
* CMOS level input * 402/384 outputs * 6 bits (gray scale data) x 3 dots input * 64-value output by 10 external power supplies and internal D/A converter * Output dynamic range : VSS2 + 0.1 V to VDD2 - 0.1 V * High-speed data transfer: fMAX =50 MHz MIN.(internal data transfer rate at supply voltage VDD1 of logic circuit =3.0 V) * Level of -corrected power supply can be inverted * Input data inversion function (INV) * Precharge-less output buffer * Logic supply voltage (VDD1) : 3.3 V 0.3 V * Driver supply voltage (VDD2) : 5.0 V 0.5 V * Slim TCP
ORDERING INFORMATION
Part Number Package TCP (TAB package)
PD16647N-xxx
Remark
The TCP package is a custom-ordered item. Users are requested to consult with an NEC sales representative.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S13607EJ2V0DS00 (2nd edition) Date Published August 1999 NS CP (K) Printed in Japan
The mark * shows major revised points.
(c)
1998
PD16647
1. BLOCK DIAGRAM
STHL VDD1 (3.3 V) VSS1 C134
STHR R,/L CLK Osel
134-bit bidirectical shift register C1 C2 C133
D00 - D05 D10 - D15 D20 - D25 INV
Data register
STB
Latch
Bcont V0 - V9
D/A converter
VDD2 (5.0 V) VSS2
Output buffer
S1
S2
S3
S402/384
Remark /xxx indicates active low signal.
2
Data Sheet S13607EJ2V0DS00
PD16647
2. PIN CONFIGURATION ( PD16647N-xxx)
Bcont VSS2 VDD2 VDD1 R,/L INV STHL D20 D21 D22 D23 D24 D25 D10 D11 D12 D13 D14 D15 V9 V8 V7 V6 V5 V4 V3 V2 V1 V0 CLK STB D00 D01 D02 D03 D04 D05 STHR VSS1 VDD2 VSS2 Osel
S402/384 S401/383 S400/382 S399/381
Copper foil surface
S212/194 S211/193 S210 S209 S208 S207 S206 S205 S204 S203 S202 S201 S200 S199 S198 S197 S196 S195 S194 S193
S4 S3 S2 S1
Remark This figure does not specify the TCP package.
Data Sheet S13607EJ2V0DS00
3
PD16647
3. PIN DESCRIPTION
Pin Symbol S1 to S402/384 Pin Name Driver output Description Output 64 gray-scale analog voltages converted from digital signals. Osel = H or open: 402 outputs (S1 to S402/384) Osel = L : 384 outputs (S1 to S192, S211/193 to S402/384) S193 to S210 outputs are invalid in 384 outputs. Inputs 18-bit-wide display gray scale data (6 bits) x 3 dots (RGB). DX0 : LSB, DX5 : MSB
D00 to D05 D10 to D15 D20 to D25 R,/L
Display data input
Shift direction select input
This pin inputs/outputs start pulses in cascade mode. Shift direction of shift register is as follows: R,/L = H : STHR input, S1 S402, STHL output R,/L = L : STHL input, S402 S1, STHR output R,/L = H : Inputs start pulse R,/L = L : Outputs start pulse R/L = H : Outputs start pulse R/L = L : Inputs start pulse This pin can be used to finely control the bias current inside the output amplifier. In cases when fine-control is necessary, connect this pin to VDD2 using a resistor of 10 to 100k (per IC). When this fine-control function is not required, short-circuit this pin to VDD2. Refer to 7. Bias Current Control Function/Bcont. Inputs shift clock to shift register. Display data is loaded to data register at rising edge of this pin. Start pulse output goes high at rising edge of 134th clock after start pulse has been input, and serves as start pulse to driver in next stage. 134th clock of driver in first stage serves as start pulse of driver in next stage. Contents of data register are latched at rising edge, transferred to D/A converter, and output as analog voltage corresponding to display data. Contents of internal shift register are cleared after STB has been input. One pulse of this signal is input when PD16647 is started, and then device operates normally. For STB input timing, refer to 9. Switching Characteristics Waveform. Selects number of outputs. This pin is internally pulled up to VDD1. Osel = H or open : 402 outputs (S1 to S402/384) Osel = L : 384 outputs (S1 to S192, S211/193 to S402/384) Inputs -corrected power from external source. VSS2 V9 V8 V7 V6 V5 V4 V3 V2 V1 V0 VDD2 or VSS2 V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VDD2 Maintain gray scale power supply during gray scale voltage output. Input data can be inverted when display data is loaded. INV = H : Inverts and loads input data. INV = L : Does not invert input data. 3.3 V 0.3 V 5.0 V 0.5 V Ground Ground
STHR STHL Bcont
Right shift start pulse I/O Left shift start pulse I/O Bias control
CLK
Shift clock input
STB
Latch input
Osel
Selection of number of outputs
V0 to V9
-corrected power supply
INV
Data inversion input
VDD1 VDD2 VSS1 VSS2
Logic circuit power supply Driver circuit power supply Logic ground Driver ground
Caution
Be sure to turn on power in the order VDD1, logic input, VDD2, and gray scale power (V0 to V9), and turn off power in the reverse order, to prevent the PD16647 from being damaged by latchup. Be sure to observe this power sequence even during a transition period.
4
Data Sheet S13607EJ2V0DS00
PD16647
4. RELATION BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
The 10 major points on the -characteristic curve of the LCD panel are arbitrarily set by external power supplies V0 through V9. If the display data is 00H or 3FH, gray scale voltage V0 or V9 is output. If the display data is in the range 01H to 3EH, the high-order 3 bits select an external power pair Vn+1, Vn. The low-order 3 bits evenly divide the range of Vn+1 to Vn into eight segments by means of D/A conversion (however, the ranges from V8 to V7 and from V1 to V0 are divided into seven segments) to output a 64 gray scale voltage.
DX5(MSB) DX4 DX3 DX2 DX1 DX0 (LSB)
High-order 3 bits : -corrected power selected (Vn, Vn+1)
DX5 0 0 0 0 1 1 1 1 DX4 0 0 1 1 0 0 1 1 DX3 0 1 0 1 0 1 0 1 Vn+1-Vn V1-V2 V2-V3 V3-V4 V4-V5 V5-V6 V6-V7 V7-V8 V8-V9
Low-order 3 bits : 3-bit D/A (range Vn to Vn+1 is divided to 7 or 8 segments)
Vn
1 2 3 4 5 6 7 8 000 001 010 011 100 101 110 111 Vn+1
Figure4-1. Relationship between Input Data and -corrected Voltage
VDD2 V0 gray scale supply specified by 00H 7 segments V1 8 segments V2 8 segments V3 8 segments V4 8 segments V5 8 segments V6 8 segments V7 7 segments V8
VSS2 V9 0 7 F 17 1F Input data (HEX) 27 2F 37 3F
gray scale supply specified by 3FH
Data Sheet S13607EJ2V0DS00
5
PD16647
Table 4-1. Relationship between Input Data and Output Voltage
Input Data 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH DX5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DX4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DX3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DX2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DX1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DX0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output Voltage V0 V1 + (V0 - V1) x 6/7 V1 + (V0 - V1) x 5/7 V1 + (V0 - V1) x 4/7 V1 + (V0 - V1) x 3/7 V1 + (V0 - V1) x 2/7 V1 + (V0 - V1) x 1/7 V1 V2 + (V1 - V2) x 7/8 V2 + (V1 - V2) x 6/8 V2 + (V1 - V2) x 5/8 V2 + (V1 - V2) x 4/8 V2 + (V1 - V2) x 3/8 V2 + (V1 - V2) x 2/8 V2 + (V1 - V2) x 1/8 V2 V3 + (V2 - V3) x 7/8 V3 + (V2 - V3) x 6/8 V3 + (V2 - V3) x 5/8 V3 + (V2 - V3) x 4/8 V3 + (V2 - V3) x 3/8 V3 + (V2 - V3) x 2/8 V3 + (V2 - V3) x 1/8 V3 V4 + (V3 - V4) x 7/8 V4 + (V3 - V4) x 6/8 V4 + (V3 - V4) x 5/8 V4 + (V3 - V4) x 4/8 V4 + (V3 - V4) x 3/8 V4 + (V3 - V4) x 2/8 V4 + (V3 - V4) x 1/8 V4 V5 + (V4 - V5) x 7/8 V5 + (V4 - V5) x 6/8 V5 + (V4 - V5) x 5/8 V5 + (V4 - V5) x 4/8 V5 + (V4 - V5) x 3/8 V5 + (V4 - V5) x 2/8 V5 + (V4 - V5) x 1/8 V5 V6 + (V5 - V6) x 7/8 V6 + (V5 - V6) x 6/8 V6 + (V5 - V6) x 5/8 V6 + (V5 - V6) x 4/8 V6 + (V5 - V6) x 3/8 V6 + (V5 - V6) x 2/8 V6 + (V5 - V6) x 1/8 V6 V7 + (V6 - V7) x 7/8 V7 + (V6 - V7) x 6/8 V7 + (V6 - V7) x 5/8 V7 + (V6 - V7) x 4/8 V7 + (V6 - V7) x 3/8 V7 + (V6 - V7) x 2/8 V7 + (V6 - V7) x 1/8 V7 V8 + (V7 - V8) x 6/7 V8 + (V7 - V8) x 5/7 V8 + (V7 - V8) x 4/7 V8 + (V7 - V8) x 3/7 V8 + (V7 - V8) x 2/7 V8 + (V7 - V8) x 1/7 V8 V9
6
Data Sheet S13607EJ2V0DS00
PD16647
4.1 -Corrected Power Circuit The reference power supply of the D/A converter consists of a ladder circuit with a total of 64 resistors, and resistance ri between -corrected power pins differs depending on each pair of -corrected power pins. One pair of
-corrected power pins consists of seven or eight series resistors, and resistance ri in the figure below is indicated
as the sum of the seven or eight resistors. The resistance ratio between the -corrected power pins (ri ratio) is designed to be a value relatively close to the ratio of the -corrected voltages V1 through V8 (gray scale voltages in 7 steps) used in an actual LCD panel. Under ideal conditions where there is no difference between the two, therefore, there is no voltage difference between the voltage of the -corrected power supplies and the gray scale voltages in 7 steps of the resistor ladder circuits of the PD16647, and no current flows into the -corrected power pins V1 through V8. As a result, a voltage follower circuit is not necessary. Figure4-2. -Corrected Power Circuit
-corrected power pin -corrected resister
PD16647
V0
i0 7 R0 : 1.98 k = ri i=1 8 R1 : 1.72 k = ri i=1 8 R2 :0.86 k = ri i=1 8 R3 : 0.99 k = ri i=1 8 R4 : 0.73 k = ri i=1 8 R5 : 0.79 k = ri i=1 8 R6 :1.06 k = ri i=1 7 R7 : 1.58 k = ri i=1 R8 : 6.28 k
V1
i1
V2
i2
V3
i3
Sum of eight -corrected resistors
V4
i4
V5
i5
V6
i6
V7
i7
V8
i8
V9
i9
Data Sheet S13607EJ2V0DS00
7
PD16647
5. RELATION BETWEEN INPUT DATA AND OUTPUT VOLTAGE
Data format : 6 bits x RGB (3 dots) Input width : 18 bits (1 pixel data) (1) R,/L = H (right shift)
Output Data S1 D00 to D05 S2 D10 to D15 S3 D20 to D25 S4 D00 to D05 ... ... S401/383 D10 to D15 S402/384 D20 to D25
(2) R,/L = L (left shift)
Output Data S1 D00 to D05 S2 D10 to D15 S3 D20 to D25 S4 D00 to D05 ... ... S401/383 D10 to D15 S402/384 D20 to D25
6. OPERATION OF OUTPUT BUFFER
The output buffer consists of an operational amplifier circuit that does not perform precharge operation. Therefore, driver output current IVOH1/2 is the charging current to the LCD, and IVOL1/2 is the discharging current. Figure6-1. LCD panel driving waveform of PD16647
VDD2
Sn
VSS2
Write (IVOL1/2/IVOH1/2)
Write (IVOL1/2/IVOH1/2)
1 horizontal period
8
Data Sheet S13607EJ2V0DS00
PD16647
7. BIAS CURRENT CONTROL FUNCTION/Bcont
It is possible to fine-control the current consumption by using the bias current control function (Bcont pin). When using this function, connect this pin to the stabilized VDD2 potential using an external resistor (REXT). When not using this function, however, short-circuit this pin to VDD2.
Figure7-1. Bias Current Control Function/Bcont
PD16647
Bcont
REXT
VDD2
Refer to the table below for the percentage of current regulation when using the bias current control function.
Table7-1. Current Consumption Regulation Percentage Compared to Normal Mode
REXT SHORT 10 k 20 k 40 k 80 k Current Consumption Regulation Percentage 100 % 95 % 91 % 85 % 79 %
Remark Be aware that the above current consumption regulation percentages are not productcharacteristic guaranteed as they are based on the results of simulation. Caution Because the low-power and bias-current control functions control the bias current in the output amplifier and regulate the over-all current consumption of the driver IC, when this occurs, the characteristics of the output amplifier will simultaneously change. Therefore, when using these functions, be sure to sufficiently evaluate the picture quality.
Data Sheet S13607EJ2V0DS00
9
PD16647
8. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (VSS1 = VSS2 = 0 V)
Parameter Logic Supply Voltage Driver Supply Voltage Input Voltage Output Voltage Operating Ambient Temperature Storage Temperature VDD1 VDD2 VI VO TA Tstg
Symbol
Ratings -0.3 to +4.5 -0.3 to +6.0 -0.3 to VDD1,2 + 0.3 -0.3 to VDD1,2 + 0.3 -10 to +75 -55 to +125
Unit V V V V C C
Caution
If the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the range of the absolute maximum ratings.
Recommended Operating Range (TA = -10 to +75 C, VSS1 = VSS2 = 0 V)
Parameter Logic Supply Voltage Driver Supply Voltage High-level Input Voltage Low-level Input Voltage -corrected Supply Voltage Maximum Clock Frequency
Symbol VDD1 VDD2 VIH VIL V0 to V9 fMAX.
MIN. 3.0 4.5 0.7 VDD1 0 VSS2 + 0.1 50
TYP. 3.3 5.0
MAX. 3.6 5.5 VDD1 0.3 VDD1 VDD2 - 0.1
Unit V V V V V MHz
10
Data Sheet S13607EJ2V0DS00
PD16647
Electrical Characteristics (TA = -10 to +75 C, VDD1 = 3.3 V 0.3 V, VDD2 = 5.0 V 0.5 V, VSS1 = VSS2 = 0 V)
Parameter Input Leakage Current
Symbol IIL
Condition D00-D05,D10-D15,D20-D25 R,/L,STB
MIN.
TYP.
MAX. 1.0
Unit
A
Pull-up Resistor High-level Output Voltage Low-level Output Voltage Static Current Consumption of
RPU VOH VOL Ivn1
VDD1 = 3.3 V STHR(STHL),IO = -1.0 mA STHR(STHL),IO = +1.0 mA VDD1 = 3.3 V, Vn -Vn+1 = 0.5 V, VDD2 = 5.0 V V0-V1 V1-V2 V2-V3 V3-V4 V4-V5 V5-V6 V6-V7 V7-V8 V8-V9
40 VDD1 - 0.5
100
250
k V
0.5 126 145 289 252 343 315 237 158 40 253 291 579 504 686 631 474 316 80 506 582 1158 1008 1372 1262 948 632 160 -0.03
V
A A A A A A A A A
mA
-corrected Power
Driver Output Current
IVOH2
VOUT = 4.4 V, VX = 4.9 V
Note1
(-0.12)
VDD1 = 3.3 V, VDD2 = 5.0 V IVOL2 VOUT = 0.6 V, VX = 0.1 V
Note1
0.04
(0.16)
mA
VDD1 = 3.3 V, VDD2 = 5.0 V Output Voltage Deviation VO VP-P VO IDD1 IDD2 VDD1 = 3.3 V, VDD2=5.0 V, VOUT=2.5 V Output Swing Difference Deviation Output Voltage Range Dynamic Logic Current Consumption Dynamic Driver Current Consumption Input data Input data : 00H to 3FH No load, VDD2 = 3.3 V No load, VDD2 = 5.0 V
Note2 Note2 Note1
10
20
mV
(5) VSS2 + 0.1 0.5 5.0 VDD2 - 0.1 2.5 10.0
mV V mA mA
Notes 1. VX refers to the output voltage of analog output pins S1 to S402/384. VOUT refers to the voltage applied to analog output pins S1 to S402/384. 2. The STB cycle is specified at 31 s and fCLK= 16 MHz.
Data Sheet S13607EJ2V0DS00
11
PD16647
Switching Characteristics (TA = -10 to +75 C, VDD1 = 3.3 V 0.3 V, VDD2 = 5.0 V 0.5 V, VSS1 = VSS2 = 0 V)
Parameter Start Pulse Delay Time
Symbol tPLH1 tPHL1 CL = 15 pF
Condition
MIN.
TYP. 7 7
MAX. 12 12 10 12 10 12 20 150 15
Unit ns ns
Driver Output Delay Time tPLH2 tPLH3 tPHL2 tPHL3 Input Capacitance CI1 CI2 CI3
VDD2 = 5.0 V 5 k +36 pF
VO: 0.1 V 4.9 V
2.2 2.9
s s s s
pF pF pF
VO: 4.9 V 0.1 V
2.6 3.6
STHR (STHL), TA = 25 C V0 to V9, TA = 25 C STHR (STHL), other than V0 to V9 , TA = 25 C
10 100 10

2.5 k Output 9 pF 18 pF 9 pF 2.5 k
Timing Requirements (TA = -10 to +75 C, VDD1 = 3.3 V 0.3 V, VDD2 = 5.0 V 0.5 V, VSS1 = VSS2 = 0 V)
Parameter Clock Pulse Width Clock Low Period Clock High Period Data Setup Time Data Hold Time Start Pulse Setup Time Start Pulse Hold Time INV Setup Time INV Hold Time Start Pulse Low Period Start Pulse Rise Time
Symbol PWCLK PWCLK (L) PWCLK (H) tSETUP1 tHOLD1 tSETUP2 tHOLD2 tSETUP4 tHOLD4 tSPL tSPR 384 outputs 402 outputs
Condition
MIN. 20 4 4 4 0 4 0 4 0 2
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns ns CLK
128 134 1 2 1 1
CLK CLK CLK CLK CLK CLK ns ns
STB Setup Time
tSETUP3 PWSTB tINV tLDT tCLK-STB tSTB-CLK CLK STB STB CLK
5
STB Pulse Width Data Invalid Period Last Data Timing CLK-STB Time STB-CLK Time
7 7
12
Data Sheet S13607EJ2V0DS00
5
9. SWITCHING CHARACTERISTIC WAVEFORM(R,/L= H)
Unless otherwise specified, the input level is VIH = 0.7 VDD1, VIL = 0.3 VDD1.
PWCLK(L)
PWCLK 2
PWCLK(H) 1 2 90% 3 136
tr
tf VDD1
CLK tSETUP2 STHR (1st Dr.)
1 tHOLD2
134
135
799
800
801 tSPL
10%
VSS1
VDD1 VSS1 tINV tSETUP1 tHOLD1 D397 to D399 D400 to D402 D403 to D405 D2392 to D2394 D2395 to D2397 D2398 to D2400 tSETUP3 VDD1 D1 to D3 D4 to D6 VSS1 tSETUP4 tHOLD4 VDD1
Dn0 to Dn5
INVALID
D1 to D3
D4 to D6
INVALID
INV
INVALID
INVALID VSS1 tPLH1 tSPR tPHL1 VDD1 VSS1 tCLK-STB tSTB-CLK tLDT VDD1
Data Sheet S13607EJ2V0DS00
STHL (1st Dr.)
STB
PWSTB
VSS1 tPLH31/32 tPLH21/22
Hi-Z
Target Voltage 0.1 VDD2 VOUT 6-bit accuracy
tPHL21/22
PD16647
tPHL31/32
13
PD16647
10. RECOMMENDED MOUNTING CONDITIONS
The following conditions must be met for mounting conditions of the PD16647. For more details, refer to the Semiconductor Device Mounting Technology Manual(C10535E). Please consult with our sales offices in case other mounting process is used, or in case the mounting is done under different conditions.
PD16647N-xxx : TCP(TAB Package)
Mounting Condition Thermocompression Mounting Method Soldering Condition Heating tool 300 to 350 C, heating for 2 to 3 sec ; pressure 100g(per solder) ACF (Adhesive Conductive Film) Temporary bonding 70 to 100 C ; pressure 3 to 8 kg/cm ; time 3 to 5
2
sec. Real bonding 165 to 180 C pressure 25 to 45 kg/cm time 30 to
2
40secs(When using the anisotropy conductive film SUMIZAC1003 of Sumitomo Bakelite,Ltd).
Caution
To find out the detailed conditions for mounting the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more mounting methods at a time.
14
Data Sheet S13607EJ2V0DS00
PD16647
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S13607EJ2V0DS00
15
PD16647
Reference Documents NEC Semiconductor Device Reliability/Quality Control System(C10983E) Quality Grades to NEC's Semiconductor Devices(C11531E)
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98. 8

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