| PART |
Description |
Maker |
| 5962-8978501YA 5962-8978501PC 5962-8978501YC 5962- |
5962-8978501YA · Hermetically Sealed Low IF Wide Vcc High Gain Optocouplers
5962-8978501PC · Hermetically Sealed Low IF Wide Vcc High Gain Optocouplers
5962-8978501YC · Hermetically Sealed Low IF Wide Vcc High Gain Optocouplers
5962-89785022A · Hermetically Sealed Low IF Wide Vcc High Gain Optocouplers
5962-8978501ZA · Hermetically Sealed Low IF Wide Vcc High Gain Optocouplers
5962-8978503KPC · Hermetically Sealed Low IF Wide Vcc High Gain Optocouplers
5962-8978503KYA · Hermetically Sealed Low IF Wide Vcc High Gain Optocouplers
5962-8978503KPA · Hermetically Sealed Low IF Wide Vcc High Gain Optocouplers
5962-8978503KZA · Hermetically Sealed Low IF Wide Vcc High Gain Optocouplers
5962-8978501PA · Hermetically Sealed Low IF Wide Vcc High Gain Optocouplers
5962-9800201KFC · Hermetically Sealed Low IF Wide Vcc High Gain Optocouplers
5962-8981001PA · Hermetically Sealed Low IF Wide Vcc High Gain Optocouplers
6N140A/883B · Hermetically Sealed Low IF Wide Vcc High Gain Optocouplers
8302401FC · Hermetically Sealed Low IF Wide Vcc High Gain Optocouplers
|
Agilent (Hewlett-Packard)
|
| APL5551 |
Dual Channel 500mA/500mA Regulator Reset IC
|
Anpec Electronics
|
| MAX1857 MAX1857EUA47 |
Replaced by TMS320C6202B : Fixed-Point Digital Signal Processor 352-FCBGA 500mA、具有纹波抑制的LDOamp;micro;MAX封装
500mA, Low-Dropout, Ripple-Rejecting LDO in MAX
From old datasheet system
500mA / Low-Dropout / Ripple-Rejecting LDO in MAX
500mA, Low-Dropout, Ripple-Rejecting LDO in µMAX
|
Maxim Integrated Products, Inc.
MAXIM[Maxim Integrated Products]
MAXIM - Dallas Semiconductor
|
| MAX1792 MAX1792EUA MAX1792EUA15 MAX1792EUA18 MAX17 |
500mA, Low-Dropout Linear Regulator in µMAX FIXED/ADJUSTABLE POSITIVE LDO REGULATOR, 0.225 V DROPOUT, PDSO8
500mA Low-Dropout Linear Regulator in uMAX
500mA Low-Dropout Linear Regulator in MAX
500mA Low-Dropout Linear Regulator in レMAX
|
Maxim Integrated Products, Inc.
MAXIM[Maxim Integrated Products]
MAXIM - Dallas Semiconductor
|
| IC62LV1024AL IC62LV1024ALL-45B IC62LV1024ALL-45BI |
70ns; 2.7-3.3V; 128K x 8 low-power and low Vcc CMOS static RAM
ASYNCHRONOUS STATIC RAM, Low Power A.SRAM
128K x 8 Ultra Low Power and Low VCC SRAM
From old datasheet system
55ns; 2.7-3.3V; 128K x 8 low-power and low Vcc CMOS static RAM
|
ICSI[Integrated Circuit Solution Inc]
|
| XVB-C5B4 XVB-C4B4 XVB-L4B4 XVB-C38 XVB-L4B5 XVB-C2 |
72-Mbit QDR-II™ SRAM 2-Word Burst Architecture
4-Mbit (512K x 8) MoBL® Static RAM
MoBL® 2-Mbit (128K x 16) Static RAM
TetraHub™ High-Speed USB Hub Controller
CY7C602xx Wireless; Memory Size: 8K; RAM: 256B; Vcc (V): 2.7-3.6V; Core: M8C; Code Memory Architecture: Flash; Development Kit: CY3655
镜头单元LED绿色24V
镜头单元闪烁的红
LENS UNIT LED ORANGE 24V 镜头组带领橙24V
SMD IC USB DRIVER
|
STMicroelectronics N.V.
|
| MAX6754UKLD0-T MAX6755UKLD0-T MAX6756UKLD0-T MAX67 |
Vcc: 5.0 V, active timeout period: 0.02 ms, low-power single/dual-voltage window detector
Vcc: 3.0 V, active timeout period:0.02 ms, low-power single/dual-voltage window detector
Vcc: 5.0 V, active timeout period: 100 ms-320 ms, low-power, single/dual-voltage window detector
Vcc: 5.0 V, active timeout period:185 ms, low-power single/dual-voltage window detector
Vcc: 2.5 V, Vcc:1.8 V, active timeout period:185 ms, low-power single/dual-voltage window detector
Vcc: 3.3 V, Vcc: 1.8 V, active timeout period:185 ms, low-power single/dual-voltage window detector
Vcc: 3.3 V, active timeout period:0.02 ms, low-power single/dual-voltage window detector
Vcc: 3.3 V, active timeout period:185 ms, low-power single/dual-voltage window detector
Vcc: 1.8 V, active timeout period:0.02 ms, low-power single/dual-voltage window detector
Vcc: 3.0 V, active timeout period:185 ms, low-power single/dual-voltage window detector
Vcc: 1.8 V, Vcc:adj, active timeout period:185 ms, low-power single/dual-voltage window detector
|
MAXIM - Dallas Semiconductor
|
| BD15KA5FP-E2 BD15KA5WF-E2 BD15KA5WFP-E2 BDXXKA5W B |
500mA Variable/Fixed Output LDO Regulators Built-in thermal shutdown circuit
low-saturation regulators that are available for output currents up to 500mA.
|
Rohm
|
| M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M3823 |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V
18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
|
Renesas Electronics Corporation.
Renesas Electronics, Corp.
|
| KM416C1004CJ-5 KM416C1004CJ-6 KM416C1004CJL-6 KM41 |
1M x 16Bit CMOS dynamic RAM with extended data out, 50ns, VCC=5.0V, refresh period=64ms
1M x 16Bit CMOS dynamic RAM with extended data out, 60ns, VCC=5.0V, refresh period=64ms
1M x 16Bit CMOS dynamic RAM with extended data out, 60ns, VCC=5.0V, self-refresh
1M x 16Bit CMOS dynamic RAM with extended data out, 50ns, VCC=5.0V, refresh period=16ms
1M x 16Bit CMOS dynamic RAM with extended data out, 60ns, VCC=5.0V, refresh period=16ms
1M x 16Bit CMOS dynamic RAM with extended data out, 45ns, VCC=5.0V, self-refresh
|
Samsung Electronic
|
| 403CNQ080 |
400 Amp Schottky Rectifier(400 A 肖特基整流器) 400安培肖特基整流器00甲肖特基整流器）
|
International Rectifier, Corp.
|
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