| PART |
Description |
Maker |
| 74F109 I74F109D I74F109N N74F109D N74F109N 74F109_ |
Positive J-K positive edge-triggered flip-flops F/FAST SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16
From old datasheet system
Positive J-Knot positive edge-triggered flip-flops
|
NXP Semiconductors N.V.
PHILIPS[Philips Semiconductors]
|
| 74LVX112M 74LVX112MTC 74LVX112 74LVX112SJX |
J-K-Type Flip-Flop
Low Voltage Dual J-K Flip-Flops with Preset and Clear
From old datasheet system
|
FAIRCHILD[Fairchild Semiconductor]
|
| AAT3562IGY-320-T1 AAT3562IGY-420-T1 AAT3564IGY-420 |
Triple 3-input positive-AND gates 14-PDIP 0 to 70
CONNECTOR ACCESSORY
Triple 3-input positive-AND gates 14-SOIC 0 to 70
Triple 3-input positive-NAND gates 14-SOIC 0 to 70
Triple 3-input positive-NAND gates 14-PDIP 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset 16-SOIC 0 to 70
Triple 3-input positive-NAND gates 14-SO 0 to 70
Triple 3-input positive-AND gates 14-SO 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset 16-PDIP 0 to 70
Dual J-K Flip-Flops With Clear 14-SO 0 to 70
NanoPower Voltage Detector NanoPower电压检测器
Dual J-K Flip-Flops With Clear 14-SOIC 0 to 70 NanoPower电压检测器
Dual J-K Flip-Flops With Clear 14-PDIP 0 to 70 NanoPower电压检测器
|
Advanced Analogic Technologies, Inc.
|
| HD74HC107 |
Dual J-K Flip-Flops (with Clear)
|
Hitachi Semiconductor
|
| 74VHC112MTC |
Dual J-K Flip-Flops with Preset and Clear
|
ON Semiconductor
|
| MM74C73 MM74C73N MM74C76M MM74C76N |
Dual J-K Flip-Flops with Clear and Preset
|
FAIRCHILD[Fairchild Semiconductor]
|
| HD74HC112 HD74HC112FPEL HD74HC112P |
Dual J-K Flip-Flops (with Preset and Clear)
|
Renesas Electronics Corporation
|
| HD74HC74-15 |
Dual D-type Flip-Flops (with Preset and Clear)
|
Renesas Electronics Corporation
|
| U74LVC74AG-S14-R |
DUAL POSITIVE-EDGETRIGGERED D-TYPE FLIP-FLOPS
|
Unisonic Technologies
|
| M27W201-80K6TR M27W201-200NZ6TR M27W201-80NZ6TR M2 |
2 MBIT (256KB X8) LOW VOLTAGE OTP EPROM
Test Spring Probe; Current Rating:3A; Leaded Process Compatible:Yes; Length:0.060"; Peak Reflow Compatible (260 C):No; Tip/Nozzle Style:90 Concave RoHS Compliant: Yes 2兆位56Kb × 8低压紫外线可擦写可编程只读存储器和OTP存储
Triple 3-Input Positive-AND Gates 14-SO 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-SO 0 to 70
Triple 3-Input Positive-AND Gates 14-PDIP 0 to 70
Triple 3-Input Positive-AND Gates 14-SOIC 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-PDIP 0 to 70
2 Mbit 256Kb x 8 Low Voltage UV EPROM and OTP EPROM
2 MBIT (256KB X8) LOW VOLTAGE OTP EPROM
|
STMicroelectronics N.V.
意法半导
STMICROELECTRONICS[STMicroelectronics]
ST Microelectronics
|
| DM7474 |
Dual Positive-Edge-Triggered D-Type Flip-Flops
|
Fairchild
|
