| PART |
Description |
Maker |
| PDU1032H-0.5C4 |
Delay 0.5 /-0.3 ns, 5-BIT, ECL-interfaced programmable delay line
|
Data Delay Devices Inc
|
| PDU1032H-8MC5 PDU1032H PDU1032H-.5 PDU1032H-.5C5 P |
ACTIVE DELAY LINE, TRUE OUTPUT, CDSO40
ACTIVE DELAY LINE, TRUE OUTPUT, PDSO40
Programmable 5-bit 10K ECL delay line
5-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU1032H)
|
DATA DELAY DEVICES INC
DATADELAY[Data Delay Devices, Inc.]
|
| DDU12H-75MC4 |
5-TAP, ECL-INTERFACED FIXED DELAY LINE
|
Data Delay Devices, Inc...
|
| MDU14-5C4 MDU14-7C4 |
QUAD, ECL-INTERFACED FIXED DELAY LINE (SERIES MDU14) 四，经过ECL接口固定延迟线（系列MDU14
|
Data Delay Devices, Inc.
|
| MDU13H-25C3 MDU13H-4MC3 MDU13H-15M MDU13H-45M |
TRIPLE, ECL-INTERFACED FIXED DELAY LINE (SERIES MDU13H) ACTIVE DELAY LINE, TRUE OUTPUT, DSO16
TRIPLE, ECL-INTERFACED FIXED DELAY LINE (SERIES MDU13H) ACTIVE DELAY LINE, TRUE OUTPUT, DIP9
|
Data Delay Devices, Inc.
DATA DELAY DEVICES INC
|
| MC100EP445 MC10H100MEL MC10E1651FNR2 NUP4201MR6T1 |
3.3V / 5VECL 8-Bit Serial/Parallel Converter
Quad 2-Input NOR Gate With Strobe
5V, -5V ECL Dual ECL Output Comparator With Latch
Low Capacitance Surface Mount TVS for High-Speed Data Interfaces
-3.3V / -5V Triple ECL Input to PECL Output Translator
3.3V 10-bit LVTTL/LVCMOS to LVPECL Translator
|
ON Semiconductor
|
| SPT9712 SPT9712AIP SPT9712BIP |
12-BIT, 100 MWPS ECL D/A CONVERTER PARALLEL, WORD INPUT LOADING, 0.013 us SETTLING TIME, 12-BIT DAC, PQCC28
12-BIT 100 MWPS ECL D/A CONVERTER
From old datasheet system
SPT9712
|
Fairchild Semiconductor, Corp.
Fairchild Semiconductor Corporation
FAIRCHILD[Fairchild Semiconductor]
|
| AND8090 AND8090D MC100H601 MC100H601FN MC10H106FN |
3.3V / 5V ECL Quad 2-Input Differential AND/NAND
5V ECL Low Impedance Driver
LOW VOLTAGE DUAL 1:4, 1:5 DIFFERENTIAL FANOUT BUFFER
8 Input Priority Encoder
3.3V ECL Triple D-Type Flip-Flop with Set and Reset
3.3V / 5V ECL Quad D Flip Flop with Set, Reset, and Differential Clock
3.3V Dual Differential LVPECL to LVTTL Translator
3.3V / 5V ECL 6-Bit Differential Register with Master Reset
3.3V ECL 1:15 Differential ÷1/÷2 Clock Driver
Fibre Channel Coaxial Cable Driver and Loop Resillency Circuit
3.3 V 1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable
3.3V / 5V ECL 8-Bit Synchronous Binary Up Counter
2.5 V/3.3 V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset and OLS
3.3V / 5V Programmable PLL Synthesized Clock Generator (25 to 400 MHz)
2.5 V/3.3 V SiGe 1:2 Differential Clock Driver with RSECL Outputs
2.5 V/3.3 V SiGe 1:10 Differential Clock Driver with RSECL Outputs
Triple 4-3-3-Input NOR Gate
9-Bit ECL-TTL Translator
AC Characteristics of ECL Devices
|
Motorola
ONSEMI[ON Semiconductor]
|
| DDU12H-75 DDU12H-400M DDU12H-400 |
5-TAP, ECL-interfaced fixed delay line
Delay Line 延迟
|
Data Delay Devices Inc
Data Delay Devices, Inc.
|
| MC100LVE310FN MC100LVE31006 MC100LVE310FNG MC100LV |
3.3V ECL 2:8 Differential Fanout Buffer(3.3V ECL 2 差分输出缓冲 3.3V的差分ECL 2:8扇出缓冲器（3.3 ECL 2:8差分输出缓冲器）
|
ONSEMI[ON Semiconductor]
|
