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KI1555DL - PIN Configuration Drain-Source Voltage Vds 20V

KI1555DL_8243423.PDF Datasheet


 Full text search : PIN Configuration Drain-Source Voltage Vds 20V


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Advance Product Specification
From old datasheet system
Xilinx, Inc.
XILINX[Xilinx, Inc]
PQ60150HZW40XYZ-G Industry standard half-brick pin-out configuration
SynQor Worldwide Headqu...
AT17C128 AT17C128-10JC AT17C128-10JI AT17C128-10PC FPGA Configuration E2PROM 64K X 1 CONFIGURATION MEMORY, PDSO20
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High Speed CMOS Logic Dual Monostable Multivibrators with Reset 16-TSSOP -55 to 125 FPGA配置EEPROM存储
High Speed CMOS Logic Dual Monostable Multivibrators with Reset 16-SOIC -55 to 125 高速CMOS逻辑可复位双重单稳态多谐振荡器 SOIC-16封装 工作温度55℃_125
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PhotoMOS Relay; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Voltage:5V RoHS Compliant: No
Connector assemblies, Ribbon (Flat); Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No RoHS Compliant: No
High Speed CMOS Logic 3-to-8 Line Decoder Demutiplexer with Address Latches 16-SOIC -55 to 125
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MOSFET; Transistor Polarity:N Channel; Drain Source Voltage, Vds:40V; Continuous Drain Current, Id:60A; On-Resistance, Rds(on):0.0065ohm; Rds(on) Test Voltage, Vgs:10V; Package/Case:5-D2-PAK; Leaded Process Compatible:No
MOSFET; Transistor Polarity:N Channel; Drain Source Voltage, Vds:40V; Continuous Drain Current, Id:60A; On-Resistance, Rds(on):5.5mohm; Rds(on) Test Voltage, Vgs:10V; Package/Case:5-D2-PAK; Leaded Process Compatible:No
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Panasonic, Corp.
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