| PART |
Description |
Maker |
| PEX8603 |
Low Packet Latency & High Performance
PCI Express Gen 2 Switch
|
Shenzhen Luguang Electronic Technology Co., Ltd
AVAGO TECHNOLOGIES LIMI...
|
| EP731105 EP7311-CB-90 EP7311-CR-90 EP7311-IB-90 EP |
High-performance, Low-power, System-on-chip with SDRAM & Enhanced Digital Audio Interface
Embedded Processors IC Ultra Low PWR Hi Perf SOC w/LCD 32-BIT, 90 MHz, RISC MICROCONTROLLER, PBGA256
32-Bit Microcontroller IC; Controller Family/Series:(ARM7); Memory Size, SRAM:48KB; Number of I/O Pins:27; Number of Timers 8/12/16/32 Bits:0 / 0 / 2 / 0; Number of PWM Channels:2; Clock Speed:74MHz; Interfaces:SSI, UART
|
Cirrus Logic, Inc.
CIRRUS LOGIC INC
|
| LTC2421 LTC2422 LTC2421CMS LTC2422CMS LTC2422IMS L |
1-/2-Channel 20-Bit UPower No Latency ADCs in MSOP-10
2-Ch 8ppm INL, 1.2ppm Noise, No Latency Delta Sigma, MS10
8ppm INL, 1.2ppm Noise, 20-Bit No Latency Delta Sigma, MS10
1-/2-Channel 20-Bit Power No Latency DeltaSigmaADCs in MSOP-10
1-/2-Channel 20-Bit µPower No Latency DeltaSigma™ ADCs in MSOP-10
|
LINER[Linear Technology]
|
| 89HPES32T8G2 |
Low latency cut-through architecture
|
Integrated Device Techn...
|
| 89HPES32H8G2 |
Low latency cut-through architecture
|
Integrated Device Techn...
|
| VDS-0202 |
Low-Latency for Video/Voice/Data applications
|
Level One
|
| CXG1125ER |
High Power 6 × 4 Antenna Switch MMIC with Integrated Control Logic for PDC Full Packet
High Power 6 4 Antenna Switch MMIC with Integrated Control Logic for PDC Full Packet
High Power 6 】 4 Antenna Switch MMIC with Integrated Control Logic for PDC Full Packet
High Power 6x4 Antenna Switch MMIC with
|
Sony Corporation
|
| LTC2436-1CGN LTC2436-1IGN LTC2436-1 LTC2436-1-15 |
2-Channel Differential Input 16-Bit No Latency ADC
2-Channel Differential Input 16-Bit No Latency DS ADC 2-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16
2-Channel Differential Input 16-Bit No Latency DS ADC
|
Linear Technology Corporation
Linear Technology, Corp.
|
| CY7C1165V18 CY7C1163V18 CY7C1161V18 CY7C1176V18 CY |
18-Mbit QDRII SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) 2M X 9 QDR SRAM, 0.45 ns, PBGA165
18-Mbit QDRII SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) 18兆位的国防评估报告⑩- II SRAM字突发架构（2.5周期读写延迟
18-Mbit QDR??II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
|
Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
|
| RPC-UHF |
Radio Packet Controller
|
http://
|
| AC48304 |
Voice Over Packet Processor
|
Audio Codes
|
