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CY7C1146KV18 - 18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)

CY7C1146KV18_4665358.PDF Datasheet


 Full text search : 18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)


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