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CAT64LC20J - 18-Mbit (512K x 36/1Mbit x 18) Pipelined Register-Register Late Write 36-Mbit DDR-II SRAM 2-Word Burst Architecture 9-Mbit QDR- II™ SRAM 2-Word Burst Architecture 36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL™ Architecture 36 Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL™ Architecture SPI Serial EEPROM 4-Mbit (128K x 36) Pipelined Sync SRAM 9-Mbit (256K x 36/512K x 18) Pipelined SRAM

CAT64LC20J_1120941.PDF Datasheet

Part No.

CAT64LC20J CAT64LC40J CAT64LC10PI CAT64LC40SA CAT64LC40SI CAT64LC20SI CAT64LC20JI CAT64LC20PI

Description

18-Mbit (512K x 36/1Mbit x 18) Pipelined Register-Register Late Write
36-Mbit DDR-II SRAM 2-Word Burst Architecture
9-Mbit QDR- II™ SRAM 2-Word Burst Architecture
36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL™ Architecture
36 Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL™ Architecture
SPI Serial EEPROM
4-Mbit (128K x 36) Pipelined Sync SRAM
9-Mbit (256K x 36/512K x 18) Pipelined SRAM

File Size

87.91K / 9 Page

Maker

N/A

JITONG TECHNOLOGY
(CHINA HK & SZ)
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Part: CAT64LC20JI-TE13

Maker: CSI

Pack: SOP-8

Stock: 1076

Unit price for :

50: $0.90

100: $0.86

1000: $0.81

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Full text search : 18-Mbit (512K x 36/1Mbit x 18) Pipelined Register-Register Late Write 36-Mbit DDR-II SRAM 2-Word Burst Architecture 9-Mbit QDR- II™ SRAM 2-Word Burst Architecture 36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL™ Architecture 36 Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL™ Architecture SPI Serial EEPROM 4-Mbit (128K x 36) Pipelined Sync SRAM 9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Product Description search : 18-Mbit (512K x 36/1Mbit x 18) Pipelined Register-Register Late Write 36-Mbit DDR-II SRAM 2-Word Burst Architecture 9-Mbit QDR- II™ SRAM 2-Word Burst Architecture 36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL™ Architecture 36 Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL™ Architecture SPI Serial EEPROM 4-Mbit (128K x 36) Pipelined Sync SRAM 9-Mbit (256K x 36/512K x 18) Pipelined SRAM

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