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Part No. HYMD1166458
OCR Text ...nced to both rising and falling edges of differential clock inputs. while all addresses and control inputs are latched on the rising edges of the clock, data, data strobes and write data masks inputs are sampled on both rising and falling e...
Description 16Mx64|2.5V|H/L|x8|DDR SDRAM - Unbuffered DIMM 128MB

File Size 150.62K  /  16 Page

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    NANOAMP[NanoAmp Solutions, Inc.]
Part No. NT5DS4M32EG-6 NT5DS4M32EG NT5DS4M32EG-5 NT5DS4M32EG-5G
OCR Text ...ansactions are possible on both edges of the clock. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications. Features...
Description 1M 】 32 Bits 】 4 Banks Double Data Rate Synchronous RAM With Bi-Directional Data Strobe and DLL

File Size 781.03K  /  46 Page

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    Pericom Technology
PERICOM[Pericom Semiconductor Corporation]
Part No. PI6C2410QE PI6C2410 PI6C2410L PI6C2410LE PI6C2410Q
OCR Text ...2.0V 35 50 CLKIN to FBIN rising edges @VDD/2 @1.4V, rising edges @VDD/2, rising edges, same CLKIN -150 40 66 80 160 150 200 400 200 65 1. 5 % ns ps MHz Te s t Conditions Low Freq., HF# = "1" M in. 10 Typ. 33 M ax. 40 Units Note: Tjc = Tp...
Description PCI-X Clock Buffers

File Size 82.89K  /  6 Page

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    ALSC[Alliance Semiconductor Corporation]
Part No. AS80M2516A AS80M2516A_V1.0
OCR Text ...) to one clock period On rising edges 500 s apart at 2.5V relative to an ideal clock, CL = 15pF, fXIN=14.318MHz, FOUT = CLOCK (MHz) MIN TYP MAX UNIT fo tr Tf 4 2.1 1.9 140 MHz ns ns Clock Outputs (PLL A clock v...
Description 3.3 V, generater an EMI optimizer clocking signal at output
dual phase lock loop clock chip
From old datasheet system

File Size 437.78K  /  15 Page

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    Nanya Techology
Part No. NT5DS32M8BF NT5DS64M4BT
OCR Text ...d data mask referenced to both edges of dqs ? burst lengths: 2, 4, or 8 ? cas latency: 2.5, 3 ? auto precharge option for each burst access ? auto refresh and self refresh modes ? 7.8 m s maximum average periodic refresh interval ? sstl_2...
Description (NT5DSxxMxBx) 256Mb DDR SDRAM

File Size 1,953.01K  /  80 Page

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    Alliance Semiconductor, Corp.
ALSC[Alliance Semiconductor Corporation]
Part No. AS7C3364PFS36A-166TQI AS7C3364PFS32A AS7C3364PFS32A-100TQC AS7C3364PFS32A-100TQI AS7C3364PFS32A-133TQC AS7C3364PFS32A-133TQI AS7C3364PFS32A-150TQC AS7C3364PFS32A-150TQI AS7C3364PFS32A-166TQC AS7C3364PFS32A-166TQI AS7C3364PFS36A AS7C3364PFS36A-100TQC AS7C3364PFS36A-100TQI AS7C3364PFS36A-133TQC AS7C3364PFS36A-133TQI AS7C3364PFS36A-150TQC AS7C3364PFS36A-150TQI AS7C3364PFS36A-166TQC
OCR Text ...sampled on all subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled Low, and both address strobes are High. Burst operation is selectable with the LBO input. With LBO unconnected or ...
Description 3.3V 64K X 32/36 pipeline burst synchronous SRAM 64K X 36 STANDARD SRAM, 9 ns, PQFP100
3.3V 64K X 32/36 pipeline burst synchronous SRAM 64K X 36 STANDARD SRAM, 10 ns, PQFP100
3.3V 64K X 32/36 pipeline burst synchronous SRAM 64K X 32 STANDARD SRAM, 10 ns, PQFP100
DIODE ZENER SINGLE 1000mW 16Vz 15.5mA-Izt 0.05 5uA-Ir 12.2Vr DO41-GLASS 5K/REEL 64K X 36 STANDARD SRAM, 12 ns, PQFP100
3.3V 64K X 32/36 pipeline burst synchronous SRAM 64K X 32 STANDARD SRAM, 12 ns, PQFP100

File Size 216.30K  /  11 Page

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    Alliance Semiconductor ...
ALSC[Alliance Semiconductor Corporation]
Alliance Semiconductor, Corp.
Part No. AS7C3364FT36B-80TQIN AS7C3364FT32B AS7C3364FT32B-10TQC AS7C3364FT32B-10TQCN AS7C3364FT32B-10TQI AS7C3364FT32B-10TQIN AS7C3364FT32B-65TQC AS7C3364FT32B-65TQCN AS7C3364FT32B-65TQI AS7C3364FT32B-65TQIN AS7C3364FT32B-75TQC AS7C3364FT32B-75TQCN AS7C3364FT32B-75TQI AS7C3364FT32B-75TQIN AS7C3364FT32B-80TQC AS7C3364FT32B-80TQCN AS7C3364FT32B-80TQI AS7C3364FT32B-80TQIN AS7C3364FT36B-10TQC AS7C3364FT36B-10TQCN AS7C3364FT36B-10TQI AS7C3364FT36B-10TQIN AS7C3364FT36B-65TQC AS7C3364FT36B-65TQCN AS7C3364FT36B-65TQI AS7C3364FT36B-65TQIN AS7C3364FT36B-75TQC AS7C3364FT36B-75TQCN AS7C3364FT36B-75TQI AS7C3364FT36B-75TQIN AS7C3364FT36B-80TQC AS7C3364FT36B-80TQCN AS7C3364FT36B-80TQI AS7C3364FT32-36BV.1.2
OCR Text ...sampled on all subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled low and both address strobes are high. Burst mode is selectable with the LBO input. With LBO unconnected or driven...
Description From old datasheet system
Shielding Gasket; Gasket Style:D-Shaped; Body Material:Beryllium Copper alloy #C17200; Height:.11"; Length:16"; Mounting Type:Adhesive; Thickness:.0027"; Width:.28" 64K X 32 STANDARD SRAM, 10 ns, PQFP100
3.3V 64K x 32/36 Flow Through Synchronous SRAM 64K X 32 STANDARD SRAM, 6.5 ns, PQFP100
3.3V 64K x 32/36 Flow Through Synchronous SRAM 64K X 36 STANDARD SRAM, 7.5 ns, PQFP100

File Size 405.04K  /  19 Page

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Part No. K7A403600M-TC11
OCR Text ...zz) are sampled on rising clock edges. the start and duration of the burst access is controlled by adsc , adsp and adv and chip select pins. the accesses are enabled with the chip select signals and output enabled signals. wait states...
Description 128K X 36 CACHE SRAM, 4 ns, PQFP100

File Size 406.29K  /  15 Page

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    Alliance Semiconductor, Corp.
ALSC[Alliance Semiconductor Corporation]
Alliance Semiconductor ...
Part No. AS7C332MPFS18A-200TQIN AS7C332MPFS18A AS7C332MPFS18A-133TQC AS7C332MPFS18A-133TQCN AS7C332MPFS18A-133TQI AS7C332MPFS18A-133TQIN AS7C332MPFS18A-166TQC AS7C332MPFS18A-166TQCN AS7C332MPFS18A-166TQI AS7C332MPFS18A-166TQIN AS7C332MPFS18A-200TQC AS7C332MPFS18A-200TQCN AS7C332MPFS18A-200TQI
OCR Text ...sampled on all subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled low and both address strobes are high. Burst mode is selectable with the LBO input. With LBO unconnected or driven...
Description 3.3V 2M x 18 pipelined burst synchronous SRAM 2M X 18 STANDARD SRAM, 3.1 ns, PQFP100

File Size 489.68K  /  19 Page

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    Alliance Semiconductor, Corp.
ALSC[Alliance Semiconductor Corporation]
Alliance Semiconductor ...
Part No. AS7C33256PFS18A-166TQI AS7C33256PFS16A AS7C33256PFS16A-100TQC AS7C33256PFS16A-100TQI AS7C33256PFS16A-133TQC AS7C33256PFS16A-133TQI AS7C33256PFS16A-150TQC AS7C33256PFS16A-150TQI AS7C33256PFS16A-166TQC AS7C33256PFS16A-166TQI AS7C33256PFS18A AS7C33256PFS18A-100TQC AS7C33256PFS18A-100TQI AS7C33256PFS18A-133TQC AS7C33256PFS18A-133TQI AS7C33256PFS18A-150TQC AS7C33256PFS18A-150TQI AS7C33256PFS18A-166TQC
OCR Text ...sampled on all subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled LOW and both address strobes are HIGH. Burst operation is selectable with the LBO input. With LBO unconnected or d...
Description 3.3V 256K x 16/18 pipeline burst synchronous SRAM
3.3V 256K×18 Ppipeline Burst Synchronous SRAM(3.3V 256K×18流水线脉冲同步静态RAM) 3.3 256K × 18 Ppipeline突发同步SRAM的电压(3.3V 256K × 18流水线脉冲同步静态内存)
3.3V 256K 】 16/18 pipeline burst synchronous SRAM
3.3V 256K x 16 pipeline burst synchronous SRAM, clock speed - 133MHz
   3.3V 256K × 16/18 pipeline burst synchronous SRAM

File Size 208.83K  /  11 Page

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