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    PROMOS TECHNOLOGIES INC
Part No. V55C3256164VBUG10 V55C3256164VBUK7E V55C3256164VBUK7PC
OCR Text ... activate command cycle, a0-a12 defines the row address (ra0-ra12) when sampled at the rising clock edge. during a read or write command cycle, a0-an defines the column address (ca0-can) when sampled at the rising clock edge.can depends ...
Description SYNCHRONOUS DRAM, PBGA54

File Size 547.81K  /  46 Page

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    INTEGRATED SILICON SOLUTION INC
Part No. IS42S32160C-6BL
OCR Text ...1 input bank select:bs0 and bs1 defines to which bank the bankactivate,read,write,or bankprecharge command is being applied. a0-a12 input address inputs: a0-a12 are sampled during the bankactivate command (row address a0-a12) and read/...
Description 16M X 32 SYNCHRONOUS DRAM, 5.4 ns, PBGA90

File Size 1,412.79K  /  60 Page

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    MPC9446AC MPC9446ACR2

Integrated Device Technology
Part No. MPC9446AC MPC9446ACR2
OCR Text ... input circuitry. v cc voltage defines the input threshold and levels. v cca (2) 2. v cca is the positive power supply of the bank a outputs. v cca voltage defines bank a output levels. v ccb (3) 3. v ccb is the positive power supply of...
Description 3.3V and 2.5V, LVCMOS Clock Fanout Buffer

File Size 357.82K  /  12 Page

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    VECTRON INTERNATIONAL
Part No. VCC1-B1D-25M000 VECTRONINTERNATIONAL-VCC1-B6C-FREQ VCC1-A0B-FREQ VCC1-H1D-FREQ VCC1-G5C-FREQ VCC1-G5E-FREQ VCC1-A0A-FREQ
OCR Text ...s recommended . 2. figure 1 defines these parameters. figure 2 illustrates the operating conditions under which these parameters are tested and specified. 3. symmetry is measured defined as on time/period. 4. includes cali...
Description CRYSTAL OSCILLATOR, CLOCK, 25 MHz, CMOS OUTPUT
CRYSTAL OSCILLATOR, CLOCK, 0.012 MHz - 125 MHz, CMOS OUTPUT
CRYSTAL OSCILLATOR, CLOCK, 0.048 MHz - 172 MHz, CMOS OUTPUT
CRYSTAL OSCILLATOR, CLOCK, 0.012 MHz - 172 MHz, CMOS OUTPUT

File Size 243.64K  /  10 Page

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    HYNIX SEMICONDUCTOR INC
Part No. HMT351U6BFR8C-G7 HMT325U6BFR8C-H9 HMT351U7BFR8C-H9 HMT312U6BFR6C-H9
OCR Text ...te command cycle, address input defines the row address (ra0?ra15). during a read or write command cycl e, address input defines the column address. in addition to the column a ddress, ap is used to invoke autopre- charge operation at the...
Description 512M X 64 DDR DRAM MODULE, DMA240
256M X 64 DDR DRAM MODULE, DMA240
512M X 72 DDR DRAM MODULE, DMA240
128M X 64 DDR DRAM MODULE, DMA240

File Size 592.57K  /  59 Page

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