...tial/Interleave * Auto Refresh (cbr) * Self Refresh with programmable refresh periods * 4096 refresh cycles every 64 ms * Random column address every clock cycle * Programmable CAS latency (2, 3 clocks) * Burst read/write and burst read/sin...
16Meg x 8 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM
...arge and controlled precharge * cbr (Auto) refresh and self refresh * x4, x8, x16 organization * Single 3.3 V 0.3 V power supply * LVTTL compatible inputs and outputs * 4,096 refresh cycles / 64 ms * Burst termination by Burst stop command...
...cheduling * Hardware support of cbr/VBR/ABR/UBR service * Supports multi-cell burst transfer for transmission and reception * MIB counter function * Supports LAN emulation function * Receive FIFO of 96 cells * External PHY devices connectab...
..., execute Power on sequence and cbr (auto) Refresh before proper device operation is achieved. Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipat...
...onses/telemetry via the CRR and cbr (if used) pins. Note: in CT mode, BAT1 must be connected to the l-busses. In RT mode, the CITSEL, MOD, CLK, SYNC and INV pins are disabled and the clocks are supplied by the l-bus BAR in response to the s...
...by Average Self Refresh Current cbr cycle with tRAS > tRASS min., (L-version only) CAS held low, WE = VCC - 0.2V, Address and DIN = VCC - 0.2V or 0.2V VCC Supply Current, during CAS-before-RAS Refresh 50 60 70
RAS VCC - 0.2 V, CAS...
...y back up current (Standby with cbr refresh) (L-version) Input leakage current Output leakage current Output high voltage Output low voltage
ICC3 ICC5 ICC6 ICC7 ICC10
-- -- -- -- --
110 -- 5 --
100 -- 5 --
90 5 90 90
1,048,576-word x 4-bit dynamic random access memory, 80ns 1,048,576-word x 4-bit dynamic random access memory, 60ns 1/048/576-word X 4-bit Dynamic Random Access Memory 1,048,576-word x 4-bit dynamic random access memory, 70ns
...re RAS refresh, Hidden refresh, cbr self refresh(-6S,-7S) capabilities. Early-write mode and OE and W to control output buffer impedance 1024 refresh cycles every 16.4ms (A0~A9) 1024refresh cycle every128ms (A0~A9)* *: Applicable to self re...
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC EDO (HYPER PAGE MODE) 4194304-BIT (1048576-WORD BY 4-BIT) DYNAMIC RAM EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
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