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For sleep Found Datasheets File :: 19929    Search Time::2.484ms    
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    AM29DL322D/323D/324D

Advanced Micro Devices
Part No. AM29DL322D/323D/324D
OCR Text ... 200 na in standby or automatic sleep mode minimum 1 million writ e cycles guaranteed per sector 20 year data retention at 125 c ? reliable operation for the life of the system software features data management software (dms) ? amd-sup...
Description 200V Single N-Channel Hi-Rel MOSFET in a TO-205AF package; A JANTX2N6790 with Standard Packaging
32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory

File Size 675.55K  /  54 Page

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    Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
Part No. CY7C1484V25-167AXC CY7C1484V25-250BZC CY7C1484V25-250BZXI CY7C1484V25-167BZC CY7C1484V25-167BZI CY7C1484V25-250BZXC CY7C1484V25-250BZI CY7C1484V25-200BZXI CY7C1484V25-200BZXC CY7C1484V25-200BZI CY7C1484V25-167BZXC CY7C1484V25-200BZC CY7C1484V25-167BZXI CY7C1485V25-200AXC CY7C1485V25-200AXI CY7C1485V25-250AXC CY7C1485V25-250AXI CY7C1485V25-250BZXC CY7C1485V25-200BZXI CY7C1485V25-200BZXC CY7C1485V25-167BZXI CY7C1485V25-167BZXC CY7C1485V25-167AXI CY7C1485V25-167AXC CY7C1485V25-200BZC CY7C1485V25-200BZI CY7C1484V25-167AXI CY7C1484V25-250AXC C1484V25-200AXI
OCR Text ...compatible boundary scan ? ?zz? sleep mode option functional description [1] the cy7c1484v25/cy7c1485v25 sram integrates 2m x 36/4m x 18 sram cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst ope...
Description 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM 4M X 18 CACHE SRAM, 3 ns, PBGA165
72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM 2M X 36 CACHE SRAM, 3.4 ns, PQFP100
72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM 2M X 36 CACHE SRAM, 3 ns, PQFP100

File Size 899.27K  /  26 Page

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    LTC1401

Linear Technology Corporation
Part No. LTC1401
OCR Text ...ree power saving modes: nap and sleep, through the serial interface and shutdown by setting the shdn pin to zero. in nap mode, it consumes only 1.5mw of power and can wake up and convert immediately. in sleep (shutdown) mode, it consumes 19...
Description Complete SO-8, 12-Bit, 200ksps ADC with Shutdown(SO-8封装2200ksps,模数转换器(带关断
Complete SO-8, 12-Bit, 200kspsADC with Shutdown

File Size 306.31K  /  20 Page

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    CY7C1351F CY7C1351F-100AC CY7C1351F-100AI CY7C1351F-100BGC CY7C1351F-100BGI CY7C1351F-117AC CY7C1351F-117AI CY7C1351F-11

Cypress Semiconductor, Corp.
Cypress Semiconductor Corp.
CYPRESS[Cypress Semiconductor]
Part No. CY7C1351F CY7C1351F-100AC CY7C1351F-100AI CY7C1351F-100BGC CY7C1351F-100BGI CY7C1351F-117AC CY7C1351F-117AI CY7C1351F-117BGC CY7C1351F-117BGI CY7C1351F-133AC CY7C1351F-133AI CY7C1351F-133BGC CY7C1351F-133BGI CY7C1351F-66AC CY7C1351F-66AI CY7C1351F-66BGC CY7C1351F-66BGI CY7C1351
OCR Text ...NPUT REGISTER READLOGIC E sleep Control 1 Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 38...
Description 4-Mb (128K x 36) Flow-through SRAM with NoBLArchitecture 128K X 36 ZBT SRAM, 7.5 ns, PQFP100
4-Mb (128K x 36) Flow-through SRAM with NoBLArchitecture 128K X 36 ZBT SRAM, 11 ns, PBGA119
4-Mb (128K x 36) Flow-through SRAM with NoBLArchitecture 128K X 36 ZBT SRAM, 8 ns, PQFP100
4-Mb (128K x 36) Flow-through SRAM with NoBLArchitecture 128K X 36 ZBT SRAM, 8 ns, PBGA119
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture
4-Mb (128K x 36) Flow-through SRAM with NoBL Architecture

File Size 423.97K  /  15 Page

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    SAMSUNG SEMICONDUCTOR CO. LTD.
Part No. K7P801811M-H20 K7P801811M-H21 K7P801811M-H25 K7P803611M-H20 K7P803611M-H21 K7P803611M-H25
OCR Text ...re than 0.5v during power-down. sleep mode sleep mode is a low power mode initiated by bringing the asynchronous zz pin high. during sleep mode, all other inputs are ignor ed and outputs are brought to a high-impedance state. sleep mode cur...
Description 256Kx36 & 512Kx18 SRAM
256Kx36 & 512Kx18 SRAM

File Size 213.93K  /  13 Page

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    EM78811

EMC[ELAN Microelectronics Corp]
Part No. EM78811
OCR Text ...es (internal clock 3.679MHz) 1. sleep mode : CPU and 3.679MHz clock turn off, 32.768KHz clock turn off 2. Idle mode : CPU and 3.679 MHz clock turn off, 32.768KHz clock turn on 3. Green mode : 3.679MHz clock turn off, CPU and 32.768KHz clock...
Description 8-BIT MICRO-CONTROLLER FOR TELECOM PRODUCT

File Size 162.49K  /  33 Page

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    SAMSUNG SEMICONDUCTOR CO. LTD.
Part No. K7P801811B-HC27 K7P801811B-HC30 K7P801811B-HC25 K7P801811B-HC33
OCR Text ...re than 0.5v during power-down. sleep mode sleep mode is a low power mode initiated by bringing the asynchronous zz pin high. during sleep mode, all other inputs are ignor ed and outputs are brought to a high-impedance state. sleep mode cur...
Description 256Kx36 & 512Kx18 Synchronous Pipelined SRAM
256Kx36 & 512Kx18 Synchronous Pipelined SRAM 256Kx36

File Size 249.68K  /  13 Page

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    EM78P156EL EM78P156ELAS EM78P156ELKM EM78P156ELM EM78P156ELP

ELAN Microelectronics Corp
Part No. EM78P156EL EM78P156ELAS EM78P156ELKM EM78P156ELM EM78P156ELP
OCR Text ...3V/32KHz * Typically 1 A during sleep mode * 1K x 13 bits on chip ROM * One security register to prevent intrusion of OTP memory codes * One configuration register to accommodate user's requirements * 48x 8 bits on chip registers (SRAM, gen...
Description 8-bit microprocessor designed and developed with low-power and high-speed CMOS technology

File Size 578.39K  /  39 Page

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    EM78P156E EM78P156E.PDF

义隆
EMC [ELAN Microelectronics Corp]
Part No. EM78P156E EM78P156E.PDF
OCR Text ...KHz * typical of 1 A during the sleep mode 1Kx13 bits on chip ROM One security register to prevent the code in the OTP memory from intruding One configuration register to match the user's requirements 48x8 bits on chip registers (SRAM) 2 bi...
Description From old datasheet system
8 Bit MCU
8-bit microprocessor with low-power and high-speed CMOS technology

File Size 141.64K  /  28 Page

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