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lvttl-to-differential Datasheet PDF File

For lvttl-to-differential Found Datasheets File :: 4367 Search Time::2.39ms
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				MICREL[Micrel Semiconductor] Micrel Semiconductor,Inc. MICREL INC
Part No.	SY10EPT20V SY10EPT20VKC SY10EPT20VKCTR SY10EPT20VZC SY10EPT20VZCTR SY100EPT20V SY100EPT20VKC SY100EPT20VKCTR SY100EPT20VZC SY100EPT20VZCTR
OCR Text	LVTTL/LVCMOS-toDIFFERENTIAL LVPECL TRANSLATOR FEATURES s s s s s s s s 3.3V and 5V power supply options 300ps typical propagation delay Di...to 800MHz typical Available in 8-pin MSOP and SOIC package SY10EPT20V SY100EPT20V DESCRIPTION ...
Description	3.3V/5V LVTTL/LVCMOS-to- DIFFERENTIAL LVPECL TRANSLATOR
File Size	85.84K / 8 Page	View it Online	Download Datasheet

				SONY[Sony Corporation]
Part No.	CXK77B3610GB- CXK77B3610GB-6 CXK77B3610GB-7 CXK77B3610GB
OCR Text	...142MHz * Inputs and outputs are LVTTL/LVCMOS compatible * Single 3.3V power supply: 3.3V 0.15V * Byte-write possible * OE asynchronization ...to change products and specifications without prior notice. This information does not convey any lic...
Description	High Speed 1MBit Bi-CMOS Synchronous Static RAM(高M位Bi-CMOS同步静态RAM) High Speed Bi-CMOS Synchronous Static RAM From old datasheet system
File Size	197.33K / 16 Page	View it Online	Download Datasheet

				CYPRESS SEMICONDUCTOR CORP CYPRESS[Cypress Semiconductor] Cypress Semiconductor, Corp.
Part No.	CY29940 CY29940AC CY29940ACT CY29940AI CY29940AIT
OCR Text	... clock support LVPECL or LVCMOS/LVTTL clock input LVCMOS/LVTTL compatible inputs 18 clock outputs: drive up to 36 clock lines 150 ps max. output-to-output skew Dual or single supply operation: -- 3.3V core and 3.3V outputs -- 3.3V core and ...
Description	2.5V or 3.3V/ 200-MHz/ 1:18 Clock Distribution Buffer 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer 29940 SERIES, LOW SKEW CLOCK DRIVER, 18 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
File Size	188.76K / 7 Page	View it Online	Download Datasheet

				CYPRESS[Cypress Semiconductor]
Part No.	CY29949 CY29949AC CY29949ACT CY29949AI CY29949AIT
OCR Text	...lock support * LVPECL or LVCMOS/LVTTL clock input * LVCMOS-/LVTTL-compatible outputs * 15 clock outputs: drive up to 30 clock lines * 1X and 1/2X configurable outputs * Output three-state control * 350 ps max. output-to-output skew * Pin co...
Description	2.5V or 3.3V 200-MHz 1:15 Clock Distribution Buffer
File Size	65.02K / 7 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7B993V-5AC CY7B993V-7AC CY7B994V CY7B994V-5AC CY7B994V-5AI CY7B994V-5BBC CY7B994V-7AC
OCR Text	...Zero input-to-output delay * 18 LVTTL 50% duty-cycle outputs capable of driving 50 terminated lines * Commercial Temp. Range with 16 outputs at 185 MHz * Industrial Temp. Range with 6 outputs at 185 MHz * 3.3V LVTTL/LV Differential (LVPECL)...
Description	High-Speed Multi-Phase PLL Clock Buffer
File Size	287.78K / 14 Page	View it Online	Download Datasheet

				Fairchild Semiconductor, Corp. FAIRCHILD[Fairchild Semiconductor]
Part No.	FIN1017 FIN1017K8X FIN1017M FIN1017MX
OCR Text	...chnology. The driver translates LVTTL signal levels to LVDS levels with a typical differential output swing of 350 mV which provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transf...
Description	3.3V LVDS 1-Bit High Speed Differential Driver 3.3 LVDS位高速差分驱动器 From old datasheet system
File Size	621.03K / 8 Page	View it Online	Download Datasheet

				FAIRCHILD[Fairchild Semiconductor]
Part No.	FIN1018 FIN1018K8X FIN1018M FIN1018MX
OCR Text	...l input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock or data. The FIN1018 can be paired with its companion ...
Description	3.3V LVDS 1-Bit High Speed Differential Receiver From old datasheet system
File Size	1,039.08K / 8 Page	View it Online	Download Datasheet

				Fairchild Semiconductor, Corp. FAIRCHILD[Fairchild Semiconductor]
Part No.	FIN1019 FIN1019M FIN1019MTC FIN1019MTCX FIN1019MX
OCR Text	...chnology. The driver translates LVTTL signals to LVDS levels with a typical differential output swing of 350mV and the receiver translates LVDS signals, with a typical differential input threshold of 100mV, into LVTTL levels. LVDS technolog...
Description	3.3V LVDS High Speed Differential Driver/Receiver; Package: TSSOP; No of Pins: 14; Container: Tape & Reel LINE TRANSCEIVER, PDSO14 From old datasheet system
File Size	1,465.52K / 14 Page	View it Online	Download Datasheet

				http:// ICST[Integrated Circuit Systems]
Part No.	ICS952001
OCR Text	...I_STOP# PCI clock outputs. 3.3V LVTTL input for selecting the current multiplier for CPU outputs. Clock output for super I/O/USB default is ...to power down the device into a low power state. The internal clocks are disabled and the VCO and th...
Description	Preliminary Product Previes SIS645, P4 Main Clock (P)
File Size	208.65K / 17 Page	View it Online	Download Datasheet

				ICST[Integrated Circuit Systems]
Part No.	ICS952004
OCR Text	...I_STOP# PCI clock outputs. 3.3V LVTTL input for selecting the current multiplier for CPU outputs. Clock output for super I/O/USB default is ...to power down the device into a low power state. The internal clocks are disabled and the VCO and th...
Description	Programmable Timing Control Hub⑩ for P4⑩ processor Programmable Timing Control Hub for P4 processor
File Size	168.23K / 19 Page	View it Online	Download Datasheet

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