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Altera Corp
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| Part No. |
EP610PC-15
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| OCR Text |
... programmed for D, T, SR, or JK flipflop operation or can be bypassed for combinatorial operation. In addition, macrocell registers can be individually clocked either by a global clock or by any input or feedback path to the AND array. Alte... |
| Description |
IC,SIMPLE-EPLD,PAL-TYPE,CMOS,DIP,24PIN,PLASTIC
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| File Size |
311.73K /
42 Page |
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it Online |
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ST Microelectronics
STMICROELECTRONICS[STMicroelectronics]
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| Part No. |
M74HCT648 M74HCT646 2127 M74HCT646B1R M74HCT648M1R M74HCT648B1R M74HCT646M1R
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| OCR Text |
... bus are stored to the internal flipflop on low to high transition of the clock pulse. The states of the internal flip-flops output directly to the B bus The A bus are outputs and the B bus are inputs The data at the B bus are displayed at ... |
| Description |
HCT646 OCTAL BUS TRANSCEIVER/REGISTER 3-STATE HCT648 OCTAL BUS TRANSCEIVER/REGISTER 3-STATE / INV.
HCT646 OCTAL BUS TRANSCEIVER/REGISTER 3-STATE HCT648 OCTAL BUS TRANSCEIVER/REGISTER 3-STATE, INV.
From old datasheet system
HCT646 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE)HCT648 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE, INV.)
HCT646 OCTAL BUS TRANSCEIVER/REGISTER 3-STATE HCT648 OCTAL BUS TRANSCEIVER/REGISTER 3-STATE, INV.
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| File Size |
199.88K /
12 Page |
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it Online |
Download Datasheet |
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LATTICE[Lattice Semiconductor]
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| Part No. |
MACH445-12 MACH445-15 MACH445-15YC MACH445-12YC MACH445-20YC
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| OCR Text |
... configured with or without the flipflop, and whether or not the macrocell drives an I/O cell. The flip-flop clock depends on the mode selected for the macrocell. In synchronous mode, any of the PAL block clocks generated by the clock Gener... |
| Description |
High-Density EE CMOS Programmable Logic
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| File Size |
206.54K /
28 Page |
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it Online |
Download Datasheet |
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MAXIM - Dallas Semiconductor
MAXIM[Maxim Integrated Products]
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| Part No. |
MAX9381
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| OCR Text |
...tial data, differential clock D flipflop is pin compatible with the ON Semiconductor MC100EP52, with the added benefit of a wider supplyvoltage range from 2.25V to 5.5V and 25% lower supply current. Data enters the master part of the flip-f... |
| Description |
Lowest Power 3.0GHz ECL/PECL Differential Data and clock D Flip-Flop
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| File Size |
185.97K /
7 Page |
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it Online |
Download Datasheet |
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FAIRCHILD[Fairchild Semiconductor]
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| Part No. |
74VHCT574A 74VHCT574ASJ 74VHCT574AN 74VHCT574AMTC 74VHCT574AM 74VHCT574ASJX 74VHCT574N
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| OCR Text |
... dissipation. This 8-bit D-type flipflop is controlled by a clock input (CP) and an Output Enable input (OE). When the OE input is HIGH, the eight outputs are in a high impedance state. Protection circuits ensure that 0V to 7V can be applie... |
| Description |
ACTIVE HIGH P-P WITH WDI, MR, -40C to 125C, 5-SOT-23, T/R
Octal D-Type Flip-Flop with 3-STATE Outputs
Active low P-P with WDI, MR, -40C to 125C, 5-SOT-23, T/R
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| File Size |
92.66K /
7 Page |
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it Online |
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