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  divider fanout Datasheet PDF File

For divider fanout Found Datasheets File :: 365    Search Time::5.922ms    
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    ISPPAC-CLK5610V-01T100I ISPPAC-CLK5610V-01T48C ISPPAC-CLK5610V-01T48I ISPPAC-CLK5610V-01TN100C ISPPAC-CLK5610V-01TN48I I

LATTICE[Lattice Semiconductor]
Part No. ISPPAC-CLK5610V-01T100I ISPPAC-CLK5610V-01T48C ISPPAC-CLK5610V-01T48I ISPPAC-CLK5610V-01TN100C ISPPAC-CLK5610V-01TN48I ISPPAC-CLK5620V-01T100C ISPPAC-CLK5620V-01T100I ISPPAC-CLK5620V-01T48I ISPPAC-CLK5620V-01TN100C ISPPAC-CLK5620V-01TN100I ISPPAC-CLK5620V-01TN48C ISPPAC-CLK5620V-01TN48I ISPCLOCK5600 ISPPAC-CLK5610V-01T100C ISPPAC-CLK5610V-01TN100I ISPPAC-CLK5610V-01TN48C
OCR Text ...ide ratio controlled by - Input divider (5 bits) - Feedback divider (5 bits) - Five output dividers (5 bits) * Programmable On-chip Loop Fil...fanout PLL-based clock drivers designed for use in high performance communications and computing app...
Description In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer

File Size 814.68K  /  47 Page

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    CY29351AI CY29351AIT CY29351

CYPRESS[Cypress Semiconductor]
Part No. CY29351AI CY29351AIT CY29351
OCR Text ...rence clock set by the feedback divider, see the Table 1. When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not...
Description 2.5V or 3.3V, 200-MHz, 9-Output Zero Delay Buffer

File Size 284.36K  /  8 Page

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    PC107AMZFU100LC PC107AMZFU100L PC107AVZFU100LD PC107AVZFU100LC PC107AVZFU100L PC107A PC107AMGHU100L PC107AMGHU100LC PC10

ATMEL[ATMEL Corporation]
Part No. PC107AMZFU100LC PC107AMZFU100L PC107AVZFU100LD PC107AVZFU100LC PC107AVZFU100L PC107A PC107AMGHU100L PC107AMGHU100LC PC107AMGHU100LD PC107AMZFU100LD PC107AVGHU100L PC107AVGHU100LC PC107AVGHU100LD
OCR Text ...s operating frequencies and bus divider ratios 32-bit address bus, 64/32-bit data bus supported at 100 MHz Supports full memory coherency Supports optional local bus slave Decoupled address and data buses for pipelining of 60x accesses Stor...
Description PCI Bridge Memory Controller

File Size 448.56K  /  50 Page

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    MPC932

Motorola, Inc
Part No. MPC932
OCR Text ...VCO lock range and the feedback divider. DC CHARACTERISTICS (TA = 0 to 70C, VCC = 3.3V 5%) Symbol VIH VIL VOH VOL IIN ICC ICCPLL CIN Cha...fanout of the MPC932 clock driver is effectively doubled due to its capability to drive multiple lin...
Description LOW VOLTAGE PLL CLOCK DRIVER

File Size 111.02K  /  8 Page

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    MPC9330

Motorola, Inc.
Part No. MPC9330
OCR Text ...ference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency ...fanout of 1:12. The device is packaged in a 7x7 mm2 32-lead LQFP package. 1. Design target, pending ...
Description 3.3V / 2.5V 1:6 LVCMOS PLL CLOCK GENERATOR

File Size 213.25K  /  16 Page

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    MPC9351D MPC9351

Freescale Semiconductor, Inc
Part No. MPC9351D MPC9351
OCR Text ... clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency ...fanout of 1:18. The device is packaged in a 7x7 mm2 32-lead LQFP package. FA SUFFIX LQFP PACKAGE CA...
Description LOW VOLTAGE PLL CLOCK DRIVER

File Size 304.91K  /  12 Page

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    MPC9774

Motorola, Inc
Freescale Semiconductor, Inc
Part No. MPC9774
OCR Text ...ference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency ...fanout of 1:12. The device is pin and function compatible to the MPC974 and is packaged in a 52-lead...
Description From old datasheet system
3.3V / 2,5V 1:14 LVCMOS PLL CLOCK GENERATOR

File Size 213.47K  /  16 Page

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    MPC9600 MPC9600FA

Freescale Semiconductor, Inc
MOTOROLA[Motorola Inc]
Motorola, Inc
Part No. MPC9600 MPC9600FA
OCR Text ...e feedback input FB_IN. The QFB divider ratio is configurable and determines the PLL frequency multiplication factor when QFB is directly co...fanout buffers for the inner branches of the clock distribution tree. All control inputs accept LVCM...
Description LOW VOLTAGE 2.5V AND 3.3 V CMOS PLL CLOCK DRIVER
LOW VOLTAGE 2.5 V AND 3.3 V CMOS PLL CLOCK DRIVER

File Size 320.52K  /  16 Page

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    http://
ICST[Integrated Circuit Systems]
Part No. ICS84314AYT ICS84314AY ICS84314 ICS84314AYLF ICS84314AYLFT
OCR Text ...are programmable and the output divider is hard-wired for divide by 2 thus providing a frequency range of 125MHz to 350MHz. In serial progra...fanout BUFFER nP_LOAD input is initially LOW. The data on inputs M0 through M8 is passed directly t...
Description 350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/fanout BUFFER
From old datasheet system
350MHZ CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/fanout BUFFER

File Size 209.12K  /  18 Page

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    MPC9331

Motorola, Inc
Part No. MPC9331
OCR Text ...ference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency ...fanout of 1:12. The device is packaged in a 7x7 mm2 32-lead LQFP package. (c) Freescale Semicondu...
Description 3.3 V 1:6 LVCMOS PLL CLOCK GENERATOR

File Size 305.14K  /  12 Page

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For divider fanout Found Datasheets File :: 365    Search Time::5.922ms    
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