| |
|
 |
ELPIDA[Elpida Memory]
|
| Part No. |
EBE20RE4AAFA-5C-E EBE20RE4AAFA EBE20RE4AAFA-4A-E
|
| OCR Text |
...ata transfer is realized by the 4bits prefetch-pipelined architecture. Data strobe (DQS and /DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked... |
| Description |
2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 1 Rank)
|
| File Size |
180.88K /
22 Page |
 View
it Online |
Download Datasheet
|
| |
|
|
ELPIDA[Elpida Memory]
|
| Part No. |
EBE21RD4ABHA-5C-E EBE21RD4ABHA EBE21RD4ABHA-4A-E
|
| OCR Text |
...ata transfer is realized by the 4bits prefetchpipelined architecture. Data strobe (DQS and /DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked ... |
| Description |
2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 2 Ranks)
|
| File Size |
165.80K /
22 Page |
View
it Online |
Download Datasheet |
| |
|
|
ELPIDA[Elpida Memory]
|
| Part No. |
EBE21RD4AEFA-5C-E EBE21RD4AEFA EBE21RD4AEFA-4A-E
|
| OCR Text |
...ata transfer is realized by the 4bits prefetchpipelined architecture. Data strobe (DQS and /DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked ... |
| Description |
2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 2 Ranks)
|
| File Size |
182.67K /
22 Page |
View
it Online |
Download Datasheet |
| |
|
|
ELPIDA[Elpida Memory]
|
| Part No. |
EBE41RE4AAHA-5C-E EBE41RE4AAHA EBE41RE4AAHA-4A-E
|
| OCR Text |
...ata transfer is realized by the 4bits prefetchpipelined architecture. Data strobe (DQS and /DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked ... |
| Description |
4GB Registered DDR2 SDRAM DIMM (512M words x 72 bits, 2 Ranks)
|
| File Size |
189.89K /
22 Page |
View
it Online |
Download Datasheet |
| |
|
|
ELPIDA[Elpida Memory]
|
| Part No. |
EBE51RD8ABFA-5C-E EBE51RD8ABFA EBE51RD8ABFA-4A-E
|
| OCR Text |
...ata transfer is realized by the 4bits prefetch-pipelined architecture. Data strobe (DQS and /DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked... |
| Description |
512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
|
| File Size |
166.30K /
22 Page |
View
it Online |
Download Datasheet |
| |
|
|
ELPIDA[Elpida Memory]
|
| Part No. |
EBE51RD8AEFA-5C-E EBE51RD8AEFA EBE51RD8AEFA-4A-E
|
| OCR Text |
...ata transfer is realized by the 4bits prefetch-pipelined architecture. Data strobe (DQS and /DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked... |
| Description |
512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
|
| File Size |
180.19K /
22 Page |
View
it Online |
Download Datasheet |
| |
|
|
ELPIDA[Elpida Memory]
|
| Part No. |
EBE51RD8AGFA-6E-E EBE51RD8AGFA EBE51RD8AGFA-4A-E EBE51RD8AGFA-5C-E
|
| OCR Text |
...ata transfer is realized by the 4bits prefetch-pipelined architecture. Data strobe (DQS and /DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked... |
| Description |
512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
|
| File Size |
186.03K /
23 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|
