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ICS
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| Part No. |
ICS843002-31
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| OCR Text |
...ols, such as: * For telecom, OC-12 to E3 rate conversion, 622.08MHz to 34.368MHz, PLL ratio of 179/32 * For digital video, ITU-R601 to SMPTE...LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the V... |
| Description |
700MHz, FemtoClock? VCXO Based Frequency Translator and Jitter Attenuator
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| File Size |
276.08K /
24 Page |
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Linear Technology Corporation
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| Part No. |
LTC2222-11
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| OCR Text |
...atible Family 135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit) 105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit) 80Msps: LTC2223 (12-Bit), LTC2233 (10-...LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full s... |
| Description |
11-Bit, 105Msps ADC
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| File Size |
556.73K /
24 Page |
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it Online |
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linear
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| Part No. |
LTC2222 LTC2223
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| OCR Text |
12-Bit,105Msps/ 80Msps ADCs
FEATURES
DESCRIPTIO
Sample Rate: 105Msps/80Msps 68dB SNR up to 140MHz Input 80dB SFDR ...LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full s... |
| Description |
12-Bit,105Msps/80Msps ADCs
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| File Size |
736.78K /
24 Page |
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it Online |
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linear
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| Part No. |
LTC2231 LTC2230
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| OCR Text |
...atible Family 170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit) 135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit) 64-Pin 9mm x 9mm QFN Package
The LT...LVDS, or single-ended CMOS. There are three format options for the CMOS outputs: a single bus runnin... |
| Description |
10-Bit,170Msps/135Msps ADCs
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| File Size |
691.07K /
28 Page |
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Integrated Circuit Syst...
ICST[Integrated Circuit Systems]
INTEGRATED DEVICE TECHNOLOGY INC
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| Part No. |
M2040 M2040-01I400.0000 M2040-01-400.0000 M2040-01I533.3334 M2040-01-533.3334
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| OCR Text |
...(Top View)
18 17 16 15 14 13 12 11 10
P_SEL INIT nFOUT0 FOUT0 GND nFOUT1 FOUT1 VCC GND
Figure 1: Pin Assignment
Example Input / ...LVDS clock input Differential LVPECL/ LVDS, or single pair 1. ended LVCMOS/ LVTTL Reference clock in... |
| Description |
FREQUENCY TRANSLATION PLL WITH AUTOSWITCH
SAW PLL for Fault Tolerant Computers with automatic reference clock reselection, Loss of Lock indicator, and Hitless Switching
PHASE LOCKED LOOP, 285 MHz, CQCC36
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| File Size |
189.51K /
12 Page |
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Xilinx
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| Part No. |
XC3S5000 XC3S400 XC3S4000 XC3S2000
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| OCR Text |
...74,880 16 24 32 48 64 80 96 104 12 20 28 40 52 64 72 80 192 480 896 1,920 3,328 5,120 6,912 8,320
Device XC3S502 XC3S2002 XC3S4002 XC3S10...LVDS Lightning Data Transport (HyperTransportTM) Logic Low-Voltage Differential Signaling 2.5 N/A St... |
| Description |
(XC3S50 - XC3S5000) Spartan-3 FPGA Family
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| File Size |
1,763.79K /
204 Page |
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Analog Devices Inc
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| Part No. |
AD9430
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| OCR Text |
12-Bit, 170 MSPS/210 MSPS 3.3 V A/D Converter AD9430
FEATURES SNR = 65 dB @ fIN up to 70 MHz @ 210 MSPS ENOB of 10.6 @ fIN up to 70 MHz @ 2...LVDS at 210 MSPS 700 MHz Full Power Analog Bandwidth On-Chip Reference and Track-and-Hold Power Diss... |
| Description |
12-Bit, 170 MSPS/210 MSPS 3.3 V A/D Converter
From old datasheet system
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| File Size |
1,354.50K /
28 Page |
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it Online |
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Price and Availability
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