divider fanout pdf Datasheet P8 Full Text Search --- IC-ON-LINE


	Part Number	Hot Search : UGF10C 2KBP10M ADG1606 S2HB10 C5909 BPC817 B16NF06 T54ACS
	Product Description
	Full Text Search

divider fanout Datasheet PDF File

For divider fanout Found Datasheets File :: 347 Search Time::1.922ms
Page :: | 1 | 2 | 3 | 4 | 5 | 6 | 7 | <8> | 9 | 10 | 11 | 12 | 13 | 14 | 15 |

				Micrel Semiconductor
Part No.	SY89875U SY89875UMI SY89875UMITR
OCR Text	divider AND 1:2 SY89875U FINAL fanout BUFFER W/ INTERNAL TERMINATION FEATURES I Integrated programmable clock divider and 1:2 fanout buffer I Guaranteed AC performance over temperature and voltage: * > 2.0GHz fMAX * < 200ps tr/tf * < 15ps...
Description	2.5V, 2.0GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK divider AND 1;2 fanout BUFFER W/ INTERNAL TERMINATION
File Size	229.38K / 10 Page	View it Online	Download Datasheet

				Micrel Semiconductor http://
Part No.	SY89535LHZ SY89535LHZTR SY89534LHZTR
OCR Text	... fanout buffer Clock generator (divider) Logic translation (LVPECL, LVDS) The SY89534L and SY89535L includes a flexible input design that accepts any reference input; single-ended LVTTL/ CMOS, SSTL and differential LVPECL, LVDS, HSTL and...
Description	3.3V, PRECISION, 33MHz to 500MHz PROGRAMMABLE LVPECL AND LVDS BUS CLOCK SYNTHESIZER
File Size	105.72K / 15 Page	View it Online	Download Datasheet

				MOTOROLA[Motorola, Inc]
Part No.	MPC9653
OCR Text	...ncy range select PLL and output divider bypass select PLL enable/disable Output enable/disable (high-impedance tristate) and device reset Cl...fanout buffer with zero insertion delay will show significantly lower clock skew than clock distribu...
Description	3.3V 1:8 LVCMOS PLL CLOCK GENERATOR
File Size	290.68K / 12 Page	View it Online	Download Datasheet

				Micrel Semiconductor http://
Part No.	SY89532L08 SY89532LHZTR SY89533LHZTR
OCR Text	...d (default) VCO Select 2x 3-Bit divider A 2, 4, 6, 8, 10, 12,18 5 A EN 44 /QB2 43 QB3 42 /QB3 41 QB4 40 /QB4 3-Bit divider B 2, 4, 6, 8, 10, 12,18 9x B EN 3 39 QB5 38 /QB5 37 QB6 36 /QB6 3-Bit divider C 2, 4, 6, 8, 10, 12,18 C EN 35 QB7 34 ...
Description	3.3V, PRECISION, 33MHz to 500MHz PROGRAMMABLE LVPECL AND LVDS BUS CLOCK SYNTHESIZER
File Size	188.19K / 15 Page	View it Online	Download Datasheet


Part No.	CY7B9940V
OCR Text	...1] input 3-level input feedback divider function select . these inputs determine the function of the qfa0 and qfa1 outputs. see table 2 . ...fanout output buffers ([1:2]q[a:b][0:1]), and an output disable (dis[1:2]). the feedback bank has on...
Description	Clocks and Buffers
File Size	139.21K / 9 Page	View it Online	Download Datasheet

				PulseCore Semiconductor
Part No.	PCS5I9653AG-32-ER PCS5I9653AG-32-LR
OCR Text	...ncy range select PLL and output divider bypass select PLL enable/disable Output enable/disable (high-impedance tristate) and device reset Cl...fanout buffer with zero insertion delay will show significantly lower clock skew than clock distribu...
Description	3.3V 1:8 LVCMOS PLL Clock Generator
File Size	637.62K / 13 Page	View it Online	Download Datasheet

				PulseCore Semiconductor
Part No.	PCS5I9658G-32-LR PCS5I9658G-32-ER
OCR Text	...ncy range select PLL and output divider bypass select PLL enable/disable Output enable/disable (high-impedance tristate) and device reset Cl...fanout buffer with zero insertion delay will show significantly lower clock skew than clock distribu...
Description	3.3V 1:10 LVCMOS PLL Clock Generator
File Size	606.63K / 15 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY23FP12OXIT CY3672-USB CY23FP12OXC CY23FP12OXCT CY23FP1211 CY23FP1212
OCR Text	...an eight-bit value to reference divider -M. The divider can be any integer value 2 from 1 to 256; however, the PLL input frequency cannot be...fanout buffer (PLL Power-down enabled), the reference frequency can be lower than 10MHz. With auto p...
Description	200 MHz Field Programmable Zero Delay Buffer 200 MHz Field Programmable Zero Delay Buffer
File Size	293.47K / 15 Page	View it Online	Download Datasheet

				MOTOROLA[Motorola, Inc]
Part No.	MPC9658
OCR Text	...ncy range select PLL and output divider bypass select PLL enable/disable Output enable/disable (high-impedance tristate) and device reset Cl...fanout buffer with zero insertion delay will show significantly lower clock skew than clock distribu...
Description	3.3V 1:10 LVCMOS PLL Clock Generator
File Size	290.07K / 12 Page	View it Online	Download Datasheet

For divider fanout Found Datasheets File :: 347 Search Time::1.922ms
Page :: | 1 | 2 | 3 | 4 | 5 | 6 | 7 | <8> | 9 | 10 | 11 | 12 | 13 | 14 | 15 |