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Cypress Semiconductor, Corp.
CYPRESS SEMICONDUCTOR CORP
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| Part No. |
CY7C1372DV25-250BGC CY7C1370DV25-200AxI CY7C1372DV25-167BGxI CY7C1372DV25-200BGxC CY7C1372DV25-167AxIT CY7C1370DV25-200BGCT
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| Description |
18-mbit (512k x 36/1M x 18) Pipelined sram with NoBLArchitecture 1M x 18 ZBT sram, 2.6 ns, PBGA119
18-mbit (512k x 36/1M x 18) Pipelined sram with NoBLArchitecture 512k x 36 ZBT sram, 3 ns, PQFP100
18-mbit (512k x 36/1M x 18) Pipelined sram with NoBLArchitecture 1M x 18 ZBT sram, 3.4 ns, PBGA119
18-mbit (512k x 36/1M x 18) Pipelined sram with NoBLArchitecture 1M x 18 ZBT sram, 3 ns, PBGA119
1M x 18 ZBT sram, 3.4 ns, PQFP100
512k x 36 ZBT sram, 3 ns, PBGA119
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| File Size |
533.02K /
27 Page |
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Renesas Electronics Corporation.
Renesas Electronics, Corp.
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| Part No. |
M38230G4-xxxFP M38230G4-xxxHP M38231G4-xxxHP M38232G4-xxxFP M38232G4-xxxHP M38233G4-xxxFP M38233G4-xxxHP M38234G4-xxxFP M38234G4-xxxHP M38235G4-xxxFP M38230G6-xxxFP M38230G6-xxxHP M38231G6-xxxFP M38231G6-xxxHP M38232G6-xxxFP M38232G6-xxxHP M38233G6-xxxFP M38233G6-xxxHP M38234G6-xxxFP M38234G6-xxxHP M38235G6-xxxFP M38235G6-xxxHP M38236G6-xxxHP M38237G6-xxxFP M38237G6-xxxHP M38238G6-xxxFP M38230G7-xxxFP M38230G7-xxxHP M38231G7-xxxFP M38231G7-xxxHP M38232G7-xxxFP M38232G7-xxxHP M38233G7-xxxFP M38233G7-xxxHP M38234G7-xxxFP M38234G7-xxxHP M38235G7-xxxFP M38235G7-xxxHP M38236G7-xxxFP M38236G7-xxxHP M38237G7-xxxFP M38237G7-xxxHP M38238G7-xxxFP M38238G7-xxxHP M38239G7-xxxFP M38239G7-xxxHP M38230G8-xxxFP M38230G8-xxxHP M38231G8-xxxFP M38231G8-xxxHP M38232G8-xxxFP M38232G8-xxxHP M38233G8-xxxFP M38233G8-xxxHP M38234G8-xxxFP M38234G8-xxxHP M38235G8-xxxFP M38235G8-xxxHP M38236G8-xxxFP M38236G8-xxxHP M38237G8-xxxFP M38237G8-xxxHP M38238G8-xxxFP M38238G8-xxxHP M38230GA-xxxFP M38230GA-xxxHP M38231GA-xxxFP M38231GA-xxxHP M38232GA-xxxFP M38232GA-xxxHP M38233GA-xxxFP M38233GA-xxxHP M38234GA-xxxFP M38234GA-xxxHP M38235GA-xxxFP M38235GA-xxxHP M38236GA-xxxFP M38236GA-xxxHP M38237GA-xxxFP M38237GA-xxxHP
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| Description |
18-mbit (512k x 36/1M x 18) Flow-Through sram; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512kb x 36; Vcc (V): 3.1 to 3.6 V
36-mbit QDR(TM)-II sram 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-mbit DDR-II sram 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-mbit (1M x 36/2M x 18/512k x 72) Pipelined sram with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V
72-mbit (2M x 36/4M x 18/1M x 72) Pipelined sram with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V
18-mbit (512k x 36/1M x 18) Pipelined sram; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-mbit (1M x 36/2M x 18/512k x 72) Pipelined sram with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-mbit QDR(TM)-II sram 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
18-mbit (512k x 36/1M x 18) Flow-Through sram; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-mbit QDR(TM)-II sram 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-mbit (1M x 36/2 M x 18/512k x 72) Flow-Through sram with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-mbit(2M x 36/4M x 18/1M x 72) Pipelined sram with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V
72-mbit QDR(TM)-II sram 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
36-mbit (1M x 36/2M x 18/512k x 72) Pipelined Sync sram; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
36-mbit (1M x 36/2M x 18/512k x 72) Pipelined sram with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V
36-mbit (1M x 36/2M x 18/512k x 72) Pipelined sram with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512kb x 72; Vcc (V): 3.1 to 3.6 V
72-mbit DDR-II sram 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
Sync sram; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-mbit DDR-II sram 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
72-mbit(2M x 36/4M x 18/1M x 72) Pipelined sram with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-mbit(2M x 36/4M x 18/1M x 72) Pipelined sram with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V
72-mbit QDR(TM)-II sram 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-mbit (2M x 36/4M x 18/1M x 72) Pipelined sram with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V
72-mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync sram; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-mbit QDR(TM)-II sram 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-mbit DDR-II sram 2-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-mbit (1M x 36/2M x 18/512k x 72) Pipelined Sync sram; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
72-mbit DDR-II sram 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
18-mbit (512k x 36/1M x 18) Flow-Through sram; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机
72-mbit(2M x 36/4M x 18/1M x 72) Pipelined sram with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-mbit(2M x 36/4M x 18/1M x 72) Pipelined sram with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-mbit QDR(TM)-II sram 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-mbit QDR(TM)-II sram 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-mbit QDR(TM)-II sram 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机
Sync sram; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-mbit DDR-II sram 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-mbit DDR-II sram 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-mbit QDR(TM)-II sram 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
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| File Size |
901.80K /
76 Page |
View
it Online |
Download Datasheet |
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Cypress Semiconductor Corp.
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| Part No. |
CY7C1370DV25
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| Description |
18-mbit (512k x 36/1M x 18) Pipelined sram with NoBL Architecture(18-Mb (512k x 36/1M x 18)管道式sram（NoBL结构 18兆位（为512k × 36/1M × 18）与总线延迟建筑18 MB的（12k × 36/1M × 18）管道式静态存储器（总线延迟结构）流水线的sram
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| File Size |
507.09K /
27 Page |
View
it Online |
Download Datasheet |
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AMD Inc
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| Part No. |
AM49DL640BG
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| Description |
64 mbit (8 M x 8-Bit/4 M x 16-Bit) CMOS and 32 mbit (512k x 16-Bit) Pseudo Static RAM (Preliminary)
From old datasheet system
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| File Size |
568.45K /
61 Page |
View
it Online |
Download Datasheet |
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Cypress Semiconductor Corp.
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| Part No. |
CY7C1371D
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| Description |
18-mbit (512k x 36/1M x 18) Flow-Through sram with NoBL Architecture(18-Mb (512k x 36/1M x 18)流通式sram（NoBL结构 18兆位（为512k × 36/1M × 18）流体系结构，通过与总线延迟18 MB的（12k × 36/1M × 18）流通式的sram（总线延迟结构）的sram
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| File Size |
417.22K /
28 Page |
View
it Online |
Download Datasheet |
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Price and Availability
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