| |
|
 |
Agilent (Hewlett-Packard)
|
| Part No. |
HDMP-1638
|
| OCR Text |
...ks which are 180 degrees out of phase with each other. the parallel data is properly aligned with the rising edge of alternating clocks. for test purposes, the transceiver provides for on-chip local loop- back functionality controlled throu... |
| Description |
Gigabit Ethernet Transceiver Chip with Dual Serial I/O and Differential PECL Clock Inputs(带双路串行I/O和差分PECL时钟输入的千兆位以太网收发器)
HDMP-1638 · 1.25 GBd Transceiver Chip with Dual Serial I/O and Differential PECL Clock Inputs for GbE
|
| File Size |
250.52K /
19 Page |
 View
it Online |
Download Datasheet
|
| |
|
|
GSI Technology, Inc.
|
| Part No. |
GS4576S18GL-24IT GS4576S18GL-24T GS4576S18L-18T
|
| OCR Text |
...ck. ck is ideally 180o out of phase with ck. cs input chip select ? cs enables the command decoder when low and disables it when high. wh...aligned with data output from the lldram ii. qk x is ideally 180o out of phase with qkx. for the x... |
| Description |
DDR DRAM, PBGA144 ROHS COMPLIANT, UBGA-144
DDR DRAM, PBGA144 UBGA-144
|
| File Size |
2,462.90K /
64 Page |
View
it Online |
Download Datasheet |
| |
|
|
GSI Technology, Inc.
|
| Part No. |
GS4576C18GL-24T GS4576C18GL-24I GS4576C18L-18T
|
| OCR Text |
...ck. ck is ideally 180o out of phase with ck. cs input chip select ? cs enables the command decoder when low and disables it when high. wh...aligned with data output from the lldram ii. qk x is ideally 180o out of phase with qkx. for the x... |
| Description |
DDR DRAM, PBGA144 ROHS COMPLIANT, UBGA-144
DDR DRAM, PBGA144 UBGA-144
|
| File Size |
2,612.59K /
63 Page |
View
it Online |
Download Datasheet |
| |
|
|
Unisonic Technologies Co., Ltd.
|
| Part No. |
9170-XXCS08LF
|
| OCR Text |
...onizer and multiplier on-chip phase-locked loop for clocks synchronization synchronizes frequencies up to 107 mhz (output) @ 5.0v 1ns ...aligned (figure 4). figure 5: input and output clock waveforms with clk1 connected to fbin table 2: ... |
| Description |
107 MHz, OTHER CLOCK GENERATOR, PDSO8 0.150 INCH, ROHS COMPLIANT, SOIC-8
|
| File Size |
183.61K /
12 Page |
View
it Online |
Download Datasheet |
| |
|
|
Bourns, Inc.
|
| Part No. |
UPD48288118FF-EF25-DW1
|
| OCR Text |
... is ideally 180 degrees out of phase with ck. cs# input chip select cs# enables the commands when cs# is low and disables them when cs# ...aligned with data output from the pd48288118. qkx# is ideally 180 degrees out of phase with qkx. ... |
| Description |
16M X 18 DDR DRAM, PBGA144 18.50 X 11 MM, PLASTIC, FBGA-144
|
| File Size |
921.25K /
52 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|
