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Samsung semiconductor
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| Part No. |
K7S3236U4C
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| OCR Text |
...11m,10k,11j,11g,10e,11d,11c,10n,9m,9l 9j,10g,9f,10d,9c,9b,3b,3c,2d,3f,2g,3j,3l,3m,2n 1c,1d,2e,1g,1j,2k,1m,1n,2p data inputs q0-35 11p,10m,11...bit sequential for both rea d and write operations, requiring two full clock bus cycles. any request... |
| Description |
1Mx36 & 2Mx18 QDR II b4 SRAM
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| File Size |
440.25K /
20 Page |
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Micron Technology, Inc.
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| Part No. |
MT9V403 MT9V403C12STM
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| OCR Text |
...x 494v pixel size and type: 9.9m x 9.9m truesnap? (shuttered-node active pixel) optical format: 1/2-inch frame rate: 0-200 fram es/s...bit power: 130mw at 200 fps supply voltage: +3.3v internal intra-scene dynamic range: 60db o... |
| Description |
1/2-INCH CMOS ACTIVEPIXEL CMOS IMAGE SENSOR
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
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| File Size |
391.92K /
33 Page |
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it Online |
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Integrated Device Technology, Inc.
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| Part No. |
IDT72T36135ML5BBG IDT72T36135ML6BBGI IDT72T36135ML5BBGI
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| OCR Text |
...e space saving than the leading 9m-bit fifos ? ? ? ? ? independent read and write clocks (permit reading and writing simultaneously) ? ? ? ? ? high-performance submicron cmos technology ? ? ? ? ? industrial temperature range (?40 c to ... |
| Description |
2.5V 18M-BIT HIGH-SPEED TeraSync FIFO 36-BIT CONFIGURATIONS 524,288 x 36
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| File Size |
495.92K /
48 Page |
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it Online |
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Samsung semiconductor
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| Part No. |
K7I161882B
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| OCR Text |
...,2j,9j,1k,2k,9k 1l,9l,10l,1m,2m,9m,1n,9n,10n,1p,2p,9p no connect 3
512kx36 & 1mx18 ddrii cio b2 sram - 4 - rev 3.1 july. 2004 k7i163682b k...bit sequential for both read and write operations. synchronous pipeline read and late write enable h... |
| Description |
(K7I163682B / K7I161882B) 1Mx18-bit DDRII CIO b2 SRAM
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| File Size |
403.88K /
17 Page |
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it Online |
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SAMSUNG SEMICONDUCTOR CO. LTD.
SAMSUNG[Samsung semiconductor]
Samsung Electronic
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| Part No. |
K7I323682M K7I321882M K7M161825A-QCI65
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| OCR Text |
...,2J,9J,1K,2K,9K 1L,9L,10L,1M,2M,9M,1N,9N,10N,1P,2P,9P DESCRIPTION Input Clock Input Clock for Output Data Output Echo Clock DLL Disable when...bit sequential for both read and write operations. Synchronous pipeline read and late write enable h... |
| Description |
1Mx36 & 2Mx18 DDRII CIO b2 SRAM
512Kx36 & 1Mx18 Pipelined NtRAM
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| File Size |
375.01K /
17 Page |
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it Online |
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Price and Availability
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