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  pairs Datasheet PDF File

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    8741004BGI 8741004BGILFT ICS8741004BGI 8741004BGILF 8741004BGIT ICS8741004BIL ICS8741004I

Integrated Device Technology
Part No. 8741004BGI 8741004BGILFT ICS8741004BGI 8741004BGILF 8741004BGIT ICS8741004BIL ICS8741004I
OCR Text ...nd two 0.7V differential output pairs Bank A has two LVDS output pairs and Bank B has two 0.7V differential output pairs One differential clock input pair CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHS...
Description DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS⑩ JITTER ATTENUATOR

File Size 1,556.42K  /  20 Page

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    ICS87410041 8741004AG 8741004AGLF 8741004AGLFT 8741004AGT ICS8741004 ICS8741004AG

Integrated Device Technology
Part No. ICS87410041 8741004AG 8741004AGLF 8741004AGLFT 8741004AGT ICS8741004 ICS8741004AG
OCR Text ...nd two 0.7V differential output pairs Bank A has two LVDS output pairs and Bank B has two 0.7V differential output pairs One differential clock input pair CLK, CLK pair can accept the following differential input levels: LVPECL, LVDS, LVHST...
Description DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS JITTER ATTENUATOR
DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS⑩ JITTER ATTENUATOR

File Size 1,106.74K  /  19 Page

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    MC10E411 MC10E411FN ON0650

ONSEMI[ON Semiconductor]
Motorola, Inc
Part No. MC10E411 MC10E411FN ON0650
OCR Text ...ications, all nine differential pairs will be used and therefore terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on the same package side as the pair(s) being used on that...
Description From old datasheet system
1:9 DIFFERENTIAL ECL/PECL RAMBUS CLOCK BUFFER

File Size 128.04K  /  6 Page

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    ICS8741004 ICS8741004AG ICS8741004AGLF

Integrated Device Technology
Part No. ICS8741004 ICS8741004AG ICS8741004AGLF
OCR Text ...nd two 0.7V differential output pairs Bank A has two LVDS output pairs and Bank B has two 0.7V differential output pairs One differential clock input pair CLK, CLK pair can accept the following differential input levels: LVPECL, LVDS, LVHST...
Description DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS JITTER ATTENUATOR
DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS⑩ JITTER ATTENUATOR

File Size 701.53K  /  17 Page

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    ML4642 ML4642CQ ML4642CR

MICRO-LINEAR[Micro Linear Corporation]
Part No. ML4642 ML4642CQ ML4642CR
OCR Text ...e active TXIN pair to the RXOUT pairs and enables SQE test. If tied to 0.6 volts internal loopback is enable but SQE test is disabled. SQE and loopback are disabled when this pin is pulled high. Receive signal pair for MAU port. Receive sig...
Description AUI Multiplexer

File Size 276.11K  /  15 Page

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    CY23FP12-002 CY3692 CY23FP12OC-002 CY23FP12OC-002T CY23FP12OI-002 CY23FP12OI-002T

Cypress Semiconductor, Corp.
Part No. CY23FP12-002 CY3692 CY23FP12OC-002 CY23FP12OC-002T CY23FP12OI-002 CY23FP12OI-002T
OCR Text ...CLKA1 will become complimentary pairs. Generates an inverted clock on the CLKA2 output. When this option is programmed, CLKA2 and CLKA3 will become complimentary pairs. Generates an inverted clock on the CLKA4 output. When this option is pr...
Description 23FP SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 5.30 MM, SSOP-28
200-MHz Field Programmable Zero Delay Buffer

File Size 207.98K  /  10 Page

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    LATTICEXP2

Lattice Semiconductor
Part No. LATTICEXP2
OCR Text ...lock encompasses two pios (pio pairs) with their respective sysi o buffers. the sysio buffers of the latticexp2 devices are arranged into eight banks, allowing the implementation of a wide variety of i/o standards. pio pairs on the left ...
Description FPGA fabric

File Size 1,078.95K  /  92 Page

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