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IDT
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| Part No. |
IDT72T18105
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| OCR Text |
... the oe input used to provide three-state control of the outputs, qn. the output port can be selected for either 2.5v lvttl or hstl operation, this operation is selected by the state of the rhstl input during a master reset. an output ena... |
| Description |
(IDT72T18xxx) HIGH-SPEED TeraSync FIFO 18-BIT/9-BIT CONFIGURATIONS
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| File Size |
569.75K /
55 Page |
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XILINX
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| Part No. |
XC4006E
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| OCR Text |
...tors
During configuration, the three mode pins, M0, M1, and M2, have weak pull-up resistors. For the most popular configuration mode, Slave...Output Propagation Delays Clock (OK) to Pad (fast) same (slew rate limited) Output (O) to Pad (fast)... |
| Description |
XC4000E and XC4000X Series Field Programmable Gate Arrays
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| File Size |
22.15K /
5 Page |
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it Online |
Download Datasheet |
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EXAR[Exar Corporation]
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| Part No. |
XR16V2650IM XR16V2650_07 XR16V2650 XR16V2650IL32
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| OCR Text |
...o a logic 1. INTA is set to the three state mode and OP2A# output HIGH when MCR[3] is set to a logic 0 (default). See MCR[3]. UART channel B Interrupt output. The output state is defined by the user through the software setting of MCR[3]. I... |
| Description |
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO
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| File Size |
467.88K /
47 Page |
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it Online |
Download Datasheet |
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EXAR[Exar Corporation]
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| Part No. |
XR16V2651IM XR16V2651_07 XR16V2651 XR16V2651IL32
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| OCR Text |
...o a logic 1. INTA is set to the three state mode and OP2A# to a logic 1 when MCR[3] is set to a logic 0. See MCR[3]. When 16/68# pin is LOW for Motorola bus interface, this output becomes device interrupt output (active low, open drain). An... |
| Description |
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE
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| File Size |
499.21K /
51 Page |
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it Online |
Download Datasheet |
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