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				Holtek Semiconductor In...
Part No.	HT7344-1 HT7321-1 HT7323-1 HT7325-1 HT7327-1 HT7330-1 HT7333-1
OCR Text	... 1ma i out 100ma 45 90 mv v dif dropout voltage i out =1ma, v out change=2% (note) 6 15 mv i out =30ma, v out change=2% (note) 120 300 i ss quiescent current i out =0ma 2.5 4.0 ua v in v out v out line regulation (v out +2v) ...
Description	30V, 250mA TinyPowerTM LDO
File Size	828.14K / 16 Page	View it Online	Download Datasheet

				Integrated Device Techn...
Part No.	9DML0441
OCR Text	...00mhz low-power hcsl (lp-hcsl) dif pairs ? 9dml0441 default z out = 100 ? ? 9dml0451 default z out = 85 ? ? 9dml04p1 factory programmable defaults ? see an-891 for easy termination to other logic levels features ? direct connection to ...
Description	2:4 3.3V PCIe Clock Mux
File Size	227.48K / 10 Page	View it Online	Download Datasheet

				Silicon Laboratories
Part No.	CY505YC64DT CY505YC64DTT
OCR Text	... srct0/dot96t srcc0/dot96c o, dif 100 mhz differential serial refe rence clocks/fixed 96 mhz clock output. selected via i2c default is src0. 15 vss_io gnd ground for pll2. 16 vdd_pll3 pwr 3.3v power supply for pll3 17, 18 srct1/lcdt_1...
Description	Clock Generator for Intel?Broadwater Chipset
File Size	179.08K / 24 Page	View it Online	Download Datasheet

				Integrated Device Techn...
Part No.	9DBV0441 9DBV0441AKILF
OCR Text	...4 ? 1-200hz low-power (lp) hcsl dif pairs w/z o =100 ? key specifications ? dif cycle-to-cycle jitter <50ps ? dif output-to-output skew <50ps ? dif additive phase jitter is <100fs rms for pcie gen3 ? dif additive phase jitter <300fs rms...
Description	4 O/P 1.8V PCIe Gen1-2-3 ZDB/FOB
File Size	207.27K / 17 Page	View it Online	Download Datasheet

				Integrated Device Techn...
Part No.	9DBV0431 9DBV0431AKILF 9DBV0431AKILFT 9DBV0431AKLF 9DBV0431AKLFT 9DBV0431-16
OCR Text	...4 - 1-200hz low-power (lp) hcsl dif pairs w/z o =100ohms key specifications ? dif cycle-to-cycle jitter <50ps ? dif output-to-output skew <50ps ? dif additive phase jitter is <100fs rms for pcie gen3 ? dif additive phase jitter <300fs ...
Description	4-output 1.8V PCIe Gen1-2-3 Zero-delay/Fanout Buffer (ZDB/FOB)
File Size	204.60K / 16 Page	View it Online	Download Datasheet

				Integrated Circuit Syst... Integrated Device Techn...
Part No.	9DBV0431
OCR Text	...4 - 1-200hz low-power (lp) hcsl dif pairs w/z o =100ohms key specifications ? dif cycle-to-cycle jitter <50ps ? dif output-to-output skew <50ps ? dif additive phase jitter is <100fs rms for pcie gen3 ? dif additive phase jitter <300fs ...
Description	LP-HCSL outputs save 8 resistors; minimal board space and BOM cost HCSL compatible differential input
File Size	208.15K / 17 Page	View it Online	Download Datasheet

				Integrated Device Techn...
Part No.	9DBV0241 9DBV0241AKILFT 9DBV0241AKLF 9DBV0241AKLFT 9DBV0241-16
OCR Text	... - 1-200mhz low-power (lp) hcsl dif pairs w/z o =100 ? key specifications ? dif cycle-to-cycle jitter <50ps ? dif output-to-output skew <50ps ? dif additive phase jitter is <100fs rms for pcie gen3 ? dif additive phase jitter <300fs rms...
Description	2-Output 1.8V PCIe Gen1/2/3 Zero Delay
File Size	309.27K / 17 Page	View it Online	Download Datasheet

				Integrated Device Techn...
Part No.	9DBV0241
OCR Text	...power hcsl-compatible (lp-hcsl) dif pairs w/z o =100 ? key specifications ? dif cycle-to-cycle jitter <50ps ? dif output-to-output skew <50ps ? dif additive phase jitter is <100fs rms for pcie gen3 ? dif additive phase jitter <300fs rms (...
Description	SMBus-selectable features
File Size	307.15K / 17 Page	View it Online	Download Datasheet

				Integrated Circuit Syst...
Part No.	9DBV0241
OCR Text	...power hcsl-compatible (lp-hcsl) dif pairs w/z o =100 ? key specifications ? dif cycle-to-cycle jitter <50ps ? dif output-to-output skew <50ps ? dif additive phase jitter is <100fs rms for pcie gen3 ? dif additive phase jitter <300fs rms (...
Description	slew rate for each output
File Size	307.06K / 17 Page	View it Online	Download Datasheet

				Integrated Circuit Syst... Integrated Device Techn...
Part No.	9DBV0231
OCR Text	... ? 1-200mhz low-power (lp) hcsl dif pairs key specifications ? dif cycle-to-cycle jitter <50ps ? dif output-to-output skew <50ps ? dif additive phase jitter is <100fs rms for pcie gen3 ? dif additive phase jitter <300fs rms (12k-20mhz) ...
Description	slew rate for each output SMBus-selectable features
File Size	302.62K / 17 Page	View it Online	Download Datasheet

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