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  lvcmos lvttl-to-lvds Datasheet PDF File

For lvcmos lvttl-to-lvds Found Datasheets File :: 1476    Search Time::8.328ms    
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    ICS874004 ICS874004AG ICS874004AGT

ICST[Integrated Circuit Systems]
Part No. ICS874004 ICS874004AG ICS874004AGT
OCR Text ...rs and the outputs are enabled. lvcmos/LVTTL interface levels. Pullup/ Selects PLL Band Width input. lvcmos/LVTTL interface levels. Pulldown Analog supply pin. Pulldown Frequency select pin. lvcmos/LVTTL interface levels. Core supply pin. O...
Description PCI EXPRESS JITTER ATTENUATOR
High Performance Differential-to HCSL Jitter Attenuator for PCI Express?

File Size 173.99K  /  10 Page

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    NB7L14MNTXG NB7L14MNG

ON Semiconductor
Part No. NB7L14MNTXG NB7L14MNG
OCR Text ...rds, such as lvpecl, cml, lvds, lvcmos or lvttl logic levels. the v refac reference output can be used to rebias capacitor ? coupled differential or single ? ended input signals. the 1:4 fanout design was optimized for low output skew appl...
Description 2.5V / 3.3V 7GHz/10Gbps Differential 1:4 LVPECL Fanout Buffer
   2.5V / 3.3V 7GHz/10Gbps Differential 1:4 LVPECL Fanout Buffer

File Size 141.81K  /  9 Page

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    MAX9160 MAX9160AEUI MAX9160EUI

ON Semiconductor
MAXIM[Maxim Integrated Products]
Part No. MAX9160 MAX9160AEUI MAX9160EUI
OCR Text lvcmos Input to 14 LVTTL/lvcmos Output Clock Driver General Description The MAX9160 125MHz, 14-port LVTTL/lvcmos clock driver repeats the selected LVDS or LVTTL/lvcmos input on two output banks. Each bank consists of seven LVTTL/lvcmos se...
Description LVDS or LVTTL/lvcmos Input to 14 LVTTL/lvcmos Output Clock Driver LVDSLVTTL/lvcmos输入4LVTTL/lvcmos输出的时钟驱动器

File Size 345.02K  /  13 Page

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    NB6L11DT NB6L11DG

Rectron Semiconductor
Part No. NB6L11DT NB6L11DG
OCR Text ...t accept lvnecl, lvpecl, lvttl, lvcmos, cml, or lvds. the outputs are 800 mv ecl signals. features ? input clock frequency 6 ghz ? input data rate 6 gb/s ? low 14 ma typical power supply current ? 150 ps typical propagation delay ? ...
Description 2.5 V/3.3 V Multilevel Input to Differential LVPECL/LVNECL 1:2 Clock or Data Fanout Buffer/Translator 6L SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8

File Size 358.40K  /  13 Page

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    ICS85356AGI ICS85356AGILF ICS85356AGILFT ICS85356AGIT ICS85356AMI ICS85356AMIT ICS85356 ICS85356I

Z-Communications, Inc.
ICST[Integrated Circuit Systems]
Part No. ICS85356AGI ICS85356AGILF ICS85356AGILFT ICS85356AGIT ICS85356AMI ICS85356AMIT ICS85356 ICS85356I
OCR Text ...ace levels. Clock select input. lvcmos / LVTTL interface levels. Common select input. lvcmos / LVTTL interface levels. Clock select input. lvcmos / LVTTL interface levels. Differential output pairs. LVPECL interface levels. TABLE 1. PIN ...
Description 2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER 2:1,差分至3.3V双的LVPECL / ECL时钟复用

File Size 235.50K  /  14 Page

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    NB7L86M

ON Semiconductor
Part No. NB7L86M
OCR Text ...ve ecl), lvpecl (positive ecl), lvcmos, lvttl, cml, or lvds. the differential 16 ma cml output provides matching internal 50 termination, and 400 mv output swing when externally terminated 50 to v cc . the device is housed in a low ...
Description 2.5V/3.3V 12 Gb/s Differential Clock/Data SmartGate with CML Output and Internal Termination(带CML输出和内部终端的2.5V/3.3V 12Gb/s差分时钟/数据智能门极)

File Size 1,454.67K  /  12 Page

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    Maxim
Part No. MAX9211 MAX9213 MAX9215 MAX9209
OCR Text ...9215 serialize 21 bits of LVTTL/lvcmos parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides timing for deserialization. The MAX9209/MAX9211/MAX9213/MAX9215 feature programmable DC balance, which ...
Description Programmable DC-Balance 21-Bit Serializers

File Size 412.04K  /  19 Page

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    ICS8442 ICS8442AY ICS8442AYLF ICS8442AYLFT ICS8442AYT

Integrated Circuit Syst...
Integrated Circuit Solution Inc
ICST[Integrated Circuit Systems]
Part No. ICS8442 ICS8442AY ICS8442AYLF ICS8442AYLFT ICS8442AYT
OCR Text ...crystal oscillator interface or lvcmos/LVTTL TEST_CLK * Output frequency range: 31.25MHz to 700MHz * Crystal input frequency range: 10MHz to 25MHz * VCO range: 250MHz to 700MHz * Parallel or serial interface for programming counter and outp...
Description 700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER
Hex schmitt-trigger inverters 14-SOIC 0 to 70

File Size 272.09K  /  15 Page

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    NBSG16M

ON Semiconductor
Part No. NBSG16M
OCR Text ... lv pecl (positive ecl), lvttl, lvcmos, cml, or lvds. the cm l output structure contains internal 50 source termination resistor to v cc . the device generates 400 mv output amplitude with 50 receiver resistor to v cc . the v bb pi...
Description 2.5V/3.3VMultilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer(2.5V/3.3V多级输入到CML时钟/数据接收驱动转换缓冲 2.5V/3.3V的多级白血病的输入时钟/数据接收驱动翻译缓冲区(2.5V/3.3V的多级输入到白血病时数据接收驱动转换缓冲器)

File Size 152.26K  /  11 Page

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